move RAVEN FW into Validation-VP repo
This commit is contained in:
parent
0de438dc52
commit
d2cb78724a
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TARGET = raven_spn
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C_SRCS = $(wildcard src/*.c) $(BSP_BASE)/drivers/fe300prci/fe300prci_driver.c $(BSP_BASE)/drivers/plic/plic_driver.c
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CXX_SRCS = $(wildcard src/*.cpp)
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HEADERS = $(wildcard src/*.h)
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CFLAGS = -g -fno-builtin-printf -DUSE_PLIC -I./src
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CXXFLAGS = -fno-use-cxa-atexit
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LDFLAGS += -g -lstdc++ -fno-use-cxa-atexit -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -mcmodel=medany
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BOARD=freedom-e300-hifive1
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LINK_TARGET=flash
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RISCV_ARCH=rv32imac
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RISCV_ABI=ilp32
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TOOL_DIR=/opt/shared/riscv/tools/Ubuntu/riscv64-unknown-elf-gcc-8.3.0-2020.04.1-x86_64-linux-ubuntu14/bin
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BSP_BASE = ./bsp
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include $(BSP_BASE)/env/common.mk
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.PHONY: all
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all: $(TARGET).dump
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$(TARGET).dump: $(TARGET)
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$(TOOL_DIR)/$(TRIPLET)-objdump -d -S -C $< > $@
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@ -1,163 +0,0 @@
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// See LICENSE for license details.
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#include "sifive/devices/clic.h"
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#include "clic/clic_driver.h"
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#include "platform.h"
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#include "encoding.h"
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#include <string.h>
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void volatile_memzero(uint8_t * base, unsigned int size) {
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volatile uint8_t * ptr;
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for (ptr = base; ptr < (base + size); ptr++){
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*ptr = 0;
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}
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}
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// Note that there are no assertions or bounds checking on these
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// parameter values.
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void clic_init (
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clic_instance_t * this_clic,
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uintptr_t hart_addr,
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interrupt_function_ptr_t* vect_table,
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interrupt_function_ptr_t default_handler,
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uint32_t num_irq,
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uint32_t num_config_bits
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)
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{
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this_clic->hart_addr= hart_addr;
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this_clic->vect_table= vect_table;
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this_clic->num_config_bits= num_config_bits;
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//initialize vector table
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for(int i=0;i++;i<num_irq) {
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this_clic->vect_table[i] = default_handler;
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}
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//set base vectors
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write_csr(mtvt, vect_table);
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//clear all interrupt enables and pending
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volatile_memzero((uint8_t*)(this_clic->hart_addr+CLIC_INTIE), num_irq);
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volatile_memzero((uint8_t*)(this_clic->hart_addr+CLIC_INTIP), num_irq);
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//clear nlbits and nvbits; all interrupts trap to level 15
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*(volatile uint8_t*)(this_clic->hart_addr+CLIC_CFG)=0;
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}
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void clic_install_handler (clic_instance_t * this_clic, uint32_t source, interrupt_function_ptr_t handler) {
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this_clic->vect_table[source] = handler;
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}
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void clic_enable_interrupt (clic_instance_t * this_clic, uint32_t source) {
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*(volatile uint8_t*)(this_clic->hart_addr+CLIC_INTIE+source) = 1;
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}
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void clic_disable_interrupt (clic_instance_t * this_clic, uint32_t source){
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*(volatile uint8_t*)(this_clic->hart_addr+CLIC_INTIE+source) = 0;
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}
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void clic_set_pending(clic_instance_t * this_clic, uint32_t source){
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*(volatile uint8_t*)(this_clic->hart_addr+CLIC_INTIP+source) = 1;
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}
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void clic_clear_pending(clic_instance_t * this_clic, uint32_t source){
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*(volatile uint8_t*)(this_clic->hart_addr+CLIC_INTIP+source) = 0;
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}
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void clic_set_intcfg (clic_instance_t * this_clic, uint32_t source, uint32_t intcfg){
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*(volatile uint8_t*)(this_clic->hart_addr+CLIC_INTCFG+source) = intcfg;
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}
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uint8_t clic_get_intcfg (clic_instance_t * this_clic, uint32_t source){
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return *(volatile uint8_t*)(this_clic->hart_addr+CLIC_INTCFG+source);
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}
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void clic_set_cliccfg (clic_instance_t * this_clic, uint32_t cfg){
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*(volatile uint8_t*)(this_clic->hart_addr+CLIC_CFG) = cfg;
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}
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uint8_t clic_get_cliccfg (clic_instance_t * this_clic){
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return *(volatile uint8_t*)(this_clic->hart_addr+CLIC_CFG);
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}
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//sets an interrupt level based encoding of nmbits, nlbits
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uint8_t clic_set_int_level( clic_instance_t * this_clic, uint32_t source, uint8_t level) {
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//extract nlbits
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uint8_t nlbits = clic_get_cliccfg(this_clic);
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nlbits = (nlbits >>1) & 0x7;
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//shift level right to mask off unused bits
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level = level>>((this_clic->num_config_bits)-nlbits); //plus this_clic->nmbits which is always 0 for now.
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//shift level into correct bit position
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level = level << (8-this_clic->num_config_bits) + (this_clic->num_config_bits - nlbits);
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//write to clicintcfg
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uint8_t current_intcfg = clic_get_intcfg(this_clic, source);
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clic_set_intcfg(this_clic, source, (current_intcfg | level));
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return level;
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}
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//gets an interrupt level based encoding of nmbits, nlbits
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uint8_t clic_get_int_level( clic_instance_t * this_clic, uint32_t source) {
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uint8_t level;
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level = clic_get_intcfg(this_clic, source);
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//extract nlbits
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uint8_t nlbits = clic_get_cliccfg(this_clic);
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nlbits = (nlbits >>1) & 0x7;
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//shift level
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level = level >> (8-(this_clic->num_config_bits));
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//shift level right to mask off priority bits
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level = level>>(this_clic->num_config_bits-nlbits); //this_clic->nmbits which is always 0 for now.
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return level;
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}
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//sets an interrupt priority based encoding of nmbits, nlbits
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uint8_t clic_set_int_priority( clic_instance_t * this_clic, uint32_t source, uint8_t priority) {
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//priority bits = num_config_bits - nlbits
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//extract nlbits
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uint8_t nlbits = clic_get_cliccfg(this_clic);
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nlbits = (nlbits >>1) & 0x7;
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uint8_t priority_bits = this_clic->num_config_bits-nlbits;
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if(priority_bits = 0) {
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//no bits to set
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return 0;
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}
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//mask off unused bits
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priority = priority >> (8-priority_bits);
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//shift into the correct bit position
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priority = priority << (8-(this_clic->num_config_bits));
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//write to clicintcfg
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uint8_t current_intcfg = clic_get_intcfg(this_clic, source);
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clic_set_intcfg(this_clic, source, (current_intcfg | priority));
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return current_intcfg;
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}
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//gets an interrupt priority based encoding of nmbits, nlbits
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uint8_t clic_get_int_priority( clic_instance_t * this_clic, uint32_t source) {
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uint8_t priority;
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priority = clic_get_intcfg(this_clic, source);
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//extract nlbits
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uint8_t nlbits = clic_get_cliccfg(this_clic);
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nlbits = (nlbits >>1) & 0x7;
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//shift left to mask off level bits
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priority = priority << nlbits;
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//shift priority
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priority = priority >> (8-((this_clic->num_config_bits)+nlbits));
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return priority;
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}
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// See LICENSE file for licence details
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#ifndef PLIC_DRIVER_H
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#define PLIC_DRIVER_H
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__BEGIN_DECLS
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#include "platform.h"
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typedef void (*interrupt_function_ptr_t) (void);
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typedef struct __clic_instance_t
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{
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uintptr_t hart_addr;
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interrupt_function_ptr_t* vect_table;
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uint32_t num_config_bits;
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uint32_t num_sources;
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} clic_instance_t;
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// Note that there are no assertions or bounds checking on these
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// parameter values.
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void clic_init (clic_instance_t * this_clic, uintptr_t hart_addr, interrupt_function_ptr_t* vect_table, interrupt_function_ptr_t default_handler, uint32_t num_irq,uint32_t num_config_bits);
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void clic_install_handler (clic_instance_t * this_clic, uint32_t source, interrupt_function_ptr_t handler);
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void clic_enable_interrupt (clic_instance_t * this_clic, uint32_t source);
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void clic_disable_interrupt (clic_instance_t * this_clic, uint32_t source);
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void clic_set_pending(clic_instance_t * this_clic, uint32_t source);
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void clic_clear_pending(clic_instance_t * this_clic, uint32_t source);
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void clic_set_intcfg (clic_instance_t * this_clic, uint32_t source, uint32_t intcfg);
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uint8_t clic_get_intcfg (clic_instance_t * this_clic, uint32_t source);
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void clic_set_cliccfg (clic_instance_t * this_clic, uint32_t cfg);
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uint8_t clic_get_cliccfg (clic_instance_t * this_clic);
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//sets an interrupt level based encoding of nmbits, nlbits
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uint8_t clic_set_int_level( clic_instance_t * this_clic, uint32_t source, uint8_t level);
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//get an interrupt level based encoding of nmbits, nlbits
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uint8_t clic_get_int_level( clic_instance_t * this_clic, uint32_t source);
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//sets an interrupt priority based encoding of nmbits, nlbits
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uint8_t clic_set_int_priority( clic_instance_t * this_clic, uint32_t source, uint8_t priority);
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//sets an interrupt priority based encoding of nmbits, nlbits
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uint8_t clic_get_int_priority( clic_instance_t * this_clic, uint32_t source);
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__END_DECLS
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#endif
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// See LICENSE file for license details
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#include "platform.h"
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#ifdef PRCI_CTRL_ADDR
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#include "fe300prci/fe300prci_driver.h"
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#include <unistd.h>
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#define rdmcycle(x) { \
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uint32_t lo, hi, hi2; \
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__asm__ __volatile__ ("1:\n\t" \
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"csrr %0, mcycleh\n\t" \
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"csrr %1, mcycle\n\t" \
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"csrr %2, mcycleh\n\t" \
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"bne %0, %2, 1b\n\t" \
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: "=r" (hi), "=r" (lo), "=r" (hi2)) ; \
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*(x) = lo | ((uint64_t) hi << 32); \
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}
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uint32_t PRCI_measure_mcycle_freq(uint32_t mtime_ticks, uint32_t mtime_freq)
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{
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uint32_t start_mtime = CLINT_REG(CLINT_MTIME);
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uint32_t end_mtime = start_mtime + mtime_ticks + 1;
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// Make sure we won't get rollover.
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while (end_mtime < start_mtime){
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start_mtime = CLINT_REG(CLINT_MTIME);
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end_mtime = start_mtime + mtime_ticks + 1;
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}
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// Don't start measuring until mtime edge.
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uint32_t tmp = start_mtime;
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do {
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start_mtime = CLINT_REG(CLINT_MTIME);
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} while (start_mtime == tmp);
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uint64_t start_mcycle;
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rdmcycle(&start_mcycle);
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while (CLINT_REG(CLINT_MTIME) < end_mtime) ;
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uint64_t end_mcycle;
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rdmcycle(&end_mcycle);
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uint32_t difference = (uint32_t) (end_mcycle - start_mcycle);
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uint64_t freq = ((uint64_t) difference * mtime_freq) / mtime_ticks;
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return (uint32_t) freq & 0xFFFFFFFF;
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}
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void PRCI_use_hfrosc(int div, int trim)
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{
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// Make sure the HFROSC is running at its default setting
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// It is OK to change this even if we are running off of it.
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PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1));
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while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0);
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PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1);
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}
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void PRCI_use_pll(int refsel, int bypass,
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int r, int f, int q, int finaldiv,
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int hfroscdiv, int hfrosctrim)
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{
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// Ensure that we aren't running off the PLL before we mess with it.
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if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) {
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// Make sure the HFROSC is running at its default setting
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PRCI_use_hfrosc(4, 16);
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}
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// Set PLL Source to be HFXOSC if desired.
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uint32_t config_value = 0;
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config_value |= PLL_REFSEL(refsel);
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if (bypass) {
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// Bypass
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config_value |= PLL_BYPASS(1);
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PRCI_REG(PRCI_PLLCFG) = config_value;
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// If we don't have an HFXTAL, this doesn't really matter.
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// Set our Final output divide to divide-by-1:
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PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
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} else {
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// To overclock, use the hfrosc
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if (hfrosctrim >= 0 && hfroscdiv >= 0) {
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PRCI_use_hfrosc(hfroscdiv, hfrosctrim);
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}
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// Set DIV Settings for PLL
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// (Legal values of f_REF are 6-48MHz)
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// Set DIVR to divide-by-2 to get 8MHz frequency
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// (legal values of f_R are 6-12 MHz)
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config_value |= PLL_BYPASS(1);
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config_value |= PLL_R(r);
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// Set DIVF to get 512Mhz frequncy
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// There is an implied multiply-by-2, 16Mhz.
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// So need to write 32-1
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// (legal values of f_F are 384-768 MHz)
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config_value |= PLL_F(f);
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// Set DIVQ to divide-by-2 to get 256 MHz frequency
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// (legal values of f_Q are 50-400Mhz)
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config_value |= PLL_Q(q);
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// Set our Final output divide to divide-by-1:
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if (finaldiv == 1){
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PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
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} else {
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PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV(finaldiv-1));
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}
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PRCI_REG(PRCI_PLLCFG) = config_value;
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// Un-Bypass the PLL.
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PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1);
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// Wait for PLL Lock
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// Note that the Lock signal can be glitchy.
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// Need to wait 100 us
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// RTC is running at 32kHz.
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// So wait 4 ticks of RTC.
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uint32_t now = CLINT_REG(CLINT_MTIME);
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while (CLINT_REG(CLINT_MTIME) - now < 4) ;
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// Now it is safe to check for PLL Lock
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while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0);
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}
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// Switch over to PLL Clock source
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PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1);
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// If we're running off HFXOSC, turn off the HFROSC to
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// save power.
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if (refsel) {
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PRCI_REG(PRCI_HFROSCCFG) &= ~ROSC_EN(1);
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}
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}
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void PRCI_use_default_clocks()
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{
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// Turn off the LFROSC
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AON_REG(AON_LFROSC) &= ~ROSC_EN(1);
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// Use HFROSC
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PRCI_use_hfrosc(4, 16);
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}
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void PRCI_use_hfxosc(uint32_t finaldiv)
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{
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PRCI_use_pll(1, // Use HFXTAL
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1, // Bypass = 1
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0, // PLL settings don't matter
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0, // PLL settings don't matter
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0, // PLL settings don't matter
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finaldiv,
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-1,
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-1);
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}
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// This is a generic function, which
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// doesn't span the entire range of HFROSC settings.
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// It only adjusts the trim, which can span a hundred MHz or so.
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// This function does not check the legality of the PLL settings
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// at all, and it is quite possible to configure invalid PLL settings
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// this way.
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// It returns the actual measured CPU frequency.
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uint32_t PRCI_set_hfrosctrim_for_f_cpu(uint32_t f_cpu, PRCI_freq_target target )
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{
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uint32_t hfrosctrim = 0;
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uint32_t hfroscdiv = 4;
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uint32_t prev_trim = 0;
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// In this function we use PLL settings which
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// will give us a 32x multiplier from the output
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// of the HFROSC source to the output of the
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// PLL. We first measure our HFROSC to get the
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// right trim, then finally use it as the PLL source.
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// We should really check here that the f_cpu
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// requested is something in the limit of the PLL. For
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// now that is up to the user.
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// This will undershoot for frequencies not divisible by 16.
|
||||
uint32_t desired_hfrosc_freq = (f_cpu/ 16);
|
||||
|
||||
PRCI_use_hfrosc(hfroscdiv, hfrosctrim);
|
||||
|
||||
// Ignore the first run (for icache reasons)
|
||||
uint32_t cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ);
|
||||
|
||||
cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ);
|
||||
uint32_t prev_freq = cpu_freq;
|
||||
|
||||
while ((cpu_freq < desired_hfrosc_freq) && (hfrosctrim < 0x1F)){
|
||||
prev_trim = hfrosctrim;
|
||||
prev_freq = cpu_freq;
|
||||
hfrosctrim ++;
|
||||
PRCI_use_hfrosc(hfroscdiv, hfrosctrim);
|
||||
cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ);
|
||||
}
|
||||
|
||||
// We couldn't go low enough
|
||||
if (prev_freq > desired_hfrosc_freq){
|
||||
PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
|
||||
cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ);
|
||||
return cpu_freq;
|
||||
}
|
||||
|
||||
// We couldn't go high enough
|
||||
if (cpu_freq < desired_hfrosc_freq){
|
||||
PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
|
||||
cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ);
|
||||
return cpu_freq;
|
||||
}
|
||||
|
||||
// Check for over/undershoot
|
||||
switch(target) {
|
||||
case(PRCI_FREQ_CLOSEST):
|
||||
if ((desired_hfrosc_freq - prev_freq) < (cpu_freq - desired_hfrosc_freq)) {
|
||||
PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
|
||||
} else {
|
||||
PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim);
|
||||
}
|
||||
break;
|
||||
case(PRCI_FREQ_UNDERSHOOT):
|
||||
PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
|
||||
break;
|
||||
default:
|
||||
PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim);
|
||||
}
|
||||
|
||||
cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ);
|
||||
return cpu_freq;
|
||||
|
||||
}
|
||||
|
||||
#endif
|
|
@ -1,79 +0,0 @@
|
|||
// See LICENSE file for license details
|
||||
|
||||
#ifndef _FE300PRCI_DRIVER_H_
|
||||
#define _FE300PRCI_DRIVER_H_
|
||||
|
||||
__BEGIN_DECLS
|
||||
|
||||
#include <unistd.h>
|
||||
|
||||
typedef enum prci_freq_target {
|
||||
|
||||
PRCI_FREQ_OVERSHOOT,
|
||||
PRCI_FREQ_CLOSEST,
|
||||
PRCI_FREQ_UNDERSHOOT
|
||||
|
||||
} PRCI_freq_target;
|
||||
|
||||
/* Measure and return the approximate frequency of the
|
||||
* CPU, as given by measuring the mcycle counter against
|
||||
* the mtime ticks.
|
||||
*/
|
||||
uint32_t PRCI_measure_mcycle_freq(uint32_t mtime_ticks, uint32_t mtime_freq);
|
||||
|
||||
/* Safely switch over to the HFROSC using the given div
|
||||
* and trim settings.
|
||||
*/
|
||||
void PRCI_use_hfrosc(int div, int trim);
|
||||
|
||||
/* Safely switch over to the 16MHz HFXOSC,
|
||||
* applying the finaldiv clock divider (1 is the lowest
|
||||
* legal value).
|
||||
*/
|
||||
void PRCI_use_hfxosc(uint32_t finaldiv);
|
||||
|
||||
/* Safely switch over to the PLL using the given
|
||||
* settings.
|
||||
*
|
||||
* Note that not all combinations of the inputs are actually
|
||||
* legal, and this function does not check for their
|
||||
* legality ("safely" means that this function won't turn off
|
||||
* or glitch the clock the CPU is actually running off, but
|
||||
* doesn't protect against you making it too fast or slow.)
|
||||
*/
|
||||
|
||||
void PRCI_use_pll(int refsel, int bypass,
|
||||
int r, int f, int q, int finaldiv,
|
||||
int hfroscdiv, int hfrosctrim);
|
||||
|
||||
/* Use the default clocks configured at reset.
|
||||
* This is ~16Mhz HFROSC and turns off the LFROSC
|
||||
* (on the current FE310 Dev Platforms, an external LFROSC is
|
||||
* used as it is more power efficient).
|
||||
*/
|
||||
void PRCI_use_default_clocks();
|
||||
|
||||
/* This routine will adjust the HFROSC trim
|
||||
* while using HFROSC as the clock source,
|
||||
* measure the resulting frequency, then
|
||||
* use it as the PLL clock source,
|
||||
* in an attempt to get over, under, or close to the
|
||||
* requested frequency. It returns the actual measured
|
||||
* frequency.
|
||||
*
|
||||
* Note that the requested frequency must be within the
|
||||
* range supported by the PLL so not all values are
|
||||
* achievable with this function, and not all
|
||||
* are guaranteed to actually work. The PLL
|
||||
* is rated higher than the hardware.
|
||||
*
|
||||
* There is no check on the desired f_cpu frequency, it
|
||||
* is up to the user to specify something reasonable.
|
||||
*/
|
||||
|
||||
uint32_t PRCI_set_hfrosctrim_for_f_cpu(uint32_t f_cpu, PRCI_freq_target target);
|
||||
|
||||
__END_DECLS
|
||||
|
||||
#endif
|
||||
|
|
@ -1,122 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#include "sifive/devices/plic.h"
|
||||
#include "plic/plic_driver.h"
|
||||
#include "platform.h"
|
||||
#include "encoding.h"
|
||||
#include <string.h>
|
||||
|
||||
|
||||
// Note that there are no assertions or bounds checking on these
|
||||
// parameter values.
|
||||
|
||||
void volatile_memzero(uint8_t * base, unsigned int size)
|
||||
{
|
||||
volatile uint8_t * ptr;
|
||||
for (ptr = base; ptr < (base + size); ptr++){
|
||||
*ptr = 0;
|
||||
}
|
||||
}
|
||||
|
||||
void PLIC_init (
|
||||
plic_instance_t * this_plic,
|
||||
uintptr_t base_addr,
|
||||
uint32_t num_sources,
|
||||
uint32_t num_priorities,
|
||||
uint32_t target_hartid
|
||||
)
|
||||
{
|
||||
|
||||
this_plic->base_addr = base_addr;
|
||||
this_plic->num_sources = num_sources;
|
||||
this_plic->num_priorities = num_priorities;
|
||||
this_plic->target_hartid = target_hartid;
|
||||
|
||||
// Disable all interrupts (don't assume that these registers are reset).
|
||||
volatile_memzero((uint8_t*) (this_plic->base_addr +
|
||||
PLIC_ENABLE_OFFSET +
|
||||
(this_plic->target_hartid << PLIC_ENABLE_SHIFT_PER_TARGET)),
|
||||
(num_sources + 8) / 8);
|
||||
|
||||
// Set all priorities to 0 (equal priority -- don't assume that these are reset).
|
||||
volatile_memzero ((uint8_t *)(this_plic->base_addr +
|
||||
PLIC_PRIORITY_OFFSET),
|
||||
(num_sources + 1) << PLIC_PRIORITY_SHIFT_PER_SOURCE);
|
||||
|
||||
// Set the threshold to 0.
|
||||
volatile plic_threshold* threshold = (plic_threshold*)
|
||||
(this_plic->base_addr +
|
||||
PLIC_THRESHOLD_OFFSET +
|
||||
(this_plic->target_hartid << PLIC_THRESHOLD_SHIFT_PER_TARGET));
|
||||
|
||||
*threshold = 0;
|
||||
|
||||
}
|
||||
|
||||
void PLIC_set_threshold (plic_instance_t * this_plic,
|
||||
plic_threshold threshold){
|
||||
|
||||
volatile plic_threshold* threshold_ptr = (plic_threshold*) (this_plic->base_addr +
|
||||
PLIC_THRESHOLD_OFFSET +
|
||||
(this_plic->target_hartid << PLIC_THRESHOLD_SHIFT_PER_TARGET));
|
||||
|
||||
*threshold_ptr = threshold;
|
||||
|
||||
}
|
||||
|
||||
|
||||
void PLIC_enable_interrupt (plic_instance_t * this_plic, plic_source source){
|
||||
|
||||
volatile uint8_t * current_ptr = (volatile uint8_t *)(this_plic->base_addr +
|
||||
PLIC_ENABLE_OFFSET +
|
||||
(this_plic->target_hartid << PLIC_ENABLE_SHIFT_PER_TARGET) +
|
||||
(source >> 3));
|
||||
uint8_t current = *current_ptr;
|
||||
current = current | ( 1 << (source & 0x7));
|
||||
*current_ptr = current;
|
||||
|
||||
}
|
||||
|
||||
void PLIC_disable_interrupt (plic_instance_t * this_plic, plic_source source){
|
||||
|
||||
volatile uint8_t * current_ptr = (volatile uint8_t *) (this_plic->base_addr +
|
||||
PLIC_ENABLE_OFFSET +
|
||||
(this_plic->target_hartid << PLIC_ENABLE_SHIFT_PER_TARGET) +
|
||||
(source >> 3));
|
||||
uint8_t current = *current_ptr;
|
||||
current = current & ~(( 1 << (source & 0x7)));
|
||||
*current_ptr = current;
|
||||
|
||||
}
|
||||
|
||||
void PLIC_set_priority (plic_instance_t * this_plic, plic_source source, plic_priority priority){
|
||||
|
||||
if (this_plic->num_priorities > 0) {
|
||||
volatile plic_priority * priority_ptr = (volatile plic_priority *)
|
||||
(this_plic->base_addr +
|
||||
PLIC_PRIORITY_OFFSET +
|
||||
(source << PLIC_PRIORITY_SHIFT_PER_SOURCE));
|
||||
*priority_ptr = priority;
|
||||
}
|
||||
}
|
||||
|
||||
plic_source PLIC_claim_interrupt(plic_instance_t * this_plic){
|
||||
|
||||
volatile plic_source * claim_addr = (volatile plic_source * )
|
||||
(this_plic->base_addr +
|
||||
PLIC_CLAIM_OFFSET +
|
||||
(this_plic->target_hartid << PLIC_CLAIM_SHIFT_PER_TARGET));
|
||||
|
||||
return *claim_addr;
|
||||
|
||||
}
|
||||
|
||||
void PLIC_complete_interrupt(plic_instance_t * this_plic, plic_source source){
|
||||
|
||||
volatile plic_source * claim_addr = (volatile plic_source *) (this_plic->base_addr +
|
||||
PLIC_CLAIM_OFFSET +
|
||||
(this_plic->target_hartid << PLIC_CLAIM_SHIFT_PER_TARGET));
|
||||
*claim_addr = source;
|
||||
|
||||
}
|
||||
|
|
@ -1,52 +0,0 @@
|
|||
// See LICENSE file for licence details
|
||||
|
||||
#ifndef PLIC_DRIVER_H
|
||||
#define PLIC_DRIVER_H
|
||||
|
||||
|
||||
__BEGIN_DECLS
|
||||
|
||||
#include "platform.h"
|
||||
|
||||
typedef struct __plic_instance_t
|
||||
{
|
||||
uintptr_t base_addr;
|
||||
|
||||
uint32_t num_sources;
|
||||
uint32_t num_priorities;
|
||||
uint32_t target_hartid;
|
||||
} plic_instance_t;
|
||||
|
||||
typedef uint32_t plic_source;
|
||||
typedef uint32_t plic_priority;
|
||||
typedef uint32_t plic_threshold;
|
||||
|
||||
void PLIC_init (
|
||||
plic_instance_t * this_plic,
|
||||
uintptr_t base_addr,
|
||||
uint32_t num_sources,
|
||||
uint32_t num_priorities,
|
||||
uint32_t target_hartid
|
||||
);
|
||||
|
||||
void PLIC_set_threshold (plic_instance_t * this_plic,
|
||||
plic_threshold threshold);
|
||||
|
||||
void PLIC_enable_interrupt (plic_instance_t * this_plic,
|
||||
plic_source source);
|
||||
|
||||
void PLIC_disable_interrupt (plic_instance_t * this_plic,
|
||||
plic_source source);
|
||||
|
||||
void PLIC_set_priority (plic_instance_t * this_plic,
|
||||
plic_source source,
|
||||
plic_priority priority);
|
||||
|
||||
plic_source PLIC_claim_interrupt(plic_instance_t * this_plic);
|
||||
|
||||
void PLIC_complete_interrupt(plic_instance_t * this_plic,
|
||||
plic_source source);
|
||||
|
||||
__END_DECLS
|
||||
|
||||
#endif
|
|
@ -1,66 +0,0 @@
|
|||
# See LICENSE for license details.
|
||||
|
||||
ifndef _SIFIVE_MK_COMMON
|
||||
_SIFIVE_MK_COMMON := # defined
|
||||
|
||||
.PHONY: all
|
||||
all: $(TARGET)
|
||||
|
||||
include $(BSP_BASE)/libwrap/libwrap.mk
|
||||
|
||||
ENV_DIR = $(BSP_BASE)/env
|
||||
PLATFORM_DIR = $(ENV_DIR)/$(BOARD)
|
||||
|
||||
ASM_SRCS += $(ENV_DIR)/start.S
|
||||
ASM_SRCS += $(ENV_DIR)/entry.S
|
||||
C_SRCS += $(PLATFORM_DIR)/init.c
|
||||
|
||||
LINKER_SCRIPT := $(PLATFORM_DIR)/$(LINK_TARGET).lds
|
||||
|
||||
INCLUDES += -I$(BSP_BASE)/include
|
||||
INCLUDES += -I$(BSP_BASE)/drivers/
|
||||
INCLUDES += -I$(ENV_DIR)
|
||||
INCLUDES += -I$(PLATFORM_DIR)
|
||||
|
||||
TOOL_DIR ?= $(BSP_BASE)/../toolchain/bin
|
||||
|
||||
LDFLAGS += -T $(LINKER_SCRIPT) -nostartfiles
|
||||
LDFLAGS += -L$(ENV_DIR) --specs=nano.specs
|
||||
|
||||
ASM_OBJS := $(ASM_SRCS:.S=.o)
|
||||
C_OBJS := $(C_SRCS:.c=.o)
|
||||
CXX_OBJS := $(CXX_SRCS:.cpp=.o)
|
||||
|
||||
LINK_OBJS += $(ASM_OBJS) $(C_OBJS) $(CXX_OBJS)
|
||||
LINK_DEPS += $(LINKER_SCRIPT)
|
||||
|
||||
CLEAN_OBJS += $(TARGET) $(LINK_OBJS)
|
||||
|
||||
CFLAGS += -march=$(RISCV_ARCH)
|
||||
CFLAGS += -mabi=$(RISCV_ABI)
|
||||
CFLAGS += -mcmodel=medany
|
||||
|
||||
TRIPLET?=riscv64-unknown-elf
|
||||
CXX=$(TOOL_DIR)/$(TRIPLET)-c++
|
||||
CC=$(TOOL_DIR)/$(TRIPLET)-gcc
|
||||
LD=$(TOOL_DIR)/$(TRIPLET)-gcc
|
||||
AR=$(TOOL_DIR)/$(TRIPLET)-ar
|
||||
|
||||
|
||||
$(TARGET): $(LINK_OBJS) $(LINK_DEPS)
|
||||
$(LD) $(LINK_OBJS) $(LDFLAGS) $(LIBWRAP) -o $@
|
||||
|
||||
$(ASM_OBJS): %.o: %.S $(HEADERS)
|
||||
$(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $<
|
||||
|
||||
$(C_OBJS): %.o: %.c $(HEADERS)
|
||||
$(CC) $(CFLAGS) $(INCLUDES) -include sys/cdefs.h -c -o $@ $<
|
||||
|
||||
$(CXX_OBJS): %.o: %.cpp $(HEADERS)
|
||||
$(CXX) $(CFLAGS) $(CXXFLAGS) $(INCLUDES) -include sys/cdefs.h -c -o $@ $<
|
||||
|
||||
.PHONY: clean
|
||||
clean:
|
||||
rm -f $(CLEAN_OBJS) $(LIBWRAP)
|
||||
|
||||
endif # _SIFIVE_MK_COMMON
|
|
@ -1,161 +0,0 @@
|
|||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
ENTRY( _start )
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 512M
|
||||
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 64K
|
||||
}
|
||||
|
||||
PHDRS
|
||||
{
|
||||
flash PT_LOAD;
|
||||
ram_init PT_LOAD;
|
||||
ram PT_NULL;
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||
|
||||
.init :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.text.unlikely .text.unlikely.*)
|
||||
*(.text.startup .text.startup.*)
|
||||
*(.text .text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.fini)))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
|
||||
.rodata :
|
||||
{
|
||||
*(.rdata)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
} >flash AT>flash :flash
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.lalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data_lma = . );
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data = . );
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = . );
|
||||
PROVIDE( edata = . );
|
||||
|
||||
PROVIDE( _fbss = . );
|
||||
PROVIDE( __bss_start = . );
|
||||
.bss :
|
||||
{
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _end = . );
|
||||
PROVIDE( end = . );
|
||||
|
||||
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
|
||||
{
|
||||
PROVIDE( _heap_end = . );
|
||||
. = __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
} >ram AT>ram :ram
|
||||
}
|
|
@ -1,98 +0,0 @@
|
|||
//See LICENSE for license details.
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include "platform.h"
|
||||
#include "encoding.h"
|
||||
|
||||
#define CPU_FREQ 32000000
|
||||
#define XSTR(x) #x
|
||||
#define STR(x) XSTR(x)
|
||||
|
||||
extern int main(int argc, char** argv);
|
||||
|
||||
unsigned long get_cpu_freq()
|
||||
{
|
||||
return CPU_FREQ;
|
||||
}
|
||||
|
||||
unsigned long get_timer_freq()
|
||||
{
|
||||
return get_cpu_freq();
|
||||
}
|
||||
|
||||
uint64_t get_timer_value()
|
||||
{
|
||||
#if __riscv_xlen == 32
|
||||
while (1) {
|
||||
uint32_t hi = read_csr(mcycleh);
|
||||
uint32_t lo = read_csr(mcycle);
|
||||
if (hi == read_csr(mcycleh))
|
||||
return ((uint64_t)hi << 32) | lo;
|
||||
}
|
||||
#else
|
||||
return read_csr(mcycle);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void uart_init(size_t baud_rate)
|
||||
{
|
||||
UART0_REG(UART_REG_DIV) = (get_cpu_freq() ) / baud_rate - 1;
|
||||
UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
|
||||
}
|
||||
|
||||
|
||||
typedef void (*interrupt_function_ptr_t) (void);
|
||||
interrupt_function_ptr_t localISR[CLIC_NUM_INTERRUPTS] __attribute__((aligned(64)));
|
||||
|
||||
|
||||
void trap_entry(void) __attribute__((interrupt, aligned(64)));
|
||||
void trap_entry(void)
|
||||
{
|
||||
unsigned long mcause = read_csr(mcause);
|
||||
unsigned long mepc = read_csr(mepc);
|
||||
if (mcause & MCAUSE_INT) {
|
||||
localISR[mcause & MCAUSE_CAUSE] ();
|
||||
} else {
|
||||
while(1);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CLIC_DIRECT
|
||||
#else
|
||||
void default_handler(void)__attribute__((interrupt));;
|
||||
#endif
|
||||
void default_handler(void)
|
||||
{
|
||||
puts("default handler\n");
|
||||
while(1);
|
||||
}
|
||||
|
||||
void _init()
|
||||
{
|
||||
#ifndef NO_INIT
|
||||
uart_init(115200);
|
||||
|
||||
puts("core freq at " STR(CPU_FREQ) " Hz\n");
|
||||
|
||||
//initialize vector table
|
||||
int i=0;
|
||||
while(i<CLIC_NUM_INTERRUPTS) {
|
||||
localISR[i++] = default_handler;
|
||||
}
|
||||
|
||||
write_csr(mtvt, localISR);
|
||||
|
||||
#ifdef CLIC_DIRECT
|
||||
write_csr(mtvec, ((unsigned long)&trap_entry | MTVEC_CLIC));
|
||||
#else
|
||||
write_csr(mtvec, ((unsigned long)&trap_entry | MTVEC_CLIC_VECT));
|
||||
#endif
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
void _fini()
|
||||
{
|
||||
}
|
|
@ -1,31 +0,0 @@
|
|||
# JTAG adapter setup
|
||||
adapter_khz 10000
|
||||
|
||||
interface ftdi
|
||||
ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
|
||||
ftdi_vid_pid 0x15ba 0x002a
|
||||
|
||||
ftdi_layout_init 0x0808 0x0a1b
|
||||
ftdi_layout_signal nSRST -oe 0x0200
|
||||
#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
|
||||
ftdi_layout_signal LED -data 0x0800
|
||||
|
||||
set _CHIPNAME riscv
|
||||
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
|
||||
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
|
||||
$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
|
||||
|
||||
# Un-comment these two flash lines if you have a SPI flash and want to write
|
||||
# it.
|
||||
flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
|
||||
init
|
||||
if {[ info exists pulse_srst]} {
|
||||
ftdi_set_signal nSRST 0
|
||||
ftdi_set_signal nSRST z
|
||||
}
|
||||
halt
|
||||
#flash protect 0 64 last off
|
||||
echo "Ready for Remote Connections"
|
|
@ -1,98 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_PLATFORM_H
|
||||
#define _SIFIVE_PLATFORM_H
|
||||
|
||||
// Some things missing from the official encoding.h
|
||||
|
||||
#if __riscv_xlen == 32
|
||||
#define MCAUSE_INT 0x80000000UL
|
||||
#define MCAUSE_CAUSE 0x000003FFUL
|
||||
#else
|
||||
#define MCAUSE_INT 0x8000000000000000UL
|
||||
#define MCAUSE_CAUSE 0x00000000000003FFUL
|
||||
#endif
|
||||
|
||||
#define MTVEC_DIRECT 0X00
|
||||
#define MTVEC_VECTORED 0x01
|
||||
#define MTVEC_CLIC 0x02
|
||||
#define MTVEC_CLIC_VECT 0X03
|
||||
|
||||
|
||||
#include "sifive/const.h"
|
||||
#include "sifive/devices/gpio.h"
|
||||
#include "sifive/devices/clint.h"
|
||||
#include "sifive/devices/clic.h"
|
||||
#include "sifive/devices/pwm.h"
|
||||
#include "sifive/devices/spi.h"
|
||||
#include "sifive/devices/uart.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Platform definitions
|
||||
*****************************************************************************/
|
||||
|
||||
// Memory map
|
||||
#define CLINT_CTRL_ADDR _AC(0x02000000,UL)
|
||||
#define CLIC_HART0_ADDR _AC(0x02800000,UL)
|
||||
#define GPIO_CTRL_ADDR _AC(0x20002000,UL)
|
||||
#define PWM0_CTRL_ADDR _AC(0x20005000,UL)
|
||||
#define RAM_MEM_ADDR _AC(0x80000000,UL)
|
||||
#define RAM_MEM_SIZE _AC(0x10000,UL)
|
||||
#define SPI0_CTRL_ADDR _AC(0x20004000,UL)
|
||||
#define SPI0_MEM_ADDR _AC(0x40000000,UL)
|
||||
#define SPI0_MEM_SIZE _AC(0x20000000,UL)
|
||||
#define TESTBENCH_MEM_ADDR _AC(0x20000000,UL)
|
||||
#define TESTBENCH_MEM_SIZE _AC(0x10000000,UL)
|
||||
//#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL)
|
||||
#define UART0_CTRL_ADDR _AC(0x20000000,UL)
|
||||
|
||||
// IOF masks
|
||||
|
||||
// Interrupt numbers
|
||||
#define RESERVED_INT_BASE 0
|
||||
#define UART0_INT_BASE 1
|
||||
#define EXTERNAL_INT_BASE 2
|
||||
#define SPI0_INT_BASE 6
|
||||
#define GPIO_INT_BASE 7
|
||||
#define PWM0_INT_BASE 23
|
||||
|
||||
// Helper functions
|
||||
#define _REG64(p, i) (*(volatile uint64_t *)((p) + (i)))
|
||||
#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i)))
|
||||
#define _REG16(p, i) (*(volatile uint16_t *)((p) + (i)))
|
||||
#define SET_BITS(reg, mask, value) if ((value) == 0) { (reg) &= ~(mask); } else { (reg) |= (mask); }
|
||||
#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
|
||||
#define CLIC0_REG(offset) _REG32(CLIC_HART0_ADDR, offset)
|
||||
#define CLIC0_REG8(offset) (*(volatile uint8_t *)((CLIC_HART0_ADDR) + (offset)))
|
||||
#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
|
||||
#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset)
|
||||
#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)
|
||||
#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)
|
||||
#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
|
||||
#define CLIC0_REG64(offset) _REG64(CLIC_HART0_ADDR, offset)
|
||||
#define GPIO_REG64(offset) _REG64(GPIO_CTRL_ADDR, offset)
|
||||
#define PWM0_REG64(offset) _REG64(PWM0_CTRL_ADDR, offset)
|
||||
#define SPI0_REG64(offset) _REG64(SPI0_CTRL_ADDR, offset)
|
||||
#define UART0_REG64(offset) _REG64(UART0_CTRL_ADDR, offset)
|
||||
|
||||
// Misc
|
||||
|
||||
#define NUM_GPIO 16
|
||||
|
||||
#define CLIC_NUM_INTERRUPTS 28 + 16
|
||||
|
||||
#ifdef E20
|
||||
#define CLIC_CONFIG_BITS 2
|
||||
#else
|
||||
#define CLIC_CONFIG_BITS 4
|
||||
#endif
|
||||
|
||||
#define HAS_BOARD_BUTTONS
|
||||
|
||||
#include "coreplexip-arty.h"
|
||||
|
||||
unsigned long get_cpu_freq(void);
|
||||
unsigned long get_timer_freq(void);
|
||||
uint64_t get_timer_value(void);
|
||||
|
||||
#endif /* _SIFIVE_PLATFORM_H */
|
|
@ -1,3 +0,0 @@
|
|||
# Describes the CPU on this board to the rest of the SDK.
|
||||
RISCV_ARCH := rv32imac
|
||||
RISCV_ABI := ilp32
|
|
@ -1,157 +0,0 @@
|
|||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
ENTRY( _start )
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flash (rxai!w) : ORIGIN = 0x80008000, LENGTH = 32K
|
||||
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 32K
|
||||
}
|
||||
|
||||
PHDRS
|
||||
{
|
||||
flash PT_LOAD;
|
||||
ram_init PT_LOAD;
|
||||
ram PT_NULL;
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 1K;
|
||||
|
||||
.init :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.text.unlikely .text.unlikely.*)
|
||||
*(.text.startup .text.startup.*)
|
||||
*(.text .text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.fini)))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.lalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data_lma = . );
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data = . );
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.rdata)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = . );
|
||||
PROVIDE( edata = . );
|
||||
|
||||
PROVIDE( _fbss = . );
|
||||
PROVIDE( __bss_start = . );
|
||||
.bss :
|
||||
{
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _end = . );
|
||||
PROVIDE( end = . );
|
||||
|
||||
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
|
||||
{
|
||||
PROVIDE( _heap_end = . );
|
||||
. = __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
} >ram AT>ram :ram
|
||||
}
|
|
@ -1,161 +0,0 @@
|
|||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
ENTRY( _start )
|
||||
|
||||
MEMORY
|
||||
{
|
||||
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 64K
|
||||
}
|
||||
|
||||
PHDRS
|
||||
{
|
||||
ram PT_LOAD;
|
||||
ram_init PT_LOAD;
|
||||
ram PT_NULL;
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 1K;
|
||||
|
||||
.init :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.text.unlikely .text.unlikely.*)
|
||||
*(.text.startup .text.startup.*)
|
||||
*(.text .text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.fini)))
|
||||
} >ram AT>ram :ram
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
|
||||
.rodata :
|
||||
{
|
||||
*(.rdata)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
} >ram AT>ram :ram
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.lalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data_lma = . );
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data = . );
|
||||
} >ram AT>ram :ram_init
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
} >ram AT>ram :ram_init
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = . );
|
||||
PROVIDE( edata = . );
|
||||
|
||||
PROVIDE( _fbss = . );
|
||||
PROVIDE( __bss_start = . );
|
||||
.bss :
|
||||
{
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _end = . );
|
||||
PROVIDE( end = . );
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
. += __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
PROVIDE( _heap_end = . );
|
||||
} >ram AT>ram :ram
|
||||
}
|
|
@ -1,102 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_COREPLEXIP_ARTY_H
|
||||
#define _SIFIVE_COREPLEXIP_ARTY_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/****************************************************************************
|
||||
* GPIO Connections
|
||||
*****************************************************************************/
|
||||
|
||||
// These are the GPIO bit offsets for the directly driven
|
||||
// RGB LEDs on the Freedom Exx Coreplex IP Evaluation Arty FPGA Dev Kit.
|
||||
// Additional RGB LEDs are driven by the 3 PWM outputs.
|
||||
|
||||
#define RED_LED_OFFSET 0
|
||||
#define GREEN_LED_OFFSET 1
|
||||
#define BLUE_LED_OFFSET 2
|
||||
|
||||
// Switch 3 is used as a GPIO input. (Switch 0 is used to set
|
||||
// the reset vector, the other switches are unused).
|
||||
|
||||
#define SW_3_OFFSET 3
|
||||
|
||||
// These are the buttons which are mapped as inputs.
|
||||
|
||||
#define HAS_BOARD_BUTTONS
|
||||
|
||||
#define BUTTON_0_OFFSET 4
|
||||
#define BUTTON_1_OFFSET 5
|
||||
#define BUTTON_2_OFFSET 6
|
||||
#define BUTTON_3_OFFSET 7
|
||||
|
||||
// These are the bit offsets for the different GPIO pins
|
||||
// mapped onto the PMOD A header.
|
||||
|
||||
#define JA_0_OFFSET 8
|
||||
#define JA_1_OFFSET 9
|
||||
#define JA_2_OFFSET 10
|
||||
#define JA_3_OFFSET 11
|
||||
#define JA_4_OFFSET 12
|
||||
#define JA_5_OFFSET 13
|
||||
#define JA_6_OFFSET 14
|
||||
#define JA_7_OFFSET 15
|
||||
|
||||
// The below gives a mapping between global interrupt
|
||||
// sources and their number. Note that on the coreplex
|
||||
// deliverable, the io_global_interrupts go directly into
|
||||
// the PLIC. The evaluation image on the FPGA mimics a
|
||||
// system with peripheral devices which are driving the
|
||||
// global interrupt lines.
|
||||
// So, on this image, in order to get an interrupt from
|
||||
// e.g. pressing BUTTON_0:
|
||||
// 1) Steps which are external to the delivery coreplex:
|
||||
// a) The corresponding GPIO pin must be configured as in input
|
||||
// b) The "interrupt on fall" bit must be set for the GPIO pin
|
||||
// 2) Steps which would also need to be performed for the delivery coreplex:
|
||||
// a) The corresponding global interrupt, priority, and threshold must be configured in the PLIC.
|
||||
// b) The external interrupt bit must be enabled in MSTATUS
|
||||
// c) Interrupts must be enabled globally in the core.
|
||||
|
||||
// Any of the above GPIO pins can be used as global interrupt
|
||||
// sources by adding their offset to the INT_GPIO_BASE.
|
||||
// For example, the buttons are shown here:
|
||||
|
||||
#define INT_DEVICE_BUTTON_0 (GPIO_INT_BASE + BUTTON_0_OFFSET)
|
||||
#define INT_DEVICE_BUTTON_1 (GPIO_INT_BASE + BUTTON_1_OFFSET)
|
||||
#define INT_DEVICE_BUTTON_2 (GPIO_INT_BASE + BUTTON_2_OFFSET)
|
||||
#define INT_DEVICE_BUTTON_3 (GPIO_INT_BASE + BUTTON_3_OFFSET)
|
||||
|
||||
// In addition, the Switches are mapped directly to
|
||||
// the PLIC (without going through the GPIO Peripheral).
|
||||
|
||||
#define INT_EXT_DEVICE_SW_0 (EXTERNAL_INT_BASE + 0)
|
||||
#define INT_EXT_DEVICE_SW_1 (EXTERNAL_INT_BASE + 1)
|
||||
#define INT_EXT_DEVICE_SW_2 (EXTERNAL_INT_BASE + 2)
|
||||
#define INT_EXT_DEVICE_SW_3 (EXTERNAL_INT_BASE + 3)
|
||||
|
||||
// This gives the mapping from inputs to LOCAL interrupts.
|
||||
|
||||
#define LOCAL_INT_SW_0 0
|
||||
#define LOCAL_INT_SW_1 1
|
||||
#define LOCAL_INT_SW_2 2
|
||||
#define LOCAL_INT_SW_3 3
|
||||
#define LOCAL_INT_BTN_0 4
|
||||
#define LOCAL_INT_BTN_1 5
|
||||
#define LOCAL_INT_BTN_2 6
|
||||
#define LOCAL_INT_BTN_3 7
|
||||
#define LOCAL_INT_JA_0 8
|
||||
#define LOCAL_INT_JA_1 9
|
||||
#define LOCAL_INT_JA_2 10
|
||||
#define LOCAL_INT_JA_3 11
|
||||
#define LOCAL_INT_JA_4 12
|
||||
#define LOCAL_INT_JA_5 13
|
||||
#define LOCAL_INT_JA_6 14
|
||||
#define LOCAL_INT_JA_7 15
|
||||
|
||||
#define RTC_FREQ 32768
|
||||
|
||||
void write_hex(int fd, unsigned long int hex);
|
||||
|
||||
#endif /* _SIFIVE_COREPLEXIP_ARTY_H */
|
|
@ -1,157 +0,0 @@
|
|||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
ENTRY( _start )
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 512M
|
||||
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
PHDRS
|
||||
{
|
||||
flash PT_LOAD;
|
||||
ram_init PT_LOAD;
|
||||
ram PT_NULL;
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 1K;
|
||||
|
||||
.init :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.text.unlikely .text.unlikely.*)
|
||||
*(.text.startup .text.startup.*)
|
||||
*(.text .text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.fini)))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.lalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data_lma = . );
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data = . );
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.rdata)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = . );
|
||||
PROVIDE( edata = . );
|
||||
|
||||
PROVIDE( _fbss = . );
|
||||
PROVIDE( __bss_start = . );
|
||||
.bss :
|
||||
{
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _end = . );
|
||||
PROVIDE( end = . );
|
||||
|
||||
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
|
||||
{
|
||||
PROVIDE( _heap_end = . );
|
||||
. = __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
} >ram AT>ram :ram
|
||||
}
|
|
@ -1,161 +0,0 @@
|
|||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
ENTRY( _start )
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 512M
|
||||
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
PHDRS
|
||||
{
|
||||
flash PT_LOAD;
|
||||
ram_init PT_LOAD;
|
||||
ram PT_NULL;
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||
|
||||
.init :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.text.unlikely .text.unlikely.*)
|
||||
*(.text.startup .text.startup.*)
|
||||
*(.text .text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.fini)))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
|
||||
.rodata :
|
||||
{
|
||||
*(.rdata)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
} >flash AT>flash :flash
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.lalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data_lma = . );
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data = . );
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = . );
|
||||
PROVIDE( edata = . );
|
||||
|
||||
PROVIDE( _fbss = . );
|
||||
PROVIDE( __bss_start = . );
|
||||
.bss :
|
||||
{
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _end = . );
|
||||
PROVIDE( end = . );
|
||||
|
||||
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
|
||||
{
|
||||
PROVIDE( _heap_end = . );
|
||||
. = __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
} >ram AT>ram :ram
|
||||
}
|
|
@ -1,122 +0,0 @@
|
|||
//See LICENSE for license details.
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include "platform.h"
|
||||
#include "encoding.h"
|
||||
|
||||
#define CPU_FREQ 65000000
|
||||
#define XSTR(x) #x
|
||||
#define STR(x) XSTR(x)
|
||||
|
||||
#ifndef VECT_IRQ
|
||||
#define TRAP_ENTRY trap_entry
|
||||
#else
|
||||
#define TRAP_ENTRY vtrap_entry
|
||||
#endif
|
||||
|
||||
extern int main(int argc, char** argv);
|
||||
extern void TRAP_ENTRY();
|
||||
|
||||
unsigned long get_cpu_freq()
|
||||
{
|
||||
return CPU_FREQ;
|
||||
}
|
||||
|
||||
unsigned long get_timer_freq()
|
||||
{
|
||||
return get_cpu_freq();
|
||||
}
|
||||
|
||||
uint64_t get_timer_value()
|
||||
{
|
||||
#if __riscv_xlen == 32
|
||||
while (1) {
|
||||
uint32_t hi = read_csr(mcycleh);
|
||||
uint32_t lo = read_csr(mcycle);
|
||||
if (hi == read_csr(mcycleh))
|
||||
return ((uint64_t)hi << 32) | lo;
|
||||
}
|
||||
#else
|
||||
return read_csr(mcycle);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void uart_init(size_t baud_rate)
|
||||
{
|
||||
UART0_REG(UART_REG_DIV) = (get_cpu_freq() / 2) / baud_rate - 1;
|
||||
UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
|
||||
}
|
||||
|
||||
|
||||
#ifdef USE_PLIC
|
||||
extern void handle_m_ext_interrupt();
|
||||
#endif
|
||||
|
||||
#ifdef USE_M_TIME
|
||||
extern void handle_m_time_interrupt();
|
||||
#endif
|
||||
|
||||
#ifdef USE_LOCAL_ISR
|
||||
typedef void (*my_interrupt_function_ptr_t) (void);
|
||||
extern my_interrupt_function_ptr_t localISR[];
|
||||
#endif
|
||||
|
||||
#ifndef VECT_IRQ
|
||||
uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) __attribute__((noinline));
|
||||
uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
|
||||
{
|
||||
if (0){
|
||||
#ifdef USE_PLIC
|
||||
// External Machine-Level interrupt from PLIC
|
||||
} else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) {
|
||||
handle_m_ext_interrupt();
|
||||
#endif
|
||||
#ifdef USE_M_TIME
|
||||
// External Machine-Level interrupt from PLIC
|
||||
} else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
|
||||
handle_m_time_interrupt();
|
||||
#endif
|
||||
#ifdef USE_LOCAL_ISR
|
||||
} else if (mcause & MCAUSE_INT) {
|
||||
localISR[mcause & MCAUSE_CAUSE] ();
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
write(1, "Unhandled Trap:\n", 16);
|
||||
_exit(1 + mcause);
|
||||
}
|
||||
return epc;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef USE_CLIC
|
||||
void trap_entry(void) __attribute__((interrupt("SiFive-CLIC-preemptible"), aligned(64)));
|
||||
void trap_entry(void)
|
||||
{
|
||||
unsigned long mcause = read_csr(mcause);
|
||||
unsigned long mepc = read_csr(mepc);
|
||||
handle_trap(mcause, mepc);
|
||||
}
|
||||
#endif
|
||||
|
||||
void _init()
|
||||
{
|
||||
#ifndef NO_INIT
|
||||
uart_init(115200);
|
||||
|
||||
puts("core freq at " STR(CPU_FREQ) " Hz\n");
|
||||
|
||||
#ifdef USE_CLIC
|
||||
write_csr(mtvec, ((unsigned long)&trap_entry | MTVEC_CLIC));
|
||||
#else
|
||||
write_csr(mtvec, ((unsigned long)&TRAP_ENTRY | MTVEC_VECTORED));
|
||||
#endif
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
void _fini()
|
||||
{
|
||||
}
|
|
@ -1,31 +0,0 @@
|
|||
# JTAG adapter setup
|
||||
adapter_khz 10000
|
||||
|
||||
interface ftdi
|
||||
ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
|
||||
ftdi_vid_pid 0x15ba 0x002a
|
||||
|
||||
ftdi_layout_init 0x0808 0x0a1b
|
||||
ftdi_layout_signal nSRST -oe 0x0200
|
||||
#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
|
||||
ftdi_layout_signal LED -data 0x0800
|
||||
|
||||
set _CHIPNAME riscv
|
||||
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
|
||||
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
|
||||
$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
|
||||
|
||||
# Un-comment these two flash lines if you have a SPI flash and want to write
|
||||
# it.
|
||||
flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
|
||||
init
|
||||
if {[ info exists pulse_srst]} {
|
||||
ftdi_set_signal nSRST 0
|
||||
ftdi_set_signal nSRST z
|
||||
}
|
||||
halt
|
||||
#flash protect 0 64 last off
|
||||
echo "Ready for Remote Connections"
|
|
@ -1,100 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_PLATFORM_H
|
||||
#define _SIFIVE_PLATFORM_H
|
||||
|
||||
// Some things missing from the official encoding.h
|
||||
|
||||
#if __riscv_xlen == 32
|
||||
#define MCAUSE_INT 0x80000000UL
|
||||
#define MCAUSE_CAUSE 0x000003FFUL
|
||||
#else
|
||||
#define MCAUSE_INT 0x8000000000000000UL
|
||||
#define MCAUSE_CAUSE 0x00000000000003FFUL
|
||||
#endif
|
||||
|
||||
#ifdef VECT_IRQ
|
||||
#define MTVEC_VECTORED 0x01
|
||||
#else
|
||||
#define MTVEC_VECTORED 0x00
|
||||
#endif
|
||||
#define MTVEC_CLIC 0x02
|
||||
#define IRQ_M_LOCAL 16
|
||||
#define MIP_MLIP(x) (1 << (IRQ_M_LOCAL + x))
|
||||
|
||||
#include "sifive/const.h"
|
||||
#include "sifive/devices/clint.h"
|
||||
#include "sifive/devices/gpio.h"
|
||||
#include "sifive/devices/plic.h"
|
||||
#include "sifive/devices/pwm.h"
|
||||
#include "sifive/devices/spi.h"
|
||||
#include "sifive/devices/uart.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Platform definitions
|
||||
*****************************************************************************/
|
||||
|
||||
// Memory map
|
||||
#define CLINT_CTRL_ADDR _AC(0x02000000,UL)
|
||||
#define GPIO_CTRL_ADDR _AC(0x20002000,UL)
|
||||
#define PLIC_CTRL_ADDR _AC(0x0C000000,UL)
|
||||
#define PWM0_CTRL_ADDR _AC(0x20005000,UL)
|
||||
#define RAM_MEM_ADDR _AC(0x80000000,UL)
|
||||
#define RAM_MEM_SIZE _AC(0x10000,UL)
|
||||
#define SPI0_CTRL_ADDR _AC(0x20004000,UL)
|
||||
#define SPI0_MEM_ADDR _AC(0x40000000,UL)
|
||||
#define SPI0_MEM_SIZE _AC(0x20000000,UL)
|
||||
#define TESTBENCH_MEM_ADDR _AC(0x20000000,UL)
|
||||
#define TESTBENCH_MEM_SIZE _AC(0x10000000,UL)
|
||||
#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL)
|
||||
#define UART0_CTRL_ADDR _AC(0x20000000,UL)
|
||||
|
||||
// IOF masks
|
||||
|
||||
// Interrupt numbers
|
||||
#define RESERVED_INT_BASE 0
|
||||
#define UART0_INT_BASE 1
|
||||
#define EXTERNAL_INT_BASE 2
|
||||
#define SPI0_INT_BASE 6
|
||||
#define GPIO_INT_BASE 7
|
||||
#define PWM0_INT_BASE 23
|
||||
|
||||
// Helper functions
|
||||
#define _REG64(p, i) (*(volatile uint64_t *)((p) + (i)))
|
||||
#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i)))
|
||||
#define _REG16(p, i) (*(volatile uint16_t *)((p) + (i)))
|
||||
// Bulk set bits in `reg` to either 0 or 1.
|
||||
// E.g. SET_BITS(MY_REG, 0x00000007, 0) would generate MY_REG &= ~0x7
|
||||
// E.g. SET_BITS(MY_REG, 0x00000007, 1) would generate MY_REG |= 0x7
|
||||
#define SET_BITS(reg, mask, value) if ((value) == 0) { (reg) &= ~(mask); } else { (reg) |= (mask); }
|
||||
#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
|
||||
#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
|
||||
#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset)
|
||||
#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset)
|
||||
#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)
|
||||
#define TRAPVEC_TABLE_REG(offset) _REG32(TRAPVEC_TABLE_CTRL_ADDR, offset)
|
||||
#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)
|
||||
#define CLINT_REG64(offset) _REG64(CLINT_CTRL_ADDR, offset)
|
||||
#define GPIO_REG64(offset) _REG64(GPIO_CTRL_ADDR, offset)
|
||||
#define PLIC_REG64(offset) _REG64(PLIC_CTRL_ADDR, offset)
|
||||
#define PWM0_REG64(offset) _REG64(PWM0_CTRL_ADDR, offset)
|
||||
#define SPI0_REG64(offset) _REG64(SPI0_CTRL_ADDR, offset)
|
||||
#define TRAPVEC_TABLE_REG64(offset) _REG64(TRAPVEC_TABLE_CTRL_ADDR, offset)
|
||||
#define UART0_REG64(offset) _REG64(UART0_CTRL_ADDR, offset)
|
||||
|
||||
// Misc
|
||||
|
||||
#define NUM_GPIO 16
|
||||
|
||||
#define PLIC_NUM_INTERRUPTS 28
|
||||
#define PLIC_NUM_PRIORITIES 7
|
||||
|
||||
#define HAS_BOARD_BUTTONS
|
||||
|
||||
#include "coreplexip-arty.h"
|
||||
|
||||
unsigned long get_cpu_freq(void);
|
||||
unsigned long get_timer_freq(void);
|
||||
uint64_t get_timer_value(void);
|
||||
|
||||
#endif /* _SIFIVE_PLATFORM_H */
|
|
@ -1,161 +0,0 @@
|
|||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
ENTRY( _start )
|
||||
|
||||
MEMORY
|
||||
{
|
||||
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
PHDRS
|
||||
{
|
||||
ram PT_LOAD;
|
||||
ram_init PT_LOAD;
|
||||
ram PT_NULL;
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 1K;
|
||||
|
||||
.init :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.text.unlikely .text.unlikely.*)
|
||||
*(.text.startup .text.startup.*)
|
||||
*(.text .text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.fini)))
|
||||
} >ram AT>ram :ram
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
|
||||
.rodata :
|
||||
{
|
||||
*(.rdata)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
} >ram AT>ram :ram
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.lalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data_lma = . );
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data = . );
|
||||
} >ram AT>ram :ram_init
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
} >ram AT>ram :ram_init
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = . );
|
||||
PROVIDE( edata = . );
|
||||
|
||||
PROVIDE( _fbss = . );
|
||||
PROVIDE( __bss_start = . );
|
||||
.bss :
|
||||
{
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _end = . );
|
||||
PROVIDE( end = . );
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
. += __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
PROVIDE( _heap_end = . );
|
||||
} >ram AT>ram :ram
|
||||
}
|
|
@ -1,3 +0,0 @@
|
|||
# Describes the CPU on this board to the rest of the SDK.
|
||||
RISCV_ARCH := rv32imac
|
||||
RISCV_ABI := ilp32
|
|
@ -1,157 +0,0 @@
|
|||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
ENTRY( _start )
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 512M
|
||||
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
PHDRS
|
||||
{
|
||||
flash PT_LOAD;
|
||||
ram_init PT_LOAD;
|
||||
ram PT_NULL;
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 1K;
|
||||
|
||||
.init :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.text.unlikely .text.unlikely.*)
|
||||
*(.text.startup .text.startup.*)
|
||||
*(.text .text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.fini)))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.lalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data_lma = . );
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data = . );
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.rdata)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = . );
|
||||
PROVIDE( edata = . );
|
||||
|
||||
PROVIDE( _fbss = . );
|
||||
PROVIDE( __bss_start = . );
|
||||
.bss :
|
||||
{
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _end = . );
|
||||
PROVIDE( end = . );
|
||||
|
||||
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
|
||||
{
|
||||
PROVIDE( _heap_end = . );
|
||||
. = __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
} >ram AT>ram :ram
|
||||
}
|
|
@ -1,161 +0,0 @@
|
|||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
ENTRY( _start )
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 512M
|
||||
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
PHDRS
|
||||
{
|
||||
flash PT_LOAD;
|
||||
ram_init PT_LOAD;
|
||||
ram PT_NULL;
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||
|
||||
.init :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.text.unlikely .text.unlikely.*)
|
||||
*(.text.startup .text.startup.*)
|
||||
*(.text .text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.fini)))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
|
||||
.rodata :
|
||||
{
|
||||
*(.rdata)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
} >flash AT>flash :flash
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.lalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data_lma = . );
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data = . );
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = . );
|
||||
PROVIDE( edata = . );
|
||||
|
||||
PROVIDE( _fbss = . );
|
||||
PROVIDE( __bss_start = . );
|
||||
.bss :
|
||||
{
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _end = . );
|
||||
PROVIDE( end = . );
|
||||
|
||||
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
|
||||
{
|
||||
PROVIDE( _heap_end = . );
|
||||
. = __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
} >ram AT>ram :ram
|
||||
}
|
|
@ -1,122 +0,0 @@
|
|||
//See LICENSE for license details.
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include "platform.h"
|
||||
#include "encoding.h"
|
||||
|
||||
#define CPU_FREQ 65000000
|
||||
#define XSTR(x) #x
|
||||
#define STR(x) XSTR(x)
|
||||
|
||||
#ifndef VECT_IRQ
|
||||
#define TRAP_ENTRY trap_entry
|
||||
#else
|
||||
#define TRAP_ENTRY vtrap_entry
|
||||
#endif
|
||||
|
||||
extern int main(int argc, char** argv);
|
||||
extern void TRAP_ENTRY();
|
||||
|
||||
unsigned long get_cpu_freq()
|
||||
{
|
||||
return CPU_FREQ;
|
||||
}
|
||||
|
||||
unsigned long get_timer_freq()
|
||||
{
|
||||
return get_cpu_freq();
|
||||
}
|
||||
|
||||
uint64_t get_timer_value()
|
||||
{
|
||||
#if __riscv_xlen == 32
|
||||
while (1) {
|
||||
uint32_t hi = read_csr(mcycleh);
|
||||
uint32_t lo = read_csr(mcycle);
|
||||
if (hi == read_csr(mcycleh))
|
||||
return ((uint64_t)hi << 32) | lo;
|
||||
}
|
||||
#else
|
||||
return read_csr(mcycle);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void uart_init(size_t baud_rate)
|
||||
{
|
||||
UART0_REG(UART_REG_DIV) = (get_cpu_freq() / 2) / baud_rate - 1;
|
||||
UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
|
||||
}
|
||||
|
||||
|
||||
#ifdef USE_PLIC
|
||||
extern void handle_m_ext_interrupt();
|
||||
#endif
|
||||
|
||||
#ifdef USE_M_TIME
|
||||
extern void handle_m_time_interrupt();
|
||||
#endif
|
||||
|
||||
#ifdef USE_LOCAL_ISR
|
||||
typedef void (*my_interrupt_function_ptr_t) (void);
|
||||
extern my_interrupt_function_ptr_t localISR[];
|
||||
#endif
|
||||
|
||||
#ifndef VECT_IRQ
|
||||
uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) __attribute__((noinline));
|
||||
uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
|
||||
{
|
||||
if (0){
|
||||
#ifdef USE_PLIC
|
||||
// External Machine-Level interrupt from PLIC
|
||||
} else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) {
|
||||
handle_m_ext_interrupt();
|
||||
#endif
|
||||
#ifdef USE_M_TIME
|
||||
// External Machine-Level interrupt from PLIC
|
||||
} else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
|
||||
handle_m_time_interrupt();
|
||||
#endif
|
||||
#ifdef USE_LOCAL_ISR
|
||||
} else if (mcause & MCAUSE_INT) {
|
||||
localISR[mcause & MCAUSE_CAUSE] ();
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
write(1, "Unhandled Trap:\n", 16);
|
||||
_exit(1 + mcause);
|
||||
}
|
||||
return epc;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef USE_CLIC
|
||||
void trap_entry(void) __attribute__((interrupt("SiFive-CLIC-preemptible"), aligned(64)));
|
||||
void trap_entry(void)
|
||||
{
|
||||
unsigned long mcause = read_csr(mcause);
|
||||
unsigned long mepc = read_csr(mepc);
|
||||
handle_trap(mcause, mepc);
|
||||
}
|
||||
#endif
|
||||
|
||||
void _init()
|
||||
{
|
||||
#ifndef NO_INIT
|
||||
uart_init(115200);
|
||||
|
||||
puts("core freq at " STR(CPU_FREQ) " Hz\n");
|
||||
|
||||
#ifdef USE_CLIC
|
||||
write_csr(mtvec, ((unsigned long)&trap_entry | MTVEC_CLIC));
|
||||
#else
|
||||
write_csr(mtvec, ((unsigned long)&TRAP_ENTRY | MTVEC_VECTORED));
|
||||
#endif
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
void _fini()
|
||||
{
|
||||
}
|
|
@ -1,31 +0,0 @@
|
|||
# JTAG adapter setup
|
||||
adapter_khz 10000
|
||||
|
||||
interface ftdi
|
||||
ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
|
||||
ftdi_vid_pid 0x15ba 0x002a
|
||||
|
||||
ftdi_layout_init 0x0808 0x0a1b
|
||||
ftdi_layout_signal nSRST -oe 0x0200
|
||||
#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
|
||||
ftdi_layout_signal LED -data 0x0800
|
||||
|
||||
set _CHIPNAME riscv
|
||||
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
|
||||
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
|
||||
$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
|
||||
|
||||
# Un-comment these two flash lines if you have a SPI flash and want to write
|
||||
# it.
|
||||
flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
|
||||
init
|
||||
if {[ info exists pulse_srst]} {
|
||||
ftdi_set_signal nSRST 0
|
||||
ftdi_set_signal nSRST z
|
||||
}
|
||||
halt
|
||||
#flash protect 0 64 last off
|
||||
echo "Ready for Remote Connections"
|
|
@ -1,100 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_PLATFORM_H
|
||||
#define _SIFIVE_PLATFORM_H
|
||||
|
||||
// Some things missing from the official encoding.h
|
||||
|
||||
#if __riscv_xlen == 32
|
||||
#define MCAUSE_INT 0x80000000UL
|
||||
#define MCAUSE_CAUSE 0x000003FFUL
|
||||
#else
|
||||
#define MCAUSE_INT 0x8000000000000000UL
|
||||
#define MCAUSE_CAUSE 0x00000000000003FFUL
|
||||
#endif
|
||||
|
||||
#ifdef VECT_IRQ
|
||||
#define MTVEC_VECTORED 0x01
|
||||
#else
|
||||
#define MTVEC_VECTORED 0x00
|
||||
#endif
|
||||
#define MTVEC_CLIC 0x02
|
||||
#define IRQ_M_LOCAL 16
|
||||
#define MIP_MLIP(x) (1 << (IRQ_M_LOCAL + x))
|
||||
|
||||
#include "sifive/const.h"
|
||||
#include "sifive/devices/clint.h"
|
||||
#include "sifive/devices/gpio.h"
|
||||
#include "sifive/devices/plic.h"
|
||||
#include "sifive/devices/pwm.h"
|
||||
#include "sifive/devices/spi.h"
|
||||
#include "sifive/devices/uart.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Platform definitions
|
||||
*****************************************************************************/
|
||||
|
||||
// Memory map
|
||||
#define CLINT_CTRL_ADDR _AC(0x02000000,UL)
|
||||
#define GPIO_CTRL_ADDR _AC(0x20002000,UL)
|
||||
#define PLIC_CTRL_ADDR _AC(0x0C000000,UL)
|
||||
#define PWM0_CTRL_ADDR _AC(0x20005000,UL)
|
||||
#define RAM_MEM_ADDR _AC(0x80000000,UL)
|
||||
#define RAM_MEM_SIZE _AC(0x10000,UL)
|
||||
#define SPI0_CTRL_ADDR _AC(0x20004000,UL)
|
||||
#define SPI0_MEM_ADDR _AC(0x40000000,UL)
|
||||
#define SPI0_MEM_SIZE _AC(0x20000000,UL)
|
||||
#define TESTBENCH_MEM_ADDR _AC(0x20000000,UL)
|
||||
#define TESTBENCH_MEM_SIZE _AC(0x10000000,UL)
|
||||
#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL)
|
||||
#define UART0_CTRL_ADDR _AC(0x20000000,UL)
|
||||
|
||||
// IOF masks
|
||||
|
||||
// Interrupt numbers
|
||||
#define RESERVED_INT_BASE 0
|
||||
#define UART0_INT_BASE 1
|
||||
#define EXTERNAL_INT_BASE 2
|
||||
#define SPI0_INT_BASE 6
|
||||
#define GPIO_INT_BASE 7
|
||||
#define PWM0_INT_BASE 23
|
||||
|
||||
// Helper functions
|
||||
#define _REG64(p, i) (*(volatile uint64_t *)((p) + (i)))
|
||||
#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i)))
|
||||
#define _REG16(p, i) (*(volatile uint16_t *)((p) + (i)))
|
||||
// Bulk set bits in `reg` to either 0 or 1.
|
||||
// E.g. SET_BITS(MY_REG, 0x00000007, 0) would generate MY_REG &= ~0x7
|
||||
// E.g. SET_BITS(MY_REG, 0x00000007, 1) would generate MY_REG |= 0x7
|
||||
#define SET_BITS(reg, mask, value) if ((value) == 0) { (reg) &= ~(mask); } else { (reg) |= (mask); }
|
||||
#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
|
||||
#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
|
||||
#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset)
|
||||
#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset)
|
||||
#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)
|
||||
#define TRAPVEC_TABLE_REG(offset) _REG32(TRAPVEC_TABLE_CTRL_ADDR, offset)
|
||||
#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)
|
||||
#define CLINT_REG64(offset) _REG64(CLINT_CTRL_ADDR, offset)
|
||||
#define GPIO_REG64(offset) _REG64(GPIO_CTRL_ADDR, offset)
|
||||
#define PLIC_REG64(offset) _REG64(PLIC_CTRL_ADDR, offset)
|
||||
#define PWM0_REG64(offset) _REG64(PWM0_CTRL_ADDR, offset)
|
||||
#define SPI0_REG64(offset) _REG64(SPI0_CTRL_ADDR, offset)
|
||||
#define TRAPVEC_TABLE_REG64(offset) _REG64(TRAPVEC_TABLE_CTRL_ADDR, offset)
|
||||
#define UART0_REG64(offset) _REG64(UART0_CTRL_ADDR, offset)
|
||||
|
||||
// Misc
|
||||
|
||||
#define NUM_GPIO 16
|
||||
|
||||
#define PLIC_NUM_INTERRUPTS 28
|
||||
#define PLIC_NUM_PRIORITIES 7
|
||||
|
||||
#define HAS_BOARD_BUTTONS
|
||||
|
||||
#include "coreplexip-arty.h"
|
||||
|
||||
unsigned long get_cpu_freq(void);
|
||||
unsigned long get_timer_freq(void);
|
||||
uint64_t get_timer_value(void);
|
||||
|
||||
#endif /* _SIFIVE_PLATFORM_H */
|
|
@ -1,161 +0,0 @@
|
|||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
ENTRY( _start )
|
||||
|
||||
MEMORY
|
||||
{
|
||||
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
PHDRS
|
||||
{
|
||||
ram PT_LOAD;
|
||||
ram_init PT_LOAD;
|
||||
ram PT_NULL;
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 1K;
|
||||
|
||||
.init :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.text.unlikely .text.unlikely.*)
|
||||
*(.text.startup .text.startup.*)
|
||||
*(.text .text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.fini)))
|
||||
} >ram AT>ram :ram
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
|
||||
.rodata :
|
||||
{
|
||||
*(.rdata)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
} >ram AT>ram :ram
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.lalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data_lma = . );
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data = . );
|
||||
} >ram AT>ram :ram_init
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
} >ram AT>ram :ram_init
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = . );
|
||||
PROVIDE( edata = . );
|
||||
|
||||
PROVIDE( _fbss = . );
|
||||
PROVIDE( __bss_start = . );
|
||||
.bss :
|
||||
{
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _end = . );
|
||||
PROVIDE( end = . );
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
. += __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
PROVIDE( _heap_end = . );
|
||||
} >ram AT>ram :ram
|
||||
}
|
|
@ -1,3 +0,0 @@
|
|||
# Describes the CPU on this board to the rest of the SDK.
|
||||
RISCV_ARCH := rv64imac
|
||||
RISCV_ABI := lp64
|
File diff suppressed because it is too large
Load Diff
|
@ -1,98 +0,0 @@
|
|||
// See LICENSE for license details
|
||||
|
||||
#ifndef ENTRY_S
|
||||
#define ENTRY_S
|
||||
|
||||
#include "encoding.h"
|
||||
#include "sifive/bits.h"
|
||||
|
||||
.section .text.entry
|
||||
.align 2
|
||||
.weak trap_entry
|
||||
.global trap_entry
|
||||
trap_entry:
|
||||
addi sp, sp, -32*REGBYTES
|
||||
|
||||
STORE x1, 1*REGBYTES(sp)
|
||||
STORE x2, 2*REGBYTES(sp)
|
||||
STORE x3, 3*REGBYTES(sp)
|
||||
STORE x4, 4*REGBYTES(sp)
|
||||
STORE x5, 5*REGBYTES(sp)
|
||||
STORE x6, 6*REGBYTES(sp)
|
||||
STORE x7, 7*REGBYTES(sp)
|
||||
STORE x8, 8*REGBYTES(sp)
|
||||
STORE x9, 9*REGBYTES(sp)
|
||||
STORE x10, 10*REGBYTES(sp)
|
||||
STORE x11, 11*REGBYTES(sp)
|
||||
STORE x12, 12*REGBYTES(sp)
|
||||
STORE x13, 13*REGBYTES(sp)
|
||||
STORE x14, 14*REGBYTES(sp)
|
||||
STORE x15, 15*REGBYTES(sp)
|
||||
STORE x16, 16*REGBYTES(sp)
|
||||
STORE x17, 17*REGBYTES(sp)
|
||||
STORE x18, 18*REGBYTES(sp)
|
||||
STORE x19, 19*REGBYTES(sp)
|
||||
STORE x20, 20*REGBYTES(sp)
|
||||
STORE x21, 21*REGBYTES(sp)
|
||||
STORE x22, 22*REGBYTES(sp)
|
||||
STORE x23, 23*REGBYTES(sp)
|
||||
STORE x24, 24*REGBYTES(sp)
|
||||
STORE x25, 25*REGBYTES(sp)
|
||||
STORE x26, 26*REGBYTES(sp)
|
||||
STORE x27, 27*REGBYTES(sp)
|
||||
STORE x28, 28*REGBYTES(sp)
|
||||
STORE x29, 29*REGBYTES(sp)
|
||||
STORE x30, 30*REGBYTES(sp)
|
||||
STORE x31, 31*REGBYTES(sp)
|
||||
|
||||
csrr a0, mcause
|
||||
csrr a1, mepc
|
||||
mv a2, sp
|
||||
call handle_trap
|
||||
csrw mepc, a0
|
||||
|
||||
# Remain in M-mode after mret
|
||||
li t0, MSTATUS_MPP
|
||||
csrs mstatus, t0
|
||||
|
||||
LOAD x1, 1*REGBYTES(sp)
|
||||
LOAD x2, 2*REGBYTES(sp)
|
||||
LOAD x3, 3*REGBYTES(sp)
|
||||
LOAD x4, 4*REGBYTES(sp)
|
||||
LOAD x5, 5*REGBYTES(sp)
|
||||
LOAD x6, 6*REGBYTES(sp)
|
||||
LOAD x7, 7*REGBYTES(sp)
|
||||
LOAD x8, 8*REGBYTES(sp)
|
||||
LOAD x9, 9*REGBYTES(sp)
|
||||
LOAD x10, 10*REGBYTES(sp)
|
||||
LOAD x11, 11*REGBYTES(sp)
|
||||
LOAD x12, 12*REGBYTES(sp)
|
||||
LOAD x13, 13*REGBYTES(sp)
|
||||
LOAD x14, 14*REGBYTES(sp)
|
||||
LOAD x15, 15*REGBYTES(sp)
|
||||
LOAD x16, 16*REGBYTES(sp)
|
||||
LOAD x17, 17*REGBYTES(sp)
|
||||
LOAD x18, 18*REGBYTES(sp)
|
||||
LOAD x19, 19*REGBYTES(sp)
|
||||
LOAD x20, 20*REGBYTES(sp)
|
||||
LOAD x21, 21*REGBYTES(sp)
|
||||
LOAD x22, 22*REGBYTES(sp)
|
||||
LOAD x23, 23*REGBYTES(sp)
|
||||
LOAD x24, 24*REGBYTES(sp)
|
||||
LOAD x25, 25*REGBYTES(sp)
|
||||
LOAD x26, 26*REGBYTES(sp)
|
||||
LOAD x27, 27*REGBYTES(sp)
|
||||
LOAD x28, 28*REGBYTES(sp)
|
||||
LOAD x29, 29*REGBYTES(sp)
|
||||
LOAD x30, 30*REGBYTES(sp)
|
||||
LOAD x31, 31*REGBYTES(sp)
|
||||
|
||||
addi sp, sp, 32*REGBYTES
|
||||
mret
|
||||
|
||||
.weak handle_trap
|
||||
handle_trap:
|
||||
1:
|
||||
j 1b
|
||||
|
||||
#endif
|
|
@ -1,161 +0,0 @@
|
|||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
ENTRY( _start )
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M
|
||||
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
PHDRS
|
||||
{
|
||||
flash PT_LOAD;
|
||||
ram_init PT_LOAD;
|
||||
ram PT_NULL;
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||
|
||||
.init :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.text.unlikely .text.unlikely.*)
|
||||
*(.text.startup .text.startup.*)
|
||||
*(.text .text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.fini)))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
|
||||
.rodata :
|
||||
{
|
||||
*(.rdata)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
} >flash AT>flash :flash
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.lalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data_lma = . );
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data = . );
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = . );
|
||||
PROVIDE( edata = . );
|
||||
|
||||
PROVIDE( _fbss = . );
|
||||
PROVIDE( __bss_start = . );
|
||||
.bss :
|
||||
{
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _end = . );
|
||||
PROVIDE( end = . );
|
||||
|
||||
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
|
||||
{
|
||||
PROVIDE( _heap_end = . );
|
||||
. = __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
} >ram AT>ram :ram
|
||||
}
|
|
@ -1,87 +0,0 @@
|
|||
//See LICENSE for license details.
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include "platform.h"
|
||||
#include "encoding.h"
|
||||
|
||||
extern int main(int argc, char** argv);
|
||||
extern void trap_entry();
|
||||
|
||||
static unsigned long get_cpu_freq()
|
||||
{
|
||||
return 65000000;
|
||||
}
|
||||
|
||||
unsigned long get_timer_freq()
|
||||
{
|
||||
return get_cpu_freq();
|
||||
}
|
||||
|
||||
uint64_t get_timer_value()
|
||||
{
|
||||
#if __riscv_xlen == 32
|
||||
while (1) {
|
||||
uint32_t hi = read_csr(mcycleh);
|
||||
uint32_t lo = read_csr(mcycle);
|
||||
if (hi == read_csr(mcycleh))
|
||||
return ((uint64_t)hi << 32) | lo;
|
||||
}
|
||||
#else
|
||||
return read_csr(mcycle);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void uart_init(size_t baud_rate)
|
||||
{
|
||||
GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
|
||||
GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
|
||||
UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1;
|
||||
UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
|
||||
}
|
||||
|
||||
|
||||
#ifdef USE_PLIC
|
||||
extern void handle_m_ext_interrupt();
|
||||
#endif
|
||||
|
||||
#ifdef USE_M_TIME
|
||||
extern void handle_m_time_interrupt();
|
||||
#endif
|
||||
|
||||
uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
|
||||
{
|
||||
if (0){
|
||||
#ifdef USE_PLIC
|
||||
// External Machine-Level interrupt from PLIC
|
||||
} else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) {
|
||||
handle_m_ext_interrupt();
|
||||
#endif
|
||||
#ifdef USE_M_TIME
|
||||
// External Machine-Level interrupt from PLIC
|
||||
} else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
|
||||
handle_m_time_interrupt();
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
write(1, "Unhandled Trap:\n", 16);
|
||||
_exit(1 + mcause);
|
||||
}
|
||||
return epc;
|
||||
}
|
||||
|
||||
void _init()
|
||||
{
|
||||
#ifndef NO_INIT
|
||||
uart_init(115200);
|
||||
|
||||
printf("core freq at %d Hz\n", get_cpu_freq());
|
||||
|
||||
write_csr(mtvec, &trap_entry);
|
||||
#endif
|
||||
}
|
||||
|
||||
void _fini()
|
||||
{
|
||||
}
|
|
@ -1,30 +0,0 @@
|
|||
adapter_khz 10000
|
||||
|
||||
#source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg]
|
||||
|
||||
interface ftdi
|
||||
ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
|
||||
ftdi_vid_pid 0x15ba 0x002a
|
||||
|
||||
ftdi_layout_init 0x0808 0x0a1b
|
||||
ftdi_layout_signal nSRST -oe 0x0200
|
||||
ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
|
||||
ftdi_layout_signal LED -data 0x0800
|
||||
#
|
||||
|
||||
set _CHIPNAME riscv
|
||||
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
|
||||
$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
|
||||
|
||||
flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME
|
||||
init
|
||||
#reset
|
||||
if {[ info exists pulse_srst]} {
|
||||
ftdi_set_signal nSRST 0
|
||||
ftdi_set_signal nSRST z
|
||||
}
|
||||
halt
|
||||
#flash protect 0 64 last off
|
|
@ -1,124 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_PLATFORM_H
|
||||
#define _SIFIVE_PLATFORM_H
|
||||
|
||||
// Some things missing from the official encoding.h
|
||||
#define MCAUSE_INT 0x80000000
|
||||
#define MCAUSE_CAUSE 0x7FFFFFFF
|
||||
|
||||
#include "sifive/const.h"
|
||||
#include "sifive/devices/aon.h"
|
||||
#include "sifive/devices/clint.h"
|
||||
#include "sifive/devices/gpio.h"
|
||||
#include "sifive/devices/plic.h"
|
||||
#include "sifive/devices/pwm.h"
|
||||
#include "sifive/devices/spi.h"
|
||||
#include "sifive/devices/uart.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Platform definitions
|
||||
*****************************************************************************/
|
||||
|
||||
#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL)
|
||||
#define CLINT_CTRL_ADDR _AC(0x02000000,UL)
|
||||
#define PLIC_CTRL_ADDR _AC(0x0C000000,UL)
|
||||
#define AON_CTRL_ADDR _AC(0x10000000,UL)
|
||||
#define GPIO_CTRL_ADDR _AC(0x10012000,UL)
|
||||
#define UART0_CTRL_ADDR _AC(0x10013000,UL)
|
||||
#define SPI0_CTRL_ADDR _AC(0x10014000,UL)
|
||||
#define PWM0_CTRL_ADDR _AC(0x10015000,UL)
|
||||
#define UART1_CTRL_ADDR _AC(0x10023000,UL)
|
||||
#define SPI1_CTRL_ADDR _AC(0x10024000,UL)
|
||||
#define PWM1_CTRL_ADDR _AC(0x10025000,UL)
|
||||
#define SPI2_CTRL_ADDR _AC(0x10034000,UL)
|
||||
#define PWM2_CTRL_ADDR _AC(0x10035000,UL)
|
||||
#define SPI0_MMAP_ADDR _AC(0x20000000,UL)
|
||||
#define MEM_CTRL_ADDR _AC(0x80000000,UL)
|
||||
|
||||
// IOF Mappings
|
||||
#define IOF0_SPI1_MASK _AC(0x000007FC,UL)
|
||||
#define SPI11_NUM_SS (4)
|
||||
#define IOF_SPI1_SS0 (2u)
|
||||
#define IOF_SPI1_SS1 (8u)
|
||||
#define IOF_SPI1_SS2 (9u)
|
||||
#define IOF_SPI1_SS3 (10u)
|
||||
#define IOF_SPI1_MOSI (3u)
|
||||
#define IOF_SPI1_MISO (4u)
|
||||
#define IOF_SPI1_SCK (5u)
|
||||
#define IOF_SPI1_DQ0 (3u)
|
||||
#define IOF_SPI1_DQ1 (4u)
|
||||
#define IOF_SPI1_DQ2 (6u)
|
||||
#define IOF_SPI1_DQ3 (7u)
|
||||
|
||||
#define IOF0_SPI2_MASK _AC(0xFC000000,UL)
|
||||
#define SPI2_NUM_SS (1)
|
||||
#define IOF_SPI2_SS0 (26u)
|
||||
#define IOF_SPI2_MOSI (27u)
|
||||
#define IOF_SPI2_MISO (28u)
|
||||
#define IOF_SPI2_SCK (29u)
|
||||
#define IOF_SPI2_DQ0 (27u)
|
||||
#define IOF_SPI2_DQ1 (28u)
|
||||
#define IOF_SPI2_DQ2 (30u)
|
||||
#define IOF_SPI2_DQ3 (31u)
|
||||
|
||||
#define IOF0_UART0_MASK _AC(0x00030000, UL)
|
||||
#define IOF_UART0_RX (16u)
|
||||
#define IOF_UART0_TX (17u)
|
||||
|
||||
#define IOF0_UART1_MASK _AC(0x03000000, UL)
|
||||
#define IOF_UART1_RX (24u)
|
||||
#define IOF_UART1_TX (25u)
|
||||
|
||||
#define IOF1_PWM0_MASK _AC(0x0000000F, UL)
|
||||
#define IOF1_PWM1_MASK _AC(0x00780000, UL)
|
||||
#define IOF1_PWM2_MASK _AC(0x00003C00, UL)
|
||||
|
||||
// Interrupt Numbers
|
||||
#define INT_RESERVED 0
|
||||
#define INT_WDOGCMP 1
|
||||
#define INT_RTCCMP 2
|
||||
#define INT_UART0_BASE 3
|
||||
#define INT_UART1_BASE 4
|
||||
#define INT_SPI0_BASE 5
|
||||
#define INT_SPI1_BASE 6
|
||||
#define INT_SPI2_BASE 7
|
||||
#define INT_GPIO_BASE 8
|
||||
#define INT_PWM0_BASE 40
|
||||
#define INT_PWM1_BASE 44
|
||||
#define INT_PWM2_BASE 48
|
||||
|
||||
// Helper functions
|
||||
#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
|
||||
#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))
|
||||
#define AON_REG(offset) _REG32(AON_CTRL_ADDR, offset)
|
||||
#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
|
||||
#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
|
||||
#define OTP_REG(offset) _REG32(OTP_CTRL_ADDR, offset)
|
||||
#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset)
|
||||
#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset)
|
||||
#define PWM1_REG(offset) _REG32(PWM1_CTRL_ADDR, offset)
|
||||
#define PWM2_REG(offset) _REG32(PWM2_CTRL_ADDR, offset)
|
||||
#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)
|
||||
#define SPI1_REG(offset) _REG32(SPI1_CTRL_ADDR, offset)
|
||||
#define SPI2_REG(offset) _REG32(SPI2_CTRL_ADDR, offset)
|
||||
#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)
|
||||
#define UART1_REG(offset) _REG32(UART1_CTRL_ADDR, offset)
|
||||
|
||||
// Misc
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
#define NUM_GPIO 32
|
||||
|
||||
#define PLIC_NUM_INTERRUPTS 52
|
||||
#define PLIC_NUM_PRIORITIES 7
|
||||
|
||||
#define HAS_BOARD_BUTTONS
|
||||
#include "hifive1.h"
|
||||
|
||||
unsigned long get_timer_freq(void);
|
||||
uint64_t get_timer_value(void);
|
||||
|
||||
#endif /* _SIFIVE_PLATFORM_H */
|
|
@ -1,3 +0,0 @@
|
|||
# Describes the CPU on this board to the rest of the SDK.
|
||||
RISCV_ARCH := rv32imac
|
||||
RISCV_ABI := ilp32
|
|
@ -1,157 +0,0 @@
|
|||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
ENTRY( _start )
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M
|
||||
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
PHDRS
|
||||
{
|
||||
flash PT_LOAD;
|
||||
ram_init PT_LOAD;
|
||||
ram PT_NULL;
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||
|
||||
.init :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.text.unlikely .text.unlikely.*)
|
||||
*(.text.startup .text.startup.*)
|
||||
*(.text .text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.fini)))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.lalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data_lma = . );
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data = . );
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.rdata)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = . );
|
||||
PROVIDE( edata = . );
|
||||
|
||||
PROVIDE( _fbss = . );
|
||||
PROVIDE( __bss_start = . );
|
||||
.bss :
|
||||
{
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _end = . );
|
||||
PROVIDE( end = . );
|
||||
|
||||
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
|
||||
{
|
||||
PROVIDE( _heap_end = . );
|
||||
. = __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
} >ram AT>ram :ram
|
||||
}
|
|
@ -1,166 +0,0 @@
|
|||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
ENTRY( _start )
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M
|
||||
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 512K
|
||||
}
|
||||
|
||||
PHDRS
|
||||
{
|
||||
flash PT_LOAD;
|
||||
ram_init PT_LOAD;
|
||||
ram PT_NULL;
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||
|
||||
.init :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.text.unlikely .text.unlikely.*)
|
||||
*(.text.startup .text.startup.*)
|
||||
*(.text .text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.fini)))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
|
||||
.rodata :
|
||||
{
|
||||
*(.rdata)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
} >flash AT>flash :flash
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.except :
|
||||
{
|
||||
*(.gcc_except_table.*)
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.lalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data_lma = . );
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data = . );
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = . );
|
||||
PROVIDE( edata = . );
|
||||
|
||||
PROVIDE( _fbss = . );
|
||||
PROVIDE( __bss_start = . );
|
||||
.bss :
|
||||
{
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _end = . );
|
||||
PROVIDE( end = . );
|
||||
|
||||
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
|
||||
{
|
||||
PROVIDE( _heap_end = . );
|
||||
. = __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
} >ram AT>ram :ram
|
||||
}
|
|
@ -1,238 +0,0 @@
|
|||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include "platform.h"
|
||||
#include "encoding.h"
|
||||
|
||||
extern int main(int argc, char** argv);
|
||||
extern void trap_entry();
|
||||
|
||||
static unsigned long mtime_lo(void)
|
||||
{
|
||||
return *(volatile unsigned long *)(CLINT_CTRL_ADDR + CLINT_MTIME);
|
||||
}
|
||||
|
||||
#ifdef __riscv32
|
||||
|
||||
static uint32_t mtime_hi(void)
|
||||
{
|
||||
return *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 4);
|
||||
}
|
||||
|
||||
uint64_t get_timer_value()
|
||||
{
|
||||
while (1) {
|
||||
uint32_t hi = mtime_hi();
|
||||
uint32_t lo = mtime_lo();
|
||||
if (hi == mtime_hi())
|
||||
return ((uint64_t)hi << 32) | lo;
|
||||
}
|
||||
}
|
||||
|
||||
#else /* __riscv32 */
|
||||
|
||||
uint64_t get_timer_value()
|
||||
{
|
||||
return mtime_lo();
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
unsigned long get_timer_freq()
|
||||
{
|
||||
return 32768;
|
||||
}
|
||||
|
||||
static void use_hfrosc(int div, int trim)
|
||||
{
|
||||
// Make sure the HFROSC is running at its default setting
|
||||
PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1));
|
||||
while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0) ;
|
||||
PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1);
|
||||
}
|
||||
|
||||
static void use_pll(int refsel, int bypass, int r, int f, int q)
|
||||
{
|
||||
// Ensure that we aren't running off the PLL before we mess with it.
|
||||
if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) {
|
||||
// Make sure the HFROSC is running at its default setting
|
||||
use_hfrosc(4, 16);
|
||||
}
|
||||
|
||||
// Set PLL Source to be HFXOSC if available.
|
||||
uint32_t config_value = 0;
|
||||
|
||||
config_value |= PLL_REFSEL(refsel);
|
||||
|
||||
if (bypass) {
|
||||
// Bypass
|
||||
config_value |= PLL_BYPASS(1);
|
||||
|
||||
PRCI_REG(PRCI_PLLCFG) = config_value;
|
||||
|
||||
// If we don't have an HFXTAL, this doesn't really matter.
|
||||
// Set our Final output divide to divide-by-1:
|
||||
PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
|
||||
} else {
|
||||
// In case we are executing from QSPI,
|
||||
// (which is quite likely) we need to
|
||||
// set the QSPI clock divider appropriately
|
||||
// before boosting the clock frequency.
|
||||
|
||||
// Div = f_sck/2
|
||||
SPI0_REG(SPI_REG_SCKDIV) = 8;
|
||||
|
||||
// Set DIV Settings for PLL
|
||||
// Both HFROSC and HFXOSC are modeled as ideal
|
||||
// 16MHz sources (assuming dividers are set properly for
|
||||
// HFROSC).
|
||||
// (Legal values of f_REF are 6-48MHz)
|
||||
|
||||
// Set DIVR to divide-by-2 to get 8MHz frequency
|
||||
// (legal values of f_R are 6-12 MHz)
|
||||
|
||||
config_value |= PLL_BYPASS(1);
|
||||
config_value |= PLL_R(r);
|
||||
|
||||
// Set DIVF to get 512Mhz frequncy
|
||||
// There is an implied multiply-by-2, 16Mhz.
|
||||
// So need to write 32-1
|
||||
// (legal values of f_F are 384-768 MHz)
|
||||
config_value |= PLL_F(f);
|
||||
|
||||
// Set DIVQ to divide-by-2 to get 256 MHz frequency
|
||||
// (legal values of f_Q are 50-400Mhz)
|
||||
config_value |= PLL_Q(q);
|
||||
|
||||
// Set our Final output divide to divide-by-1:
|
||||
PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
|
||||
|
||||
PRCI_REG(PRCI_PLLCFG) = config_value;
|
||||
|
||||
// Un-Bypass the PLL.
|
||||
PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1);
|
||||
|
||||
// Wait for PLL Lock
|
||||
// Note that the Lock signal can be glitchy.
|
||||
// Need to wait 100 us
|
||||
// RTC is running at 32kHz.
|
||||
// So wait 4 ticks of RTC.
|
||||
uint32_t now = mtime_lo();
|
||||
while (mtime_lo() - now < 4) ;
|
||||
|
||||
// Now it is safe to check for PLL Lock
|
||||
while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0) ;
|
||||
}
|
||||
|
||||
// Switch over to PLL Clock source
|
||||
PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1);
|
||||
}
|
||||
|
||||
static void use_default_clocks()
|
||||
{
|
||||
// Turn off the LFROSC
|
||||
AON_REG(AON_LFROSC) &= ~ROSC_EN(1);
|
||||
|
||||
// Use HFROSC
|
||||
use_hfrosc(4, 16);
|
||||
}
|
||||
|
||||
static unsigned long __attribute__((noinline)) measure_cpu_freq(size_t n)
|
||||
{
|
||||
unsigned long start_mtime, delta_mtime;
|
||||
unsigned long mtime_freq = get_timer_freq();
|
||||
|
||||
// Don't start measuruing until we see an mtime tick
|
||||
unsigned long tmp = mtime_lo();
|
||||
do {
|
||||
start_mtime = mtime_lo();
|
||||
} while (start_mtime == tmp);
|
||||
|
||||
unsigned long start_mcycle = read_csr(mcycle);
|
||||
|
||||
do {
|
||||
delta_mtime = mtime_lo() - start_mtime;
|
||||
} while (delta_mtime < n);
|
||||
|
||||
unsigned long delta_mcycle = read_csr(mcycle) - start_mcycle;
|
||||
|
||||
return (delta_mcycle / delta_mtime) * mtime_freq
|
||||
+ ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime;
|
||||
}
|
||||
|
||||
unsigned long get_cpu_freq()
|
||||
{
|
||||
static uint32_t cpu_freq;
|
||||
|
||||
if (!cpu_freq) {
|
||||
// warm up I$
|
||||
measure_cpu_freq(1);
|
||||
// measure for real
|
||||
cpu_freq = measure_cpu_freq(10);
|
||||
}
|
||||
|
||||
return cpu_freq;
|
||||
}
|
||||
|
||||
static void uart_init(size_t baud_rate)
|
||||
{
|
||||
GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
|
||||
GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
|
||||
UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1;
|
||||
UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
|
||||
}
|
||||
|
||||
|
||||
|
||||
#ifdef USE_PLIC
|
||||
extern void handle_m_ext_interrupt();
|
||||
#endif
|
||||
|
||||
#ifdef USE_M_TIME
|
||||
extern void handle_m_time_interrupt();
|
||||
#endif
|
||||
|
||||
uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
|
||||
{
|
||||
if (0){
|
||||
#ifdef USE_PLIC
|
||||
// External Machine-Level interrupt from PLIC
|
||||
} else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) {
|
||||
handle_m_ext_interrupt();
|
||||
#endif
|
||||
#ifdef USE_M_TIME
|
||||
// External Machine-Level interrupt from PLIC
|
||||
} else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
|
||||
handle_m_time_interrupt();
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
write(1, "trap\n", 5);
|
||||
_exit(1 + mcause);
|
||||
}
|
||||
return epc;
|
||||
}
|
||||
|
||||
void _init()
|
||||
{
|
||||
|
||||
#ifndef NO_INIT
|
||||
use_default_clocks();
|
||||
use_pll(0, 0, 1, 31, 1);
|
||||
uart_init(115200);
|
||||
|
||||
printf("core freq at %d Hz\n", get_cpu_freq());
|
||||
|
||||
write_csr(mtvec, &trap_entry);
|
||||
if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present
|
||||
write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping
|
||||
write_csr(fcsr, 0); // initialize rounding mode, undefined at reset
|
||||
}
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
void _fini()
|
||||
{
|
||||
}
|
|
@ -1,34 +0,0 @@
|
|||
adapter_khz 10000
|
||||
|
||||
interface ftdi
|
||||
ftdi_device_desc "Dual RS232-HS"
|
||||
ftdi_vid_pid 0x0403 0x6010
|
||||
|
||||
ftdi_layout_init 0x0008 0x001b
|
||||
ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
|
||||
|
||||
#Reset Stretcher logic on FE310 is ~1 second long
|
||||
#This doesn't apply if you use
|
||||
# ftdi_set_signal, but still good to document
|
||||
#adapter_nsrst_delay 1500
|
||||
|
||||
set _CHIPNAME riscv
|
||||
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
|
||||
$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
|
||||
|
||||
flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
|
||||
init
|
||||
#reset -- This type of reset is not implemented yet
|
||||
if {[ info exists pulse_srst]} {
|
||||
ftdi_set_signal nSRST 0
|
||||
ftdi_set_signal nSRST z
|
||||
#Wait for the reset stretcher
|
||||
#It will work without this, but
|
||||
#will incur lots of delays for later commands.
|
||||
sleep 1500
|
||||
}
|
||||
halt
|
||||
#flash protect 0 64 last off
|
|
@ -1,133 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_PLATFORM_H
|
||||
#define _SIFIVE_PLATFORM_H
|
||||
|
||||
// Some things missing from the official encoding.h
|
||||
#define MCAUSE_INT 0x80000000
|
||||
#define MCAUSE_CAUSE 0x7FFFFFFF
|
||||
|
||||
#include "sifive/const.h"
|
||||
#include "sifive/devices/aon.h"
|
||||
#include "sifive/devices/clint.h"
|
||||
#include "sifive/devices/gpio.h"
|
||||
#include "sifive/devices/otp.h"
|
||||
#include "sifive/devices/plic.h"
|
||||
#include "sifive/devices/prci.h"
|
||||
#include "sifive/devices/pwm.h"
|
||||
#include "sifive/devices/spi.h"
|
||||
#include "sifive/devices/uart.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Platform definitions
|
||||
*****************************************************************************/
|
||||
|
||||
// Memory map
|
||||
#define MASKROM_MEM_ADDR _AC(0x00001000,UL)
|
||||
#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL)
|
||||
#define OTP_MEM_ADDR _AC(0x00020000,UL)
|
||||
#define CLINT_CTRL_ADDR _AC(0x02000000,UL)
|
||||
#define PLIC_CTRL_ADDR _AC(0x0C000000,UL)
|
||||
#define AON_CTRL_ADDR _AC(0x10000000,UL)
|
||||
#define PRCI_CTRL_ADDR _AC(0x10008000,UL)
|
||||
#define OTP_CTRL_ADDR _AC(0x10010000,UL)
|
||||
#define GPIO_CTRL_ADDR _AC(0x10012000,UL)
|
||||
#define UART0_CTRL_ADDR _AC(0x10013000,UL)
|
||||
#define SPI0_CTRL_ADDR _AC(0x10014000,UL)
|
||||
#define PWM0_CTRL_ADDR _AC(0x10015000,UL)
|
||||
#define UART1_CTRL_ADDR _AC(0x10023000,UL)
|
||||
#define SPI1_CTRL_ADDR _AC(0x10024000,UL)
|
||||
#define PWM1_CTRL_ADDR _AC(0x10025000,UL)
|
||||
#define SPI2_CTRL_ADDR _AC(0x10034000,UL)
|
||||
#define PWM2_CTRL_ADDR _AC(0x10035000,UL)
|
||||
#define SPI0_MEM_ADDR _AC(0x20000000,UL)
|
||||
#define MEM_CTRL_ADDR _AC(0x80000000,UL)
|
||||
|
||||
// IOF masks
|
||||
#define IOF0_SPI1_MASK _AC(0x000007FC,UL)
|
||||
#define SPI11_NUM_SS (4)
|
||||
#define IOF_SPI1_SS0 (2u)
|
||||
#define IOF_SPI1_SS1 (8u)
|
||||
#define IOF_SPI1_SS2 (9u)
|
||||
#define IOF_SPI1_SS3 (10u)
|
||||
#define IOF_SPI1_MOSI (3u)
|
||||
#define IOF_SPI1_MISO (4u)
|
||||
#define IOF_SPI1_SCK (5u)
|
||||
#define IOF_SPI1_DQ0 (3u)
|
||||
#define IOF_SPI1_DQ1 (4u)
|
||||
#define IOF_SPI1_DQ2 (6u)
|
||||
#define IOF_SPI1_DQ3 (7u)
|
||||
|
||||
#define IOF0_SPI2_MASK _AC(0xFC000000,UL)
|
||||
#define SPI2_NUM_SS (1)
|
||||
#define IOF_SPI2_SS0 (26u)
|
||||
#define IOF_SPI2_MOSI (27u)
|
||||
#define IOF_SPI2_MISO (28u)
|
||||
#define IOF_SPI2_SCK (29u)
|
||||
#define IOF_SPI2_DQ0 (27u)
|
||||
#define IOF_SPI2_DQ1 (28u)
|
||||
#define IOF_SPI2_DQ2 (30u)
|
||||
#define IOF_SPI2_DQ3 (31u)
|
||||
|
||||
//#define IOF0_I2C_MASK _AC(0x00003000,UL)
|
||||
|
||||
#define IOF0_UART0_MASK _AC(0x00030000, UL)
|
||||
#define IOF_UART0_RX (16u)
|
||||
#define IOF_UART0_TX (17u)
|
||||
|
||||
#define IOF0_UART1_MASK _AC(0x03000000, UL)
|
||||
#define IOF_UART1_RX (24u)
|
||||
#define IOF_UART1_TX (25u)
|
||||
|
||||
#define IOF1_PWM0_MASK _AC(0x0000000F, UL)
|
||||
#define IOF1_PWM1_MASK _AC(0x00780000, UL)
|
||||
#define IOF1_PWM2_MASK _AC(0x00003C00, UL)
|
||||
|
||||
// Interrupt numbers
|
||||
#define INT_RESERVED 0
|
||||
#define INT_WDOGCMP 1
|
||||
#define INT_RTCCMP 2
|
||||
#define INT_UART0_BASE 3
|
||||
#define INT_UART1_BASE 4
|
||||
#define INT_SPI0_BASE 5
|
||||
#define INT_SPI1_BASE 6
|
||||
#define INT_SPI2_BASE 7
|
||||
#define INT_GPIO_BASE 8
|
||||
#define INT_PWM0_BASE 40
|
||||
#define INT_PWM1_BASE 44
|
||||
#define INT_PWM2_BASE 48
|
||||
|
||||
// Helper functions
|
||||
#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
|
||||
#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))
|
||||
#define AON_REG(offset) _REG32(AON_CTRL_ADDR, offset)
|
||||
#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
|
||||
#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
|
||||
#define OTP_REG(offset) _REG32(OTP_CTRL_ADDR, offset)
|
||||
#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset)
|
||||
#define PRCI_REG(offset) _REG32(PRCI_CTRL_ADDR, offset)
|
||||
#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset)
|
||||
#define PWM1_REG(offset) _REG32(PWM1_CTRL_ADDR, offset)
|
||||
#define PWM2_REG(offset) _REG32(PWM2_CTRL_ADDR, offset)
|
||||
#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)
|
||||
#define SPI1_REG(offset) _REG32(SPI1_CTRL_ADDR, offset)
|
||||
#define SPI2_REG(offset) _REG32(SPI2_CTRL_ADDR, offset)
|
||||
#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)
|
||||
#define UART1_REG(offset) _REG32(UART1_CTRL_ADDR, offset)
|
||||
|
||||
// Misc
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define NUM_GPIO 32
|
||||
|
||||
#define PLIC_NUM_INTERRUPTS 52
|
||||
#define PLIC_NUM_PRIORITIES 7
|
||||
|
||||
#include "hifive1.h"
|
||||
|
||||
unsigned long get_cpu_freq(void);
|
||||
unsigned long get_timer_freq(void);
|
||||
uint64_t get_timer_value(void);
|
||||
|
||||
#endif /* _SIFIVE_PLATFORM_H */
|
|
@ -1,3 +0,0 @@
|
|||
# Describes the CPU on this board to the rest of the SDK.
|
||||
RISCV_ARCH := rv32imac
|
||||
RISCV_ABI := ilp32
|
|
@ -1,81 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_HIFIVE1_H
|
||||
#define _SIFIVE_HIFIVE1_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/****************************************************************************
|
||||
* GPIO Connections
|
||||
*****************************************************************************/
|
||||
|
||||
// These are the GPIO bit offsets for the RGB LED on HiFive1 Board.
|
||||
// These are also mapped to RGB LEDs on the Freedom E300 Arty
|
||||
// FPGA
|
||||
// Dev Kit.
|
||||
|
||||
#define RED_LED_OFFSET 22
|
||||
#define GREEN_LED_OFFSET 19
|
||||
#define BLUE_LED_OFFSET 21
|
||||
|
||||
// These are the GPIO bit offsets for the differen digital pins
|
||||
// on the headers for both the HiFive1 Board and the Freedom E300 Arty FPGA Dev Kit.
|
||||
#define PIN_0_OFFSET 16
|
||||
#define PIN_1_OFFSET 17
|
||||
#define PIN_2_OFFSET 18
|
||||
#define PIN_3_OFFSET 19
|
||||
#define PIN_4_OFFSET 20
|
||||
#define PIN_5_OFFSET 21
|
||||
#define PIN_6_OFFSET 22
|
||||
#define PIN_7_OFFSET 23
|
||||
#define PIN_8_OFFSET 0
|
||||
#define PIN_9_OFFSET 1
|
||||
#define PIN_10_OFFSET 2
|
||||
#define PIN_11_OFFSET 3
|
||||
#define PIN_12_OFFSET 4
|
||||
#define PIN_13_OFFSET 5
|
||||
//#define PIN_14_OFFSET 8 //This pin is not connected on either board.
|
||||
#define PIN_15_OFFSET 9
|
||||
#define PIN_16_OFFSET 10
|
||||
#define PIN_17_OFFSET 11
|
||||
#define PIN_18_OFFSET 12
|
||||
#define PIN_19_OFFSET 13
|
||||
|
||||
// These are *PIN* numbers, not
|
||||
// GPIO Offset Numbers.
|
||||
#define PIN_SPI1_SCK (13u)
|
||||
#define PIN_SPI1_MISO (12u)
|
||||
#define PIN_SPI1_MOSI (11u)
|
||||
#define PIN_SPI1_SS0 (10u)
|
||||
#define PIN_SPI1_SS1 (14u)
|
||||
#define PIN_SPI1_SS2 (15u)
|
||||
#define PIN_SPI1_SS3 (16u)
|
||||
|
||||
#define SS_PIN_TO_CS_ID(x) \
|
||||
((x==PIN_SPI1_SS0 ? 0 : \
|
||||
(x==PIN_SPI1_SS1 ? 1 : \
|
||||
(x==PIN_SPI1_SS2 ? 2 : \
|
||||
(x==PIN_SPI1_SS3 ? 3 : \
|
||||
-1)))))
|
||||
|
||||
|
||||
// These buttons are present only on the Freedom E300 Arty Dev Kit.
|
||||
#ifdef HAS_BOARD_BUTTONS
|
||||
#define BUTTON_0_OFFSET 15
|
||||
#define BUTTON_1_OFFSET 30
|
||||
#define BUTTON_2_OFFSET 31
|
||||
|
||||
#define INT_DEVICE_BUTTON_0 (INT_GPIO_BASE + BUTTON_0_OFFSET)
|
||||
#define INT_DEVICE_BUTTON_1 (INT_GPIO_BASE + BUTTON_1_OFFSET)
|
||||
#define INT_DEVICE_BUTTON_2 (INT_GPIO_BASE + BUTTON_2_OFFSET)
|
||||
|
||||
#endif
|
||||
|
||||
#define HAS_HFXOSC 1
|
||||
#define HAS_LFROSC_BYPASS 1
|
||||
|
||||
#define RTC_FREQ 32768
|
||||
|
||||
void write_hex(int fd, unsigned long int hex);
|
||||
|
||||
#endif /* _SIFIVE_HIFIVE1_H */
|
|
@ -1,111 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
#include <sifive/smp.h>
|
||||
|
||||
/* This is defined in sifive/platform.h, but that can't be included from
|
||||
* assembly. */
|
||||
#define CLINT_CTRL_ADDR 0x02000000
|
||||
|
||||
.section .init
|
||||
.globl _start
|
||||
.type _start,@function
|
||||
|
||||
_start:
|
||||
.cfi_startproc
|
||||
.cfi_undefined ra
|
||||
.option push
|
||||
.option norelax
|
||||
la gp, __global_pointer$
|
||||
.option pop
|
||||
la sp, _sp
|
||||
|
||||
#if defined(ENABLE_SMP)
|
||||
smp_pause(t0, t1)
|
||||
#endif
|
||||
|
||||
/* Load data section */
|
||||
la a0, _data_lma
|
||||
la a1, _data
|
||||
la a2, _edata
|
||||
bgeu a1, a2, 2f
|
||||
1:
|
||||
lw t0, (a0)
|
||||
sw t0, (a1)
|
||||
addi a0, a0, 4
|
||||
addi a1, a1, 4
|
||||
bltu a1, a2, 1b
|
||||
2:
|
||||
|
||||
/* Clear bss section */
|
||||
la a0, __bss_start
|
||||
la a1, _end
|
||||
bgeu a0, a1, 2f
|
||||
1:
|
||||
sw zero, (a0)
|
||||
addi a0, a0, 4
|
||||
bltu a0, a1, 1b
|
||||
2:
|
||||
|
||||
/* Call global constructors */
|
||||
la a0, __libc_fini_array
|
||||
call atexit
|
||||
call __libc_init_array
|
||||
|
||||
#ifndef __riscv_float_abi_soft
|
||||
/* Enable FPU */
|
||||
li t0, MSTATUS_FS
|
||||
csrs mstatus, t0
|
||||
csrr t1, mstatus
|
||||
and t1, t1, t0
|
||||
beqz t1, 1f
|
||||
fssr x0
|
||||
1:
|
||||
#endif
|
||||
|
||||
#if defined(ENABLE_SMP)
|
||||
smp_resume(t0, t1)
|
||||
|
||||
csrr a0, mhartid
|
||||
bnez a0, 2f
|
||||
#endif
|
||||
|
||||
auipc ra, 0
|
||||
addi sp, sp, -16
|
||||
#if __riscv_xlen == 32
|
||||
sw ra, 8(sp)
|
||||
#else
|
||||
sd ra, 8(sp)
|
||||
#endif
|
||||
|
||||
/* argc = argv = 0 */
|
||||
li a0, 0
|
||||
li a1, 0
|
||||
call main
|
||||
tail exit
|
||||
1:
|
||||
j 1b
|
||||
|
||||
#if defined(ENABLE_SMP)
|
||||
2:
|
||||
la t0, trap_entry
|
||||
csrw mtvec, t0
|
||||
|
||||
csrr a0, mhartid
|
||||
la t1, _sp
|
||||
slli t0, a0, 10
|
||||
sub sp, t1, t0
|
||||
|
||||
auipc ra, 0
|
||||
addi sp, sp, -16
|
||||
#if __riscv_xlen == 32
|
||||
sw ra, 8(sp)
|
||||
#else
|
||||
sd ra, 8(sp)
|
||||
#endif
|
||||
|
||||
call secondary_main
|
||||
tail exit
|
||||
|
||||
1:
|
||||
j 1b
|
||||
#endif
|
||||
.cfi_endproc
|
|
@ -1,288 +0,0 @@
|
|||
// See LICENSE for license details
|
||||
|
||||
#ifndef VENTRY_S
|
||||
#define VENTRY_S
|
||||
|
||||
#include "encoding.h"
|
||||
#include "sifive/bits.h"
|
||||
|
||||
#only save caller registers
|
||||
.macro TRAP_ENTRY
|
||||
addi sp, sp, -16*REGBYTES
|
||||
|
||||
STORE x1, 0*REGBYTES(sp)
|
||||
STORE x5, 1*REGBYTES(sp)
|
||||
STORE x6, 2*REGBYTES(sp)
|
||||
STORE x7, 3*REGBYTES(sp)
|
||||
STORE x10, 4*REGBYTES(sp)
|
||||
STORE x11, 5*REGBYTES(sp)
|
||||
STORE x12, 6*REGBYTES(sp)
|
||||
STORE x13, 7*REGBYTES(sp)
|
||||
STORE x14, 8*REGBYTES(sp)
|
||||
STORE x15, 9*REGBYTES(sp)
|
||||
STORE x16, 10*REGBYTES(sp)
|
||||
STORE x17, 11*REGBYTES(sp)
|
||||
STORE x28, 12*REGBYTES(sp)
|
||||
STORE x29, 13*REGBYTES(sp)
|
||||
STORE x30, 14*REGBYTES(sp)
|
||||
STORE x31, 15*REGBYTES(sp)
|
||||
.endm
|
||||
|
||||
#restore caller registers
|
||||
.macro TRAP_EXIT
|
||||
# Remain in M-mode after mret
|
||||
li t0, MSTATUS_MPP
|
||||
csrs mstatus, t0
|
||||
|
||||
LOAD x1, 0*REGBYTES(sp)
|
||||
LOAD x5, 1*REGBYTES(sp)
|
||||
LOAD x6, 2*REGBYTES(sp)
|
||||
LOAD x7, 3*REGBYTES(sp)
|
||||
LOAD x10, 4*REGBYTES(sp)
|
||||
LOAD x11, 5*REGBYTES(sp)
|
||||
LOAD x12, 6*REGBYTES(sp)
|
||||
LOAD x13, 7*REGBYTES(sp)
|
||||
LOAD x14, 8*REGBYTES(sp)
|
||||
LOAD x15, 9*REGBYTES(sp)
|
||||
LOAD x16, 10*REGBYTES(sp)
|
||||
LOAD x17, 11*REGBYTES(sp)
|
||||
LOAD x28, 12*REGBYTES(sp)
|
||||
LOAD x29, 13*REGBYTES(sp)
|
||||
LOAD x30, 14*REGBYTES(sp)
|
||||
LOAD x31, 15*REGBYTES(sp)
|
||||
|
||||
addi sp, sp, 16*REGBYTES
|
||||
mret
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
#Vector table for E31/E51
|
||||
|
||||
.section .text.entry
|
||||
.align 8
|
||||
.global vtrap_entry
|
||||
vtrap_entry:
|
||||
j sync_trap
|
||||
.align 2
|
||||
j reserved
|
||||
.align 2
|
||||
j reserved
|
||||
.align 2
|
||||
j vmsi_Handler
|
||||
.align 2
|
||||
j reserved
|
||||
.align 2
|
||||
j reserved
|
||||
.align 2
|
||||
j reserved
|
||||
.align 2
|
||||
j vmti_Handler
|
||||
.align 2
|
||||
j reserved
|
||||
.align 2
|
||||
j reserved
|
||||
.align 2
|
||||
j reserved
|
||||
.align 2
|
||||
j vmei_Handler
|
||||
.align 2
|
||||
j reserved
|
||||
.align 2
|
||||
j reserved
|
||||
.align 2
|
||||
j reserved
|
||||
.align 2
|
||||
j reserved
|
||||
.align 2
|
||||
j vlip_Handler0
|
||||
.align 2
|
||||
j vlip_Handler1
|
||||
.align 2
|
||||
j vlip_Handler2
|
||||
.align 2
|
||||
j vlip_Handler3
|
||||
.align 2
|
||||
j vlip_Handler4
|
||||
.align 2
|
||||
j vlip_Handler5
|
||||
.align 2
|
||||
j vlip_Handler6
|
||||
.align 2
|
||||
j vlip_Handler7
|
||||
.align 2
|
||||
j vlip_Handler8
|
||||
.align 2
|
||||
j vlip_Handler9
|
||||
.align 2
|
||||
j vlip_Handler10
|
||||
.align 2
|
||||
j vlip_Handler11
|
||||
.align 2
|
||||
j vlip_Handler12
|
||||
.align 2
|
||||
j vlip_Handler13
|
||||
.align 2
|
||||
j vlip_Handler14
|
||||
.align 2
|
||||
j vlip_Handler15
|
||||
|
||||
#synchronous trap
|
||||
sync_trap:
|
||||
TRAP_ENTRY
|
||||
jal handle_sync_trap
|
||||
TRAP_EXIT
|
||||
|
||||
#Machine Software Interrupt
|
||||
vmsi_Handler:
|
||||
TRAP_ENTRY
|
||||
jal reserved
|
||||
TRAP_EXIT
|
||||
|
||||
#Machine Timer Interrupt
|
||||
vmti_Handler:
|
||||
TRAP_ENTRY
|
||||
jal handle_m_time_interrupt
|
||||
TRAP_EXIT
|
||||
|
||||
#Machine External Interrupt
|
||||
vmei_Handler:
|
||||
TRAP_ENTRY
|
||||
jal handle_m_external_interrupt
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP0
|
||||
vlip_Handler0:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt0
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP1
|
||||
vlip_Handler1:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt1
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP2
|
||||
vlip_Handler2:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt2
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP3
|
||||
vlip_Handler3:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt3
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP4
|
||||
vlip_Handler4:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt4
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP5
|
||||
vlip_Handler5:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt5
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP6
|
||||
vlip_Handler6:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt6
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP7
|
||||
vlip_Handler7:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt7
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP8
|
||||
vlip_Handler8:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt8
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP9
|
||||
vlip_Handler9:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt9
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP10
|
||||
vlip_Handler10:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt10
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP11
|
||||
vlip_Handler11:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt11
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP12
|
||||
vlip_Handler12:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt12
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP13
|
||||
vlip_Handler13:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt13
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP14
|
||||
vlip_Handler14:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt14
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP15
|
||||
vlip_Handler15:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt15
|
||||
TRAP_EXIT
|
||||
|
||||
#unimplemented ISRs trap here
|
||||
.weak reserved
|
||||
reserved:
|
||||
.weak handle_local_interrupt0
|
||||
handle_local_interrupt0:
|
||||
.weak handle_local_interrupt1
|
||||
handle_local_interrupt1:
|
||||
.weak handle_local_interrupt2
|
||||
handle_local_interrupt2:
|
||||
.weak handle_local_interrupt3
|
||||
handle_local_interrupt3:
|
||||
.weak handle_local_interrupt4
|
||||
handle_local_interrupt4:
|
||||
.weak handle_local_interrupt5
|
||||
handle_local_interrupt5:
|
||||
.weak handle_local_interrupt6
|
||||
handle_local_interrupt6:
|
||||
.weak handle_local_interrupt7
|
||||
handle_local_interrupt7:
|
||||
.weak handle_local_interrupt8
|
||||
handle_local_interrupt8:
|
||||
.weak handle_local_interrupt9
|
||||
handle_local_interrupt9:
|
||||
.weak handle_local_interrupt10
|
||||
handle_local_interrupt10:
|
||||
.weak handle_local_interrupt11
|
||||
handle_local_interrupt11:
|
||||
.weak handle_local_interrupt12
|
||||
handle_local_interrupt12:
|
||||
.weak handle_local_interrupt13
|
||||
handle_local_interrupt13:
|
||||
.weak handle_local_interrupt14
|
||||
handle_local_interrupt14:
|
||||
.weak handle_local_interrupt15
|
||||
handle_local_interrupt15:
|
||||
1:
|
||||
j 1b
|
||||
|
||||
#endif
|
|
@ -1,36 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
#ifndef _RISCV_BITS_H
|
||||
#define _RISCV_BITS_H
|
||||
|
||||
#define likely(x) __builtin_expect((x), 1)
|
||||
#define unlikely(x) __builtin_expect((x), 0)
|
||||
|
||||
#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b))
|
||||
#define ROUNDDOWN(a, b) ((a)/(b)*(b))
|
||||
|
||||
#define MAX(a, b) ((a) > (b) ? (a) : (b))
|
||||
#define MIN(a, b) ((a) < (b) ? (a) : (b))
|
||||
#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
|
||||
|
||||
#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1)))
|
||||
#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
|
||||
|
||||
#define STR(x) XSTR(x)
|
||||
#define XSTR(x) #x
|
||||
|
||||
#if __riscv_xlen == 64
|
||||
# define SLL32 sllw
|
||||
# define STORE sd
|
||||
# define LOAD ld
|
||||
# define LWU lwu
|
||||
# define LOG_REGBYTES 3
|
||||
#else
|
||||
# define SLL32 sll
|
||||
# define STORE sw
|
||||
# define LOAD lw
|
||||
# define LWU lw
|
||||
# define LOG_REGBYTES 2
|
||||
#endif
|
||||
#define REGBYTES (1 << LOG_REGBYTES)
|
||||
|
||||
#endif
|
|
@ -1,18 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
/* Derived from <linux/const.h> */
|
||||
|
||||
#ifndef _SIFIVE_CONST_H
|
||||
#define _SIFIVE_CONST_H
|
||||
|
||||
#ifdef __ASSEMBLER__
|
||||
#define _AC(X,Y) X
|
||||
#define _AT(T,X) X
|
||||
#else
|
||||
#define _AC(X,Y) (X##Y)
|
||||
#define _AT(T,X) ((T)(X))
|
||||
#endif /* !__ASSEMBLER__*/
|
||||
|
||||
#define _BITUL(x) (_AC(1,UL) << (x))
|
||||
#define _BITULL(x) (_AC(1,ULL) << (x))
|
||||
|
||||
#endif /* _SIFIVE_CONST_H */
|
|
@ -1,88 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_AON_H
|
||||
#define _SIFIVE_AON_H
|
||||
|
||||
/* Register offsets */
|
||||
|
||||
#define AON_WDOGCFG 0x000
|
||||
#define AON_WDOGCOUNT 0x008
|
||||
#define AON_WDOGS 0x010
|
||||
#define AON_WDOGFEED 0x018
|
||||
#define AON_WDOGKEY 0x01C
|
||||
#define AON_WDOGCMP 0x020
|
||||
|
||||
#define AON_RTCCFG 0x040
|
||||
#define AON_RTCLO 0x048
|
||||
#define AON_RTCHI 0x04C
|
||||
#define AON_RTCS 0x050
|
||||
#define AON_RTCCMP 0x060
|
||||
|
||||
#define AON_BACKUP0 0x080
|
||||
#define AON_BACKUP1 0x084
|
||||
#define AON_BACKUP2 0x088
|
||||
#define AON_BACKUP3 0x08C
|
||||
#define AON_BACKUP4 0x090
|
||||
#define AON_BACKUP5 0x094
|
||||
#define AON_BACKUP6 0x098
|
||||
#define AON_BACKUP7 0x09C
|
||||
#define AON_BACKUP8 0x0A0
|
||||
#define AON_BACKUP9 0x0A4
|
||||
#define AON_BACKUP10 0x0A8
|
||||
#define AON_BACKUP11 0x0AC
|
||||
#define AON_BACKUP12 0x0B0
|
||||
#define AON_BACKUP13 0x0B4
|
||||
#define AON_BACKUP14 0x0B8
|
||||
#define AON_BACKUP15 0x0BC
|
||||
|
||||
#define AON_PMUWAKEUPI0 0x100
|
||||
#define AON_PMUWAKEUPI1 0x104
|
||||
#define AON_PMUWAKEUPI2 0x108
|
||||
#define AON_PMUWAKEUPI3 0x10C
|
||||
#define AON_PMUWAKEUPI4 0x110
|
||||
#define AON_PMUWAKEUPI5 0x114
|
||||
#define AON_PMUWAKEUPI6 0x118
|
||||
#define AON_PMUWAKEUPI7 0x11C
|
||||
#define AON_PMUSLEEPI0 0x120
|
||||
#define AON_PMUSLEEPI1 0x124
|
||||
#define AON_PMUSLEEPI2 0x128
|
||||
#define AON_PMUSLEEPI3 0x12C
|
||||
#define AON_PMUSLEEPI4 0x130
|
||||
#define AON_PMUSLEEPI5 0x134
|
||||
#define AON_PMUSLEEPI6 0x138
|
||||
#define AON_PMUSLEEPI7 0x13C
|
||||
#define AON_PMUIE 0x140
|
||||
#define AON_PMUCAUSE 0x144
|
||||
#define AON_PMUSLEEP 0x148
|
||||
#define AON_PMUKEY 0x14C
|
||||
|
||||
#define AON_LFROSC 0x070
|
||||
/* Constants */
|
||||
|
||||
#define AON_WDOGKEY_VALUE 0x51F15E
|
||||
#define AON_WDOGFEED_VALUE 0xD09F00D
|
||||
|
||||
#define AON_WDOGCFG_SCALE 0x0000000F
|
||||
#define AON_WDOGCFG_RSTEN 0x00000100
|
||||
#define AON_WDOGCFG_ZEROCMP 0x00000200
|
||||
#define AON_WDOGCFG_ENALWAYS 0x00001000
|
||||
#define AON_WDOGCFG_ENCOREAWAKE 0x00002000
|
||||
#define AON_WDOGCFG_CMPIP 0x10000000
|
||||
|
||||
#define AON_RTCCFG_SCALE 0x0000000F
|
||||
#define AON_RTCCFG_ENALWAYS 0x00001000
|
||||
#define AON_RTCCFG_CMPIP 0x10000000
|
||||
|
||||
#define AON_WAKEUPCAUSE_RESET 0x00
|
||||
#define AON_WAKEUPCAUSE_RTC 0x01
|
||||
#define AON_WAKEUPCAUSE_DWAKEUP 0x02
|
||||
#define AON_WAKEUPCAUSE_AWAKEUP 0x03
|
||||
|
||||
#define AON_RESETCAUSE_POWERON 0x0000
|
||||
#define AON_RESETCAUSE_EXTERNAL 0x0100
|
||||
#define AON_RESETCAUSE_WATCHDOG 0x0200
|
||||
|
||||
#define AON_PMUCAUSE_WAKEUPCAUSE 0x00FF
|
||||
#define AON_PMUCAUSE_RESETCAUSE 0xFF00
|
||||
|
||||
#endif /* _SIFIVE_AON_H */
|
|
@ -1,30 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_CLIC_H
|
||||
#define _SIFIVE_CLIC_H
|
||||
|
||||
#define CLIC_HART0 0x00800000
|
||||
#define CLIC_MSIP 0x0000
|
||||
#define CLIC_MSIP_size 0x4
|
||||
#define CLIC_MTIMECMP 0x4000
|
||||
#define CLIC_MTIMECMP_size 0x8
|
||||
#define CLIC_MTIME 0xBFF8
|
||||
#define CLIC_MTIME_size 0x8
|
||||
|
||||
#define CLIC_INTIP 0x000
|
||||
#define CLIC_INTIE 0x400
|
||||
#define CLIC_INTCFG 0x800
|
||||
#define CLIC_CFG 0xc00
|
||||
|
||||
// These interrupt IDs are consistent across old and new mtvec modes
|
||||
#define SSIPID 1
|
||||
#define MSIPID 3
|
||||
#define STIPID 5
|
||||
#define MTIPID 7
|
||||
#define SEIPID 9
|
||||
#define MEIPID 11
|
||||
#define CSIPID 12
|
||||
#define LOCALINTIDBASE 16
|
||||
|
||||
|
||||
#endif /* _SIFIVE_CLIC_H */
|
|
@ -1,14 +0,0 @@
|
|||
// See LICENSE for license details
|
||||
|
||||
#ifndef _SIFIVE_CLINT_H
|
||||
#define _SIFIVE_CLINT_H
|
||||
|
||||
|
||||
#define CLINT_MSIP 0x0000
|
||||
#define CLINT_MSIP_size 0x4
|
||||
#define CLINT_MTIMECMP 0x4000
|
||||
#define CLINT_MTIMECMP_size 0x8
|
||||
#define CLINT_MTIME 0xBFF8
|
||||
#define CLINT_MTIME_size 0x8
|
||||
|
||||
#endif /* _SIFIVE_CLINT_H */
|
|
@ -1,24 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_GPIO_H
|
||||
#define _SIFIVE_GPIO_H
|
||||
|
||||
#define GPIO_INPUT_VAL (0x00)
|
||||
#define GPIO_INPUT_EN (0x04)
|
||||
#define GPIO_OUTPUT_EN (0x08)
|
||||
#define GPIO_OUTPUT_VAL (0x0C)
|
||||
#define GPIO_PULLUP_EN (0x10)
|
||||
#define GPIO_DRIVE (0x14)
|
||||
#define GPIO_RISE_IE (0x18)
|
||||
#define GPIO_RISE_IP (0x1C)
|
||||
#define GPIO_FALL_IE (0x20)
|
||||
#define GPIO_FALL_IP (0x24)
|
||||
#define GPIO_HIGH_IE (0x28)
|
||||
#define GPIO_HIGH_IP (0x2C)
|
||||
#define GPIO_LOW_IE (0x30)
|
||||
#define GPIO_LOW_IP (0x34)
|
||||
#define GPIO_IOF_EN (0x38)
|
||||
#define GPIO_IOF_SEL (0x3C)
|
||||
#define GPIO_OUTPUT_XOR (0x40)
|
||||
|
||||
#endif /* _SIFIVE_GPIO_H */
|
|
@ -1,23 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_OTP_H
|
||||
#define _SIFIVE_OTP_H
|
||||
|
||||
/* Register offsets */
|
||||
|
||||
#define OTP_LOCK 0x00
|
||||
#define OTP_CK 0x04
|
||||
#define OTP_OE 0x08
|
||||
#define OTP_SEL 0x0C
|
||||
#define OTP_WE 0x10
|
||||
#define OTP_MR 0x14
|
||||
#define OTP_MRR 0x18
|
||||
#define OTP_MPP 0x1C
|
||||
#define OTP_VRREN 0x20
|
||||
#define OTP_VPPEN 0x24
|
||||
#define OTP_A 0x28
|
||||
#define OTP_D 0x2C
|
||||
#define OTP_Q 0x30
|
||||
#define OTP_READ_TIMINGS 0x34
|
||||
|
||||
#endif
|
|
@ -1,31 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef PLIC_H
|
||||
#define PLIC_H
|
||||
|
||||
#include <sifive/const.h>
|
||||
|
||||
// 32 bits per source
|
||||
#define PLIC_PRIORITY_OFFSET _AC(0x0000,UL)
|
||||
#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2
|
||||
// 1 bit per source (1 address)
|
||||
#define PLIC_PENDING_OFFSET _AC(0x1000,UL)
|
||||
#define PLIC_PENDING_SHIFT_PER_SOURCE 0
|
||||
|
||||
//0x80 per target
|
||||
#define PLIC_ENABLE_OFFSET _AC(0x2000,UL)
|
||||
#define PLIC_ENABLE_SHIFT_PER_TARGET 7
|
||||
|
||||
|
||||
#define PLIC_THRESHOLD_OFFSET _AC(0x200000,UL)
|
||||
#define PLIC_CLAIM_OFFSET _AC(0x200004,UL)
|
||||
#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12
|
||||
#define PLIC_CLAIM_SHIFT_PER_TARGET 12
|
||||
|
||||
#define PLIC_MAX_SOURCE 1023
|
||||
#define PLIC_SOURCE_MASK 0x3FF
|
||||
|
||||
#define PLIC_MAX_TARGET 15871
|
||||
#define PLIC_TARGET_MASK 0x3FFF
|
||||
|
||||
#endif /* PLIC_H */
|
|
@ -1,56 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_PRCI_H
|
||||
#define _SIFIVE_PRCI_H
|
||||
|
||||
/* Register offsets */
|
||||
|
||||
#define PRCI_HFROSCCFG (0x0000)
|
||||
#define PRCI_HFXOSCCFG (0x0004)
|
||||
#define PRCI_PLLCFG (0x0008)
|
||||
#define PRCI_PLLDIV (0x000C)
|
||||
#define PRCI_PROCMONCFG (0x00F0)
|
||||
|
||||
/* Fields */
|
||||
#define ROSC_DIV(x) (((x) & 0x2F) << 0 )
|
||||
#define ROSC_TRIM(x) (((x) & 0x1F) << 16)
|
||||
#define ROSC_EN(x) (((x) & 0x1 ) << 30)
|
||||
#define ROSC_RDY(x) (((x) & 0x1 ) << 31)
|
||||
|
||||
#define XOSC_EN(x) (((x) & 0x1) << 30)
|
||||
#define XOSC_RDY(x) (((x) & 0x1) << 31)
|
||||
|
||||
#define PLL_R(x) (((x) & 0x7) << 0)
|
||||
// single reserved bit for F LSB.
|
||||
#define PLL_F(x) (((x) & 0x3F) << 4)
|
||||
#define PLL_Q(x) (((x) & 0x3) << 10)
|
||||
#define PLL_SEL(x) (((x) & 0x1) << 16)
|
||||
#define PLL_REFSEL(x) (((x) & 0x1) << 17)
|
||||
#define PLL_BYPASS(x) (((x) & 0x1) << 18)
|
||||
#define PLL_LOCK(x) (((x) & 0x1) << 31)
|
||||
|
||||
#define PLL_R_default 0x1
|
||||
#define PLL_F_default 0x1F
|
||||
#define PLL_Q_default 0x3
|
||||
|
||||
#define PLL_REFSEL_HFROSC 0x0
|
||||
#define PLL_REFSEL_HFXOSC 0x1
|
||||
|
||||
#define PLL_SEL_HFROSC 0x0
|
||||
#define PLL_SEL_PLL 0x1
|
||||
|
||||
#define PLL_FINAL_DIV(x) (((x) & 0x3F) << 0)
|
||||
#define PLL_FINAL_DIV_BY_1(x) (((x) & 0x1 ) << 8)
|
||||
|
||||
#define PROCMON_DIV(x) (((x) & 0x1F) << 0)
|
||||
#define PROCMON_TRIM(x) (((x) & 0x1F) << 8)
|
||||
#define PROCMON_EN(x) (((x) & 0x1) << 16)
|
||||
#define PROCMON_SEL(x) (((x) & 0x3) << 24)
|
||||
#define PROCMON_NT_EN(x) (((x) & 0x1) << 28)
|
||||
|
||||
#define PROCMON_SEL_HFCLK 0
|
||||
#define PROCMON_SEL_HFXOSCIN 1
|
||||
#define PROCMON_SEL_PLLOUTDIV 2
|
||||
#define PROCMON_SEL_PROCMON 3
|
||||
|
||||
#endif // _SIFIVE_PRCI_H
|
|
@ -1,37 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_PWM_H
|
||||
#define _SIFIVE_PWM_H
|
||||
|
||||
/* Register offsets */
|
||||
|
||||
#define PWM_CFG 0x00
|
||||
#define PWM_COUNT 0x08
|
||||
#define PWM_S 0x10
|
||||
#define PWM_CMP0 0x20
|
||||
#define PWM_CMP1 0x24
|
||||
#define PWM_CMP2 0x28
|
||||
#define PWM_CMP3 0x2C
|
||||
|
||||
/* Constants */
|
||||
|
||||
#define PWM_CFG_SCALE 0x0000000F
|
||||
#define PWM_CFG_STICKY 0x00000100
|
||||
#define PWM_CFG_ZEROCMP 0x00000200
|
||||
#define PWM_CFG_DEGLITCH 0x00000400
|
||||
#define PWM_CFG_ENALWAYS 0x00001000
|
||||
#define PWM_CFG_ONESHOT 0x00002000
|
||||
#define PWM_CFG_CMP0CENTER 0x00010000
|
||||
#define PWM_CFG_CMP1CENTER 0x00020000
|
||||
#define PWM_CFG_CMP2CENTER 0x00040000
|
||||
#define PWM_CFG_CMP3CENTER 0x00080000
|
||||
#define PWM_CFG_CMP0GANG 0x01000000
|
||||
#define PWM_CFG_CMP1GANG 0x02000000
|
||||
#define PWM_CFG_CMP2GANG 0x04000000
|
||||
#define PWM_CFG_CMP3GANG 0x08000000
|
||||
#define PWM_CFG_CMP0IP 0x10000000
|
||||
#define PWM_CFG_CMP1IP 0x20000000
|
||||
#define PWM_CFG_CMP2IP 0x40000000
|
||||
#define PWM_CFG_CMP3IP 0x80000000
|
||||
|
||||
#endif /* _SIFIVE_PWM_H */
|
|
@ -1,80 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_SPI_H
|
||||
#define _SIFIVE_SPI_H
|
||||
|
||||
/* Register offsets */
|
||||
|
||||
#define SPI_REG_SCKDIV 0x00
|
||||
#define SPI_REG_SCKMODE 0x04
|
||||
#define SPI_REG_CSID 0x10
|
||||
#define SPI_REG_CSDEF 0x14
|
||||
#define SPI_REG_CSMODE 0x18
|
||||
|
||||
#define SPI_REG_DCSSCK 0x28
|
||||
#define SPI_REG_DSCKCS 0x2a
|
||||
#define SPI_REG_DINTERCS 0x2c
|
||||
#define SPI_REG_DINTERXFR 0x2e
|
||||
|
||||
#define SPI_REG_FMT 0x40
|
||||
#define SPI_REG_TXFIFO 0x48
|
||||
#define SPI_REG_RXFIFO 0x4c
|
||||
#define SPI_REG_TXCTRL 0x50
|
||||
#define SPI_REG_RXCTRL 0x54
|
||||
|
||||
#define SPI_REG_FCTRL 0x60
|
||||
#define SPI_REG_FFMT 0x64
|
||||
|
||||
#define SPI_REG_IE 0x70
|
||||
#define SPI_REG_IP 0x74
|
||||
|
||||
/* Fields */
|
||||
|
||||
#define SPI_SCK_PHA 0x1
|
||||
#define SPI_SCK_POL 0x2
|
||||
|
||||
#define SPI_FMT_PROTO(x) ((x) & 0x3)
|
||||
#define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2)
|
||||
#define SPI_FMT_DIR(x) (((x) & 0x1) << 3)
|
||||
#define SPI_FMT_LEN(x) (((x) & 0xf) << 16)
|
||||
|
||||
/* TXCTRL register */
|
||||
#define SPI_TXWM(x) ((x) & 0xffff)
|
||||
/* RXCTRL register */
|
||||
#define SPI_RXWM(x) ((x) & 0xffff)
|
||||
|
||||
#define SPI_IP_TXWM 0x1
|
||||
#define SPI_IP_RXWM 0x2
|
||||
|
||||
#define SPI_FCTRL_EN 0x1
|
||||
|
||||
#define SPI_INSN_CMD_EN 0x1
|
||||
#define SPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1)
|
||||
#define SPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4)
|
||||
#define SPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8)
|
||||
#define SPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10)
|
||||
#define SPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12)
|
||||
#define SPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16)
|
||||
#define SPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24)
|
||||
|
||||
#define SPI_TXFIFO_FULL (1 << 31)
|
||||
#define SPI_RXFIFO_EMPTY (1 << 31)
|
||||
|
||||
/* Values */
|
||||
|
||||
#define SPI_CSMODE_AUTO 0
|
||||
#define SPI_CSMODE_HOLD 2
|
||||
#define SPI_CSMODE_OFF 3
|
||||
|
||||
#define SPI_DIR_RX 0
|
||||
#define SPI_DIR_TX 1
|
||||
|
||||
#define SPI_PROTO_S 0
|
||||
#define SPI_PROTO_D 1
|
||||
#define SPI_PROTO_Q 2
|
||||
|
||||
#define SPI_ENDIAN_MSB 0
|
||||
#define SPI_ENDIAN_LSB 1
|
||||
|
||||
|
||||
#endif /* _SIFIVE_SPI_H */
|
|
@ -1,27 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_UART_H
|
||||
#define _SIFIVE_UART_H
|
||||
|
||||
/* Register offsets */
|
||||
#define UART_REG_TXFIFO 0x00
|
||||
#define UART_REG_RXFIFO 0x04
|
||||
#define UART_REG_TXCTRL 0x08
|
||||
#define UART_REG_RXCTRL 0x0c
|
||||
#define UART_REG_IE 0x10
|
||||
#define UART_REG_IP 0x14
|
||||
#define UART_REG_DIV 0x18
|
||||
|
||||
/* TXCTRL register */
|
||||
#define UART_TXEN 0x1
|
||||
#define UART_TXWM(x) (((x) & 0xffff) << 16)
|
||||
|
||||
/* RXCTRL register */
|
||||
#define UART_RXEN 0x1
|
||||
#define UART_RXWM(x) (((x) & 0xffff) << 16)
|
||||
|
||||
/* IP register */
|
||||
#define UART_IP_TXWM 0x1
|
||||
#define UART_IP_RXWM 0x2
|
||||
|
||||
#endif /* _SIFIVE_UART_H */
|
|
@ -1,17 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
#ifndef _SECTIONS_H
|
||||
#define _SECTIONS_H
|
||||
|
||||
extern unsigned char _rom[];
|
||||
extern unsigned char _rom_end[];
|
||||
|
||||
extern unsigned char _ram[];
|
||||
extern unsigned char _ram_end[];
|
||||
|
||||
extern unsigned char _ftext[];
|
||||
extern unsigned char _etext[];
|
||||
extern unsigned char _fbss[];
|
||||
extern unsigned char _ebss[];
|
||||
extern unsigned char _end[];
|
||||
|
||||
#endif /* _SECTIONS_H */
|
|
@ -1,65 +0,0 @@
|
|||
#ifndef SIFIVE_SMP
|
||||
#define SIFIVE_SMP
|
||||
|
||||
// The maximum number of HARTs this code supports
|
||||
#ifndef MAX_HARTS
|
||||
#define MAX_HARTS 32
|
||||
#endif
|
||||
#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS*4)
|
||||
|
||||
// The hart that non-SMP tests should run on
|
||||
#ifndef NONSMP_HART
|
||||
#define NONSMP_HART 0
|
||||
#endif
|
||||
|
||||
/* If your test cannot handle multiple-threads, use this:
|
||||
* smp_disable(reg1)
|
||||
*/
|
||||
#define smp_disable(reg1, reg2) \
|
||||
csrr reg1, mhartid ;\
|
||||
li reg2, NONSMP_HART ;\
|
||||
beq reg1, reg2, hart0_entry ;\
|
||||
42: ;\
|
||||
wfi ;\
|
||||
j 42b ;\
|
||||
hart0_entry:
|
||||
|
||||
/* If your test needs to temporarily block multiple-threads, do this:
|
||||
* smp_pause(reg1, reg2)
|
||||
* ... single-threaded work ...
|
||||
* smp_resume(reg1, reg2)
|
||||
* ... multi-threaded work ...
|
||||
*/
|
||||
|
||||
#define smp_pause(reg1, reg2) \
|
||||
li reg2, 0x8 ;\
|
||||
csrw mie, reg2 ;\
|
||||
csrr reg2, mhartid ;\
|
||||
bnez reg2, 42f
|
||||
|
||||
#define smp_resume(reg1, reg2) \
|
||||
li reg1, CLINT_CTRL_ADDR ;\
|
||||
41: ;\
|
||||
li reg2, 1 ;\
|
||||
sw reg2, 0(reg1) ;\
|
||||
addi reg1, reg1, 4 ;\
|
||||
li reg2, CLINT_END_HART_IPI ;\
|
||||
blt reg1, reg2, 41b ;\
|
||||
42: ;\
|
||||
wfi ;\
|
||||
csrr reg2, mip ;\
|
||||
andi reg2, reg2, 0x8 ;\
|
||||
beqz reg2, 42b ;\
|
||||
li reg1, CLINT_CTRL_ADDR ;\
|
||||
csrr reg2, mhartid ;\
|
||||
slli reg2, reg2, 2 ;\
|
||||
add reg2, reg2, reg1 ;\
|
||||
sw zero, 0(reg2) ;\
|
||||
41: ;\
|
||||
lw reg2, 0(reg1) ;\
|
||||
bnez reg2, 41b ;\
|
||||
addi reg1, reg1, 4 ;\
|
||||
li reg2, CLINT_END_HART_IPI ;\
|
||||
blt reg1, reg2, 41b
|
||||
|
||||
#endif
|
|
@ -1,56 +0,0 @@
|
|||
# See LICENSE for license details.
|
||||
|
||||
ifndef _SIFIVE_MK_LIBWRAP
|
||||
_SIFIVE_MK_LIBWRAP := # defined
|
||||
|
||||
LIBWRAP_DIR := $(dir $(lastword $(MAKEFILE_LIST)))
|
||||
LIBWRAP_DIR := $(LIBWRAP_DIR:/=)
|
||||
|
||||
LIBWRAP_SRCS := \
|
||||
stdlib/malloc.c \
|
||||
sys/open.c \
|
||||
sys/lseek.c \
|
||||
sys/read.c \
|
||||
sys/write.c \
|
||||
sys/fstat.c \
|
||||
sys/stat.c \
|
||||
sys/close.c \
|
||||
sys/link.c \
|
||||
sys/unlink.c \
|
||||
sys/execve.c \
|
||||
sys/fork.c \
|
||||
sys/getpid.c \
|
||||
sys/kill.c \
|
||||
sys/wait.c \
|
||||
sys/isatty.c \
|
||||
sys/times.c \
|
||||
sys/sbrk.c \
|
||||
sys/_exit.c \
|
||||
sys/puts.c \
|
||||
misc/write_hex.c
|
||||
|
||||
LIBWRAP_SRCS := $(foreach f,$(LIBWRAP_SRCS),$(LIBWRAP_DIR)/$(f))
|
||||
LIBWRAP_OBJS := $(LIBWRAP_SRCS:.c=.o)
|
||||
|
||||
LIBWRAP_SYMS := malloc free \
|
||||
open lseek read write fstat stat close link unlink \
|
||||
execve fork getpid kill wait \
|
||||
isatty times sbrk _exit puts
|
||||
|
||||
LIBWRAP := libwrap.a
|
||||
|
||||
LINK_DEPS += $(LIBWRAP)
|
||||
|
||||
LDFLAGS += $(foreach s,$(LIBWRAP_SYMS),-Wl,--wrap=$(s))
|
||||
LDFLAGS += $(foreach s,$(LIBWRAP_SYMS),-Wl,--wrap=_$(s))
|
||||
LDFLAGS += -L. -Wl,--start-group -lwrap -lc -Wl,--end-group
|
||||
|
||||
CLEAN_OBJS += $(LIBWRAP_OBJS)
|
||||
|
||||
$(LIBWRAP_OBJS): %.o: %.c $(HEADERS)
|
||||
$(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $<
|
||||
|
||||
$(LIBWRAP): $(LIBWRAP_OBJS)
|
||||
$(AR) rcs $@ $^
|
||||
|
||||
endif # _SIFIVE_MK_LIBWRAP
|
|
@ -1,19 +0,0 @@
|
|||
/* See LICENSE of license details. */
|
||||
|
||||
#include <stdint.h>
|
||||
#include <unistd.h>
|
||||
#include "platform.h"
|
||||
|
||||
void write_hex(int fd, unsigned long int hex)
|
||||
{
|
||||
uint8_t ii;
|
||||
uint8_t jj;
|
||||
char towrite;
|
||||
write(fd , "0x", 2);
|
||||
for (ii = sizeof(unsigned long int) * 2 ; ii > 0; ii--) {
|
||||
jj = ii - 1;
|
||||
uint8_t digit = ((hex & (0xF << (jj*4))) >> (jj*4));
|
||||
towrite = digit < 0xA ? ('0' + digit) : ('A' + (digit - 0xA));
|
||||
write(fd, &towrite, 1);
|
||||
}
|
||||
}
|
|
@ -1,17 +0,0 @@
|
|||
/* See LICENSE for license details. */
|
||||
|
||||
/* These functions are intended for embedded RV32 systems and are
|
||||
obviously incorrect in general. */
|
||||
|
||||
void* __wrap_malloc(unsigned long sz)
|
||||
{
|
||||
extern void* sbrk(long);
|
||||
void* res = sbrk(sz);
|
||||
if ((long)res == -1)
|
||||
return 0;
|
||||
return res;
|
||||
}
|
||||
|
||||
void __wrap_free(void* ptr)
|
||||
{
|
||||
}
|
|
@ -1,17 +0,0 @@
|
|||
/* See LICENSE of license details. */
|
||||
|
||||
#include <unistd.h>
|
||||
#include "platform.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
void __wrap_exit(int code)
|
||||
{
|
||||
const char message[] = "\nProgam has exited with code:";
|
||||
|
||||
write(STDERR_FILENO, message, sizeof(message) - 1);
|
||||
write_hex(STDERR_FILENO, code);
|
||||
write(STDERR_FILENO, "\n", 1);
|
||||
|
||||
for (;;);
|
||||
}
|
||||
weak_under_alias(exit);
|
|
@ -1,11 +0,0 @@
|
|||
/* See LICENSE of license details. */
|
||||
|
||||
#include <errno.h>
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
int __wrap_close(int fd)
|
||||
{
|
||||
return _stub(EBADF);
|
||||
}
|
||||
weak_under_alias(close);
|
|
@ -1,11 +0,0 @@
|
|||
/* See LICENSE of license details. */
|
||||
|
||||
#include <errno.h>
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
int __wrap_execve(const char* name, char* const argv[], char* const env[])
|
||||
{
|
||||
return _stub(ENOMEM);
|
||||
}
|
||||
weak_under_alias(execve);
|
|
@ -1,9 +0,0 @@
|
|||
/* See LICENSE of license details. */
|
||||
|
||||
#include <errno.h>
|
||||
#include "stub.h"
|
||||
|
||||
int fork(void)
|
||||
{
|
||||
return _stub(EAGAIN);
|
||||
}
|
|
@ -1,18 +0,0 @@
|
|||
/* See LICENSE of license details. */
|
||||
|
||||
#include <errno.h>
|
||||
#include <unistd.h>
|
||||
#include <sys/stat.h>
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
int __wrap_fstat(int fd, struct stat* st)
|
||||
{
|
||||
if (isatty(fd)) {
|
||||
st->st_mode = S_IFCHR;
|
||||
return 0;
|
||||
}
|
||||
|
||||
return _stub(EBADF);
|
||||
}
|
||||
weak_under_alias(fstat);
|
|
@ -1,8 +0,0 @@
|
|||
/* See LICENSE of license details. */
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
int __wrap_getpid(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
weak_under_alias(getpid);
|
|
@ -1,13 +0,0 @@
|
|||
/* See LICENSE of license details. */
|
||||
|
||||
#include <unistd.h>
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
int __wrap_isatty(int fd)
|
||||
{
|
||||
if (fd == STDOUT_FILENO || fd == STDERR_FILENO)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
weak_under_alias(isatty);
|
|
@ -1,11 +0,0 @@
|
|||
/* See LICENSE of license details. */
|
||||
|
||||
#include <errno.h>
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
int __wrap_kill(int pid, int sig)
|
||||
{
|
||||
return _stub(EINVAL);
|
||||
}
|
||||
weak_under_alias(kill);
|
|
@ -1,11 +0,0 @@
|
|||
/* See LICENSE of license details. */
|
||||
|
||||
#include <errno.h>
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
int __wrap_link(const char *old_name, const char *new_name)
|
||||
{
|
||||
return _stub(EMLINK);
|
||||
}
|
||||
weak_under_alias(link);
|
|
@ -1,16 +0,0 @@
|
|||
/* See LICENSE of license details. */
|
||||
|
||||
#include <errno.h>
|
||||
#include <unistd.h>
|
||||
#include <sys/types.h>
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
off_t __wrap_lseek(int fd, off_t ptr, int dir)
|
||||
{
|
||||
if (isatty(fd))
|
||||
return 0;
|
||||
|
||||
return _stub(EBADF);
|
||||
}
|
||||
weak_under_alias(lseek);
|
|
@ -1,11 +0,0 @@
|
|||
/* See LICENSE of license details. */
|
||||
|
||||
#include <errno.h>
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
int __wrap_open(const char* name, int flags, int mode)
|
||||
{
|
||||
return _stub(ENOENT);
|
||||
}
|
||||
weak_under_alias(open);
|
|
@ -1,11 +0,0 @@
|
|||
/* See LICENSE of license details. */
|
||||
|
||||
#include <errno.h>
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
int __wrap_openat(int dirfd, const char* name, int flags, int mode)
|
||||
{
|
||||
return _stub(ENOENT);
|
||||
}
|
||||
weak_under_alias(openat);
|
|
@ -1,28 +0,0 @@
|
|||
/* See LICENSE of license details. */
|
||||
|
||||
#include <stdint.h>
|
||||
#include <errno.h>
|
||||
#include <unistd.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#include "platform.h"
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
int __wrap_puts(const char *s)
|
||||
{
|
||||
while (*s != '\0') {
|
||||
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
|
||||
UART0_REG(UART_REG_TXFIFO) = *s;
|
||||
|
||||
if (*s == '\n') {
|
||||
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
|
||||
UART0_REG(UART_REG_TXFIFO) = '\r';
|
||||
}
|
||||
|
||||
++s;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
weak_under_alias(puts);
|
|
@ -1,32 +0,0 @@
|
|||
/* See LICENSE of license details. */
|
||||
|
||||
#include <stdint.h>
|
||||
#include <errno.h>
|
||||
#include <unistd.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#include "platform.h"
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
ssize_t __wrap_read(int fd, void* ptr, size_t len)
|
||||
{
|
||||
uint8_t * current = (uint8_t *)ptr;
|
||||
volatile uint32_t * uart_rx = (uint32_t *)(UART0_CTRL_ADDR + UART_REG_RXFIFO);
|
||||
volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_CTRL_ADDR + UART_REG_RXCTRL + 2);
|
||||
|
||||
ssize_t result = 0;
|
||||
|
||||
if (isatty(fd)) {
|
||||
for (current = (uint8_t *)ptr;
|
||||
(current < ((uint8_t *)ptr) + len) && (*uart_rx_cnt > 0);
|
||||
current ++) {
|
||||
*current = *uart_rx;
|
||||
result++;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
return _stub(EBADF);
|
||||
}
|
||||
weak_under_alias(read);
|
|
@ -1,18 +0,0 @@
|
|||
/* See LICENSE of license details. */
|
||||
|
||||
#include <stddef.h>
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
void *__wrap_sbrk(ptrdiff_t incr)
|
||||
{
|
||||
extern char _end[];
|
||||
extern char _heap_end[];
|
||||
static char *curbrk = _end;
|
||||
|
||||
if ((curbrk + incr < _end) || (curbrk + incr > _heap_end))
|
||||
return NULL - 1;
|
||||
|
||||
curbrk += incr;
|
||||
return curbrk - incr;
|
||||
}
|
||||
weak_under_alias(sbrk);
|
|
@ -1,12 +0,0 @@
|
|||
/* See LICENSE of license details. */
|
||||
|
||||
#include <errno.h>
|
||||
#include <sys/stat.h>
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
int __wrap_stat(const char* file, struct stat* st)
|
||||
{
|
||||
return _stub(EACCES);
|
||||
}
|
||||
weak_under_alias(stat);
|
|
@ -1,10 +0,0 @@
|
|||
/* See LICENSE of license details. */
|
||||
#ifndef _SIFIVE_SYS_STUB_H
|
||||
#define _SIFIVE_SYS_STUB_H
|
||||
|
||||
static inline int _stub(int err)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
#endif /* _SIFIVE_SYS_STUB_H */
|
|
@ -1,12 +0,0 @@
|
|||
/* See LICENSE of license details. */
|
||||
|
||||
#include <errno.h>
|
||||
#include <sys/times.h>
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
clock_t __wrap_times(struct tms* buf)
|
||||
{
|
||||
return _stub(EACCES);
|
||||
}
|
||||
weak_under_alias(times);
|
|
@ -1,11 +0,0 @@
|
|||
/* See LICENSE of license details. */
|
||||
|
||||
#include <errno.h>
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
int __wrap_unlink(const char* name)
|
||||
{
|
||||
return _stub(ENOENT);
|
||||
}
|
||||
weak_under_alias(unlink);
|
|
@ -1,9 +0,0 @@
|
|||
/* See LICENSE of license details. */
|
||||
|
||||
#include <errno.h>
|
||||
#include "stub.h"
|
||||
|
||||
int wait(int* status)
|
||||
{
|
||||
return _stub(ECHILD);
|
||||
}
|
|
@ -1,7 +0,0 @@
|
|||
#ifndef _BSP_LIBWRAP_WEAK_UNDER_ALIAS_H
|
||||
#define _BSP_LIBWRAP_WEAK_UNDER_ALIAS_H
|
||||
|
||||
#define weak_under_alias(name) \
|
||||
extern __typeof (__wrap_##name) __wrap__##name __attribute__ ((weak, alias ("__wrap_"#name)))
|
||||
|
||||
#endif
|
|
@ -1,31 +0,0 @@
|
|||
/* See LICENSE of license details. */
|
||||
|
||||
#include <stdint.h>
|
||||
#include <errno.h>
|
||||
#include <unistd.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#include "platform.h"
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
ssize_t __wrap_write(int fd, const void* ptr, size_t len)
|
||||
{
|
||||
const uint8_t * current = (const char *)ptr;
|
||||
|
||||
if (isatty(fd)) {
|
||||
for (size_t jj = 0; jj < len; jj++) {
|
||||
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
|
||||
UART0_REG(UART_REG_TXFIFO) = current[jj];
|
||||
|
||||
if (current[jj] == '\n') {
|
||||
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
|
||||
UART0_REG(UART_REG_TXFIFO) = '\r';
|
||||
}
|
||||
}
|
||||
return len;
|
||||
}
|
||||
|
||||
return _stub(EBADF);
|
||||
}
|
||||
weak_under_alias(write);
|
Binary file not shown.
|
@ -1,22 +0,0 @@
|
|||
/*
|
||||
* bsp.h
|
||||
*
|
||||
* Created on: 30.07.2018
|
||||
* Author: eyck
|
||||
*/
|
||||
|
||||
#ifndef BSP_H_
|
||||
#define BSP_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include <fe300prci/fe300prci_driver.h>
|
||||
#include <platform.h>
|
||||
#include <encoding.h>
|
||||
extern void trap_entry();
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* BSP_H_ */
|
|
@ -1,123 +0,0 @@
|
|||
/*
|
||||
* delay.c
|
||||
*
|
||||
* Created on: 30.07.2018
|
||||
* Author: eyck
|
||||
*/
|
||||
|
||||
#include "delay.h"
|
||||
|
||||
#define rdmcycle(x) { \
|
||||
uint32_t lo, hi, hi2; \
|
||||
__asm__ __volatile__ ("1:\n\t" \
|
||||
"csrr %0, mcycleh\n\t" \
|
||||
"csrr %1, mcycle\n\t" \
|
||||
"csrr %2, mcycleh\n\t" \
|
||||
"bne %0, %2, 1b\n\t" \
|
||||
: "=r" (hi), "=r" (lo), "=r" (hi2)) ; \
|
||||
*(x) = lo | ((uint64_t) hi << 32); \
|
||||
}
|
||||
|
||||
typedef struct {
|
||||
uint32_t n;
|
||||
uint32_t mult;
|
||||
uint32_t shift;
|
||||
} int_inverse ;
|
||||
|
||||
int_inverse f_cpu_1000_inv;
|
||||
int_inverse f_cpu_1000000_inv;
|
||||
|
||||
uint32_t F_CPU=1000000;
|
||||
|
||||
void calc_inv(uint32_t n, int_inverse * res){
|
||||
uint32_t one = ~0;
|
||||
uint32_t d = one/n;
|
||||
uint32_t r = one%n + 1;
|
||||
if (r >= n) ++d;
|
||||
if (d == 0) --d;
|
||||
uint32_t shift = 0;
|
||||
while ((d & 0x80000000) == 0){
|
||||
d <<= 1;
|
||||
++shift;
|
||||
}
|
||||
res->n = n;
|
||||
res->mult = d;
|
||||
res->shift = shift;
|
||||
}
|
||||
|
||||
uint32_t divide32_using_inverse(uint32_t n, int_inverse *inv){
|
||||
uint32_t d = (uint32_t)(((uint64_t)n * inv->mult) >> 32);
|
||||
d >>= inv->shift;
|
||||
if (n - d*inv->n >= inv->n) ++d;
|
||||
return d;
|
||||
}
|
||||
|
||||
// Almost full-range 64/32 divide.
|
||||
// If divisor-1 has i bits, then the answer is exact for n of up to 64-i bits
|
||||
// e.g. for divisors up to a million, n can have up to 45 bits
|
||||
// On RV32IM with divide32_using_inverse inlines this uses 5 multiplies,
|
||||
// 33 instructions, zero branches, 3 loads, 0 stores.
|
||||
uint64_t divide64_using_inverse(uint64_t n, int_inverse *inv){
|
||||
uint32_t preshift = (31 - inv->shift) & 31;
|
||||
uint64_t d = (uint64_t)divide32_using_inverse(n >> preshift, inv) << preshift;
|
||||
uint32_t r = n - d * inv->n;
|
||||
d += divide32_using_inverse(r, inv);
|
||||
return d;
|
||||
}
|
||||
|
||||
|
||||
uint32_t millis(){
|
||||
uint64_t x;
|
||||
rdmcycle(&x);
|
||||
x = divide64_using_inverse(x, &f_cpu_1000_inv);
|
||||
return((uint32_t) (x & 0xFFFFFFFF));
|
||||
}
|
||||
|
||||
uint32_t micros(void){
|
||||
uint64_t x;
|
||||
rdmcycle(&x);
|
||||
// For Power-of-two MHz F_CPU,
|
||||
// this compiles into a simple shift,
|
||||
// and is faster than the general solution.
|
||||
#if F_CPU==16000000
|
||||
x = x / (F_CPU / 1000000);
|
||||
#else
|
||||
#if F_CPU==256000000
|
||||
x = x / (F_CPU / 1000000);
|
||||
#else
|
||||
x = divide64_using_inverse(x, &f_cpu_1000000_inv);
|
||||
#endif
|
||||
#endif
|
||||
return((uint32_t) (x & 0xFFFFFFFF));
|
||||
}
|
||||
|
||||
|
||||
void delayMS(uint32_t dwMs){
|
||||
uint64_t current, later;
|
||||
rdmcycle(¤t);
|
||||
later = current + dwMs * (F_CPU/1000);
|
||||
if (later > current){ // usual case
|
||||
while (later > current)
|
||||
rdmcycle(¤t);
|
||||
} else { // wrap. Though this is unlikely to be hit w/ 64-bit mcycle
|
||||
while (later < current)
|
||||
rdmcycle(¤t);
|
||||
while (current < later)
|
||||
rdmcycle(¤t);
|
||||
}
|
||||
}
|
||||
|
||||
void delayUS(uint32_t dwUs){
|
||||
uint64_t current, later;
|
||||
rdmcycle(¤t);
|
||||
later = current + dwUs * (F_CPU/1000000);
|
||||
if (later > current){ // usual case
|
||||
while (later > current)
|
||||
rdmcycle(¤t);
|
||||
} else {// wrap. Though this is unlikely to be hit w/ 64-bit mcycle
|
||||
while (later < current)
|
||||
rdmcycle(¤t);
|
||||
while (current < later)
|
||||
rdmcycle(¤t);
|
||||
}
|
||||
}
|
|
@ -1,25 +0,0 @@
|
|||
/*
|
||||
* delay.h
|
||||
*
|
||||
* Created on: 30.07.2018
|
||||
* Author: eyck
|
||||
*/
|
||||
|
||||
#ifndef DELAY_H_
|
||||
#define DELAY_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
extern uint32_t F_CPU;
|
||||
|
||||
void delayMS(uint32_t dwMs);
|
||||
void delayUS(uint32_t dwUs);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DELAY_H_ */
|
|
@ -1,62 +0,0 @@
|
|||
|
||||
#ifndef _DMA_REGS_H_
|
||||
#define _DMA_REGS_H_
|
||||
|
||||
#include <util/bit_field.h>
|
||||
#include <cstdint>
|
||||
|
||||
#define DMA_REG_START 0x00
|
||||
#define DMA_REG_CLEAR_INTERRUPT 0x0C
|
||||
#define DMA_REG_FPGA_ADDRESS 0x10
|
||||
#define DMA_REG_SC_ADDRESS 0x20
|
||||
#define DMA_REG_OPERATION 0x30 // 0 = READ, 1 = WRITE, 2 = ALLOC, 3 = FREE
|
||||
#define DMA_REG_BYTES 0x40
|
||||
#define DMA_REG_ALLOC_ADDRESS 0x50
|
||||
|
||||
template<uint32_t BASE_ADDR>
|
||||
class dma_regs {
|
||||
public:
|
||||
// storage declarations
|
||||
// BEGIN_BF_DECL(start_t, uint32_t);
|
||||
// BF_FIELD(start, 0, 1);
|
||||
// END_BF_DECL() r_start;
|
||||
uint32_t r_start;
|
||||
|
||||
uint32_t r_address;
|
||||
|
||||
uint32_t r_operation;
|
||||
|
||||
uint32_t r_bytes;
|
||||
|
||||
static inline uint32_t& start_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+DMA_REG_START);
|
||||
}
|
||||
|
||||
static inline uint32_t& clear_interrupt_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+DMA_REG_CLEAR_INTERRUPT);
|
||||
}
|
||||
|
||||
static inline uint32_t & fpga_address_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+DMA_REG_FPGA_ADDRESS);
|
||||
}
|
||||
|
||||
static inline uint32_t & sc_address_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+DMA_REG_SC_ADDRESS);
|
||||
}
|
||||
|
||||
static inline uint32_t & operation_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+DMA_REG_OPERATION);
|
||||
}
|
||||
|
||||
static inline uint32_t & bytes_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+DMA_REG_BYTES);
|
||||
}
|
||||
|
||||
static inline uint32_t & alloc_address_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+DMA_REG_ALLOC_ADDRESS);
|
||||
}
|
||||
|
||||
|
||||
};
|
||||
|
||||
#endif // _SPN_REGS_H_
|
|
@ -1,96 +0,0 @@
|
|||
#ifndef SRC_INIT_H_
|
||||
#define SRC_INIT_H_
|
||||
|
||||
#include <cstdio>
|
||||
#include <array>
|
||||
|
||||
#include "delay.h"
|
||||
#include "bsp.h"
|
||||
#include "plic/plic_driver.h"
|
||||
|
||||
typedef void (*function_ptr_t) (void);
|
||||
//! Instance data for the PLIC.
|
||||
plic_instance_t g_plic;
|
||||
std::array<function_ptr_t,PLIC_NUM_INTERRUPTS> g_ext_interrupt_handlers;
|
||||
bool hw_interrupt{true};
|
||||
bool dma_interrupt{true};
|
||||
|
||||
|
||||
/*! \brief external interrupt handler
|
||||
*
|
||||
* routes the peripheral interrupts to the the respective handler
|
||||
*
|
||||
*/
|
||||
extern "C" void handle_m_ext_interrupt() {
|
||||
plic_source int_num = PLIC_claim_interrupt(&g_plic);
|
||||
if ((int_num >=1 ) && (int_num < PLIC_NUM_INTERRUPTS))
|
||||
g_ext_interrupt_handlers[int_num]();
|
||||
else
|
||||
exit(1 + (uintptr_t) int_num);
|
||||
PLIC_complete_interrupt(&g_plic, int_num);
|
||||
}
|
||||
/*! \brief dummy interrupt handler
|
||||
*
|
||||
*/
|
||||
void no_interrupt_handler (void) {};
|
||||
/*! \brief configure the per-interrupt handler
|
||||
*
|
||||
*/
|
||||
void configure_irq(size_t irq_num, function_ptr_t handler, unsigned char prio=1) {
|
||||
g_ext_interrupt_handlers[irq_num] = handler;
|
||||
// Priority must be set > 0 to trigger the interrupt.
|
||||
PLIC_set_priority(&g_plic, irq_num, prio);
|
||||
// Have to enable the interrupt both at the GPIO level, and at the PLIC level.
|
||||
PLIC_enable_interrupt(&g_plic, irq_num);
|
||||
}
|
||||
|
||||
void wait_for_spn_interrupt() {
|
||||
// wait until HW is done
|
||||
if(hw_interrupt) {
|
||||
do{
|
||||
asm("wfi");
|
||||
asm("nop");
|
||||
}while(hw_interrupt);
|
||||
}
|
||||
hw_interrupt=true;
|
||||
}
|
||||
|
||||
void wait_for_dma_interrupt() {
|
||||
// wait until HW is done
|
||||
if(dma_interrupt) {
|
||||
do{
|
||||
asm("wfi");
|
||||
asm("nop");
|
||||
}while(dma_interrupt);
|
||||
}
|
||||
dma_interrupt=true;
|
||||
}
|
||||
|
||||
/*!\brief initializes platform
|
||||
*
|
||||
*/
|
||||
void platform_init(){
|
||||
// UART init section TODO: clarify how to get the functions from init.c?
|
||||
GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
|
||||
GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
|
||||
UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
|
||||
|
||||
F_CPU=PRCI_measure_mcycle_freq(20, RTC_FREQ);
|
||||
printf("core freq at %d Hz\n", F_CPU);
|
||||
// initialie interupt & trap handling
|
||||
write_csr(mtvec, &trap_entry);
|
||||
|
||||
PLIC_init(&g_plic, PLIC_CTRL_ADDR, PLIC_NUM_INTERRUPTS, PLIC_NUM_PRIORITIES, 0);
|
||||
// Disable the machine & timer interrupts until setup is done.
|
||||
clear_csr(mie, MIP_MEIP);
|
||||
clear_csr(mie, MIP_MTIP);
|
||||
for (auto& h:g_ext_interrupt_handlers) h=no_interrupt_handler;
|
||||
// Enable interrupts in general.
|
||||
set_csr(mstatus, MSTATUS_MIE);
|
||||
// Enable the Machine-External bit in MIE
|
||||
set_csr(mie, MIP_MEIP);
|
||||
|
||||
//hw_interrupt = false;
|
||||
}
|
||||
|
||||
#endif /* SRC_INIT_H_ */
|
|
@ -1,89 +0,0 @@
|
|||
/*
|
||||
* gpio.h
|
||||
*
|
||||
* Created on: 29.07.2018
|
||||
* Author: eyck
|
||||
*/
|
||||
|
||||
#ifndef GPIO_H_
|
||||
#define GPIO_H_
|
||||
|
||||
#include <sifive/devices/gpio.h>
|
||||
#include <cstdint>
|
||||
|
||||
template<uint32_t BASE_ADDR>
|
||||
class gpio_regs {
|
||||
public:
|
||||
static inline uint32_t& value_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_INPUT_VAL);
|
||||
}
|
||||
|
||||
static inline uint32_t& input_en_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_INPUT_EN);
|
||||
}
|
||||
|
||||
static inline uint32_t& output_en_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_OUTPUT_EN);
|
||||
}
|
||||
|
||||
static inline uint32_t& port_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_OUTPUT_VAL);
|
||||
}
|
||||
|
||||
static inline uint32_t& pue_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_PULLUP_EN);
|
||||
}
|
||||
|
||||
static inline uint32_t& ds_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_DRIVE);
|
||||
}
|
||||
|
||||
static inline uint32_t& rise_ie_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_RISE_IE);
|
||||
}
|
||||
|
||||
static inline uint32_t& rise_ip_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_RISE_IP);
|
||||
}
|
||||
|
||||
static inline uint32_t& fall_ie_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_FALL_IE);
|
||||
}
|
||||
|
||||
static inline uint32_t& fall_ip_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_FALL_IP);
|
||||
}
|
||||
|
||||
static inline uint32_t& high_ie_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_HIGH_IE);
|
||||
}
|
||||
|
||||
static inline uint32_t& high_ip_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_HIGH_IP);
|
||||
}
|
||||
|
||||
static inline uint32_t& low_ie_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_LOW_IE);
|
||||
}
|
||||
|
||||
static inline uint32_t& low_ip_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_LOW_IP);
|
||||
}
|
||||
|
||||
static inline uint32_t& iof_en_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_IOF_EN);
|
||||
}
|
||||
|
||||
static inline uint32_t& iof_sel_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_IOF_SEL);
|
||||
}
|
||||
|
||||
static inline uint32_t& out_xor_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_OUTPUT_XOR);
|
||||
}
|
||||
|
||||
};
|
||||
|
||||
|
||||
|
||||
#endif /* GPIO_H_ */
|
|
@ -1,122 +0,0 @@
|
|||
/*
|
||||
* pwm.h
|
||||
*
|
||||
* Created on: 29.07.2018
|
||||
* Author: eyck
|
||||
*/
|
||||
|
||||
#ifndef PWM_H_
|
||||
#define PWM_H_
|
||||
|
||||
#include <sifive/devices/pwm.h>
|
||||
#include "util/bit_field.h"
|
||||
#include <limits>
|
||||
#include <cstdint>
|
||||
|
||||
template<uint32_t BASE_ADDR>
|
||||
class pwm_regs {
|
||||
public:
|
||||
BEGIN_BF_DECL(pwmcfg_t, uint32_t);
|
||||
BF_FIELD(scale, 0, 4);
|
||||
BF_FIELD(sticky, 8, 1);
|
||||
BF_FIELD(zerocmp, 9, 1);
|
||||
BF_FIELD(deglitch, 10, 1);
|
||||
BF_FIELD(enalways, 12, 1);
|
||||
BF_FIELD(enoneshot, 13, 1);
|
||||
BF_FIELD(cmp0center, 16, 1);
|
||||
BF_FIELD(cmp1center, 17, 1);
|
||||
BF_FIELD(cmp2center, 18, 1);
|
||||
BF_FIELD(cmp3center, 19, 1);
|
||||
BF_FIELD(cmp0gang, 24, 1);
|
||||
BF_FIELD(cmp1gang, 25, 1);
|
||||
BF_FIELD(cmp2gang, 26, 1);
|
||||
BF_FIELD(cmp3gang, 27, 1);
|
||||
BF_FIELD(cmp0ip, 28, 1);
|
||||
BF_FIELD(cmp1ip, 29, 1);
|
||||
BF_FIELD(cmp2ip, 30, 1);
|
||||
BF_FIELD(cmp3ip, 31, 1);
|
||||
END_BF_DECL();
|
||||
|
||||
BEGIN_BF_DECL(pwms_t, uint32_t);
|
||||
BF_FIELD(s, 0, 16);
|
||||
END_BF_DECL() r_pwms;
|
||||
|
||||
BEGIN_BF_DECL(pwmcmp0_t, uint32_t);
|
||||
BF_FIELD(cmp0, 0, 16);
|
||||
END_BF_DECL() r_pwmcmp0;
|
||||
|
||||
BEGIN_BF_DECL(pwmcmp1_t, uint32_t);
|
||||
BF_FIELD(cmp0, 0, 16);
|
||||
END_BF_DECL() r_pwmcmp1;
|
||||
|
||||
BEGIN_BF_DECL(pwmcmp2_t, uint32_t);
|
||||
BF_FIELD(cmp0, 0, 16);
|
||||
END_BF_DECL() r_pwmcmp2;
|
||||
|
||||
BEGIN_BF_DECL(pwmcmp3_t, uint32_t);
|
||||
BF_FIELD(cmp0, 0, 16);
|
||||
END_BF_DECL() r_pwmcmp3;
|
||||
|
||||
static inline pwmcfg_t& cfg_reg(){
|
||||
return *reinterpret_cast<pwmcfg_t*>(BASE_ADDR+PWM_CFG);
|
||||
}
|
||||
|
||||
static inline uint32_t& count_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+PWM_COUNT);
|
||||
}
|
||||
|
||||
static inline pwms_t& s_reg(){
|
||||
return *reinterpret_cast<pwms_t*>(BASE_ADDR+PWM_S);
|
||||
}
|
||||
|
||||
static inline pwmcmp0_t& cmp0_reg(){
|
||||
return *reinterpret_cast<pwmcmp0_t*>(BASE_ADDR+PWM_CMP0);
|
||||
}
|
||||
|
||||
static inline pwmcmp1_t& cmp1_reg(){
|
||||
return *reinterpret_cast<pwmcmp1_t*>(BASE_ADDR+PWM_CMP1);
|
||||
}
|
||||
|
||||
static inline pwmcmp2_t& cmp2_reg(){
|
||||
return *reinterpret_cast<pwmcmp2_t*>(BASE_ADDR+PWM_CMP2);
|
||||
}
|
||||
|
||||
static inline pwmcmp3_t& cmp3_reg(){
|
||||
return *reinterpret_cast<pwmcmp3_t*>(BASE_ADDR+PWM_CMP3);
|
||||
}
|
||||
|
||||
static inline bool oneshot_delay(long delay_us){
|
||||
auto scaling_factor=0;
|
||||
while(delay_us/(1<<scaling_factor) > std::numeric_limits<unsigned short>::max()){
|
||||
scaling_factor++;
|
||||
}
|
||||
cfg_reg()=0;
|
||||
count_reg()=0;
|
||||
cfg_reg().scale=4+scaling_factor; // divide by 16 so we get 1us per pwm clock
|
||||
cmp0_reg().cmp0 = delay_us/(1<<scaling_factor);
|
||||
pwm_active=true;
|
||||
cfg_reg().enoneshot=true;
|
||||
do{
|
||||
asm("wfi");
|
||||
asm("nop");
|
||||
}while(pwm_active);
|
||||
return true;
|
||||
}
|
||||
|
||||
static void pwm_interrupt_handler(){
|
||||
cfg_reg().cmp0ip=false;
|
||||
pwm_active=false;
|
||||
}
|
||||
|
||||
inline
|
||||
static bool is_active(){ return pwm_active; }
|
||||
|
||||
inline
|
||||
static void set_active() {pwm_active=true;}
|
||||
|
||||
private:
|
||||
static volatile bool pwm_active;
|
||||
};
|
||||
|
||||
|
||||
#endif /* PWM_H_ */
|
|
@ -1,200 +0,0 @@
|
|||
/*
|
||||
* spi.h
|
||||
*
|
||||
* Created on: 29.07.2018
|
||||
* Author: eyck
|
||||
*/
|
||||
|
||||
#ifndef SPI_H_
|
||||
#define SPI_H_
|
||||
|
||||
#include <sifive/devices/spi.h>
|
||||
#include "util/bit_field.h"
|
||||
#include <array>
|
||||
#include <cstdint>
|
||||
|
||||
template<uint32_t BASE_ADDR>
|
||||
class spi_regs {
|
||||
public:
|
||||
// storage declarations
|
||||
BEGIN_BF_DECL(sckdiv_t, uint32_t);
|
||||
BF_FIELD(div, 0, 12);
|
||||
END_BF_DECL();
|
||||
|
||||
BEGIN_BF_DECL(sckmode_t, uint32_t);
|
||||
BF_FIELD(pha, 0, 1);
|
||||
BF_FIELD(pol, 1, 1);
|
||||
END_BF_DECL();
|
||||
|
||||
uint32_t r_csid;
|
||||
|
||||
uint32_t r_csdef;
|
||||
|
||||
BEGIN_BF_DECL(csmode_t, uint32_t);
|
||||
BF_FIELD(mode, 0, 2);
|
||||
END_BF_DECL();
|
||||
|
||||
BEGIN_BF_DECL(delay0_t, uint32_t);
|
||||
BF_FIELD(cssck, 0, 8);
|
||||
BF_FIELD(sckcs, 16, 8);
|
||||
END_BF_DECL();
|
||||
|
||||
BEGIN_BF_DECL(delay1_t, uint32_t);
|
||||
BF_FIELD(intercs, 0, 16);
|
||||
BF_FIELD(interxfr, 16, 8);
|
||||
END_BF_DECL();
|
||||
|
||||
BEGIN_BF_DECL(fmt_t, uint32_t);
|
||||
BF_FIELD(proto, 0, 2);
|
||||
BF_FIELD(endian, 2, 1);
|
||||
BF_FIELD(dir, 3, 1);
|
||||
BF_FIELD(len, 16, 4);
|
||||
END_BF_DECL();
|
||||
|
||||
BEGIN_BF_DECL(txdata_t, uint32_t);
|
||||
BF_FIELD(data, 0, 8);
|
||||
BF_FIELD(full, 31, 1);
|
||||
END_BF_DECL() r_txdata;
|
||||
|
||||
BEGIN_BF_DECL(rxdata_t, uint32_t);
|
||||
BF_FIELD(data, 0, 8);
|
||||
BF_FIELD(empty, 31, 1);
|
||||
END_BF_DECL();
|
||||
|
||||
BEGIN_BF_DECL(txmark_t, uint32_t);
|
||||
BF_FIELD(txmark, 0, 3);
|
||||
END_BF_DECL();
|
||||
|
||||
BEGIN_BF_DECL(rxmark_t, uint32_t);
|
||||
BF_FIELD(rxmark, 0, 3);
|
||||
END_BF_DECL();
|
||||
|
||||
BEGIN_BF_DECL(fctrl_t, uint32_t);
|
||||
BF_FIELD(en, 0, 1);
|
||||
END_BF_DECL();
|
||||
|
||||
BEGIN_BF_DECL(ffmt_t, uint32_t);
|
||||
BF_FIELD(cmd_en, 0, 1);
|
||||
BF_FIELD(addr_len, 1, 2);
|
||||
BF_FIELD(pad_cnt, 3, 4);
|
||||
BF_FIELD(cmd_proto, 7, 2);
|
||||
BF_FIELD(addr_proto, 9, 2);
|
||||
BF_FIELD(data_proto, 11, 2);
|
||||
BF_FIELD(cmd_code, 16, 8);
|
||||
BF_FIELD(pad_code, 24, 8);
|
||||
END_BF_DECL();
|
||||
|
||||
BEGIN_BF_DECL(ie_t, uint32_t);
|
||||
BF_FIELD(txwm, 0, 1);
|
||||
BF_FIELD(rxwm, 1, 1);
|
||||
END_BF_DECL();
|
||||
|
||||
BEGIN_BF_DECL(ip_t, uint32_t);
|
||||
BF_FIELD(txwm, 0, 1);
|
||||
BF_FIELD(rxwm, 1, 1);
|
||||
END_BF_DECL();
|
||||
|
||||
static inline sckdiv_t& sckdiv_reg(){
|
||||
return *reinterpret_cast<sckdiv_t*>(BASE_ADDR+SPI_REG_SCKDIV);
|
||||
}
|
||||
|
||||
static inline sckmode_t& sckmode_reg(){
|
||||
return *reinterpret_cast<sckmode_t*>(BASE_ADDR+SPI_REG_SCKMODE);
|
||||
}
|
||||
|
||||
static inline uint32_t& csid_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPI_REG_CSID);
|
||||
}
|
||||
|
||||
static inline uint32_t& csdef_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPI_REG_CSDEF);
|
||||
}
|
||||
|
||||
static inline csmode_t& csmode_reg(){
|
||||
return *reinterpret_cast<csmode_t*>(BASE_ADDR+SPI_REG_CSMODE);
|
||||
}
|
||||
|
||||
static inline delay0_t& dcssck_reg(){
|
||||
return *reinterpret_cast<delay0_t*>(BASE_ADDR+SPI_REG_DCSSCK);
|
||||
}
|
||||
|
||||
static inline uint32_t& dsckcs_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPI_REG_DSCKCS);
|
||||
}
|
||||
|
||||
static inline delay1_t& dintercs_reg(){
|
||||
return *reinterpret_cast<delay1_t*>(BASE_ADDR+SPI_REG_DINTERCS);
|
||||
}
|
||||
|
||||
static inline uint32_t& dinterxfr_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPI_REG_DINTERXFR);
|
||||
}
|
||||
|
||||
static inline fmt_t& fmt_reg(){
|
||||
return *reinterpret_cast<fmt_t*>(BASE_ADDR+SPI_REG_FMT);
|
||||
}
|
||||
|
||||
static inline txdata_t& txfifo_reg(){
|
||||
return *reinterpret_cast<txdata_t*>(BASE_ADDR+SPI_REG_TXFIFO);
|
||||
}
|
||||
|
||||
static inline rxdata_t& rxfifo_reg(){
|
||||
return *reinterpret_cast<rxdata_t*>(BASE_ADDR+SPI_REG_RXFIFO);
|
||||
}
|
||||
|
||||
static inline txmark_t& txctrl_reg(){
|
||||
return *reinterpret_cast<txmark_t*>(BASE_ADDR+SPI_REG_TXCTRL);
|
||||
}
|
||||
|
||||
static inline rxmark_t& rxctrl_reg(){
|
||||
return *reinterpret_cast<rxmark_t*>(BASE_ADDR+SPI_REG_RXCTRL);
|
||||
}
|
||||
|
||||
static inline fctrl_t& fctrl_reg(){
|
||||
return *reinterpret_cast<fctrl_t*>(BASE_ADDR+SPI_REG_FCTRL);
|
||||
}
|
||||
|
||||
static inline ffmt_t& ffmt_reg(){
|
||||
return *reinterpret_cast<ffmt_t*>(BASE_ADDR+SPI_REG_FFMT);
|
||||
}
|
||||
|
||||
static inline ie_t& ie_reg(){
|
||||
return *reinterpret_cast<ie_t*>(BASE_ADDR+SPI_REG_IE);
|
||||
}
|
||||
|
||||
static inline ip_t& ip_reg(){
|
||||
return *reinterpret_cast<ip_t*>(BASE_ADDR+SPI_REG_IP);
|
||||
}
|
||||
|
||||
template<size_t SIZE>
|
||||
static bool transfer(std::array<uint8_t, SIZE>& bytes){
|
||||
csmode_reg().mode=2; // HOLD mode
|
||||
rxctrl_reg().rxmark=bytes.size()-1; // trigger irq if more than 2 bytes are received;
|
||||
ie_reg().rxwm=1;
|
||||
// write data bytes
|
||||
for(size_t i=0; i<bytes.size(); ++i)
|
||||
txfifo_reg()=bytes[i];
|
||||
// wait until SPI is done
|
||||
spi_active=true;
|
||||
do{
|
||||
asm("wfi");
|
||||
asm("nop");
|
||||
}while(spi_active);
|
||||
// deactivate SPI
|
||||
csmode_reg().mode=0; // AUTO mode, deactivates CS
|
||||
// fetch results
|
||||
for(size_t i=0; i<bytes.size(); ++i) bytes[i]=rxfifo_reg();
|
||||
return true;
|
||||
}
|
||||
|
||||
static void spi_rx_interrupt_handler(){
|
||||
ip_reg().rxwm=0;
|
||||
ie_reg().rxwm=0;
|
||||
spi_active=false;
|
||||
}
|
||||
|
||||
private:
|
||||
static volatile bool spi_active;
|
||||
};
|
||||
|
||||
#endif /* SPI_H_ */
|
|
@ -1,83 +0,0 @@
|
|||
/*
|
||||
* spi.h
|
||||
*
|
||||
* Created on: 29.07.2018
|
||||
* Author: eyck
|
||||
*/
|
||||
|
||||
#ifndef UART_H_
|
||||
#define UART_H_
|
||||
|
||||
#include <sifive/devices/uart.h>
|
||||
#include "util/bit_field.h"
|
||||
#include <cstdint>
|
||||
|
||||
template<uint32_t BASE_ADDR>
|
||||
class uart_regs {
|
||||
public:
|
||||
BEGIN_BF_DECL(txdata_t, uint32_t);
|
||||
BF_FIELD(data, 0, 8);
|
||||
BF_FIELD(full, 31, 1);
|
||||
END_BF_DECL() ;
|
||||
|
||||
BEGIN_BF_DECL(rxdata_t, uint32_t);
|
||||
BF_FIELD(data, 0, 8);
|
||||
BF_FIELD(empty, 31, 1);
|
||||
END_BF_DECL();
|
||||
|
||||
BEGIN_BF_DECL(txctrl_t, uint32_t);
|
||||
BF_FIELD(txen, 0, 1);
|
||||
BF_FIELD(nstop, 1, 1);
|
||||
BF_FIELD(txcnt, 16, 3);
|
||||
END_BF_DECL();
|
||||
|
||||
BEGIN_BF_DECL(rxctrl_t, uint32_t);
|
||||
BF_FIELD(rxen, 0, 1);
|
||||
BF_FIELD(rxcnt, 16, 3);
|
||||
END_BF_DECL();
|
||||
|
||||
BEGIN_BF_DECL(ie_t, uint32_t);
|
||||
BF_FIELD(txwm, 0, 1);
|
||||
BF_FIELD(rxwm, 1, 1);
|
||||
END_BF_DECL();
|
||||
|
||||
BEGIN_BF_DECL(ip_t, uint32_t);
|
||||
BF_FIELD(txwm, 0, 1);
|
||||
BF_FIELD(rxwm, 1, 1);
|
||||
END_BF_DECL();
|
||||
|
||||
BEGIN_BF_DECL(div_t, uint32_t);
|
||||
BF_FIELD(div, 0, 16);
|
||||
END_BF_DECL();
|
||||
|
||||
static inline txdata_t& txdata_reg(){
|
||||
return *reinterpret_cast<txdata_t*>(BASE_ADDR+UART_REG_TXFIFO);
|
||||
}
|
||||
|
||||
static inline rxdata_t& rxdata_reg(){
|
||||
return *reinterpret_cast<rxdata_t*>(BASE_ADDR+UART_REG_RXFIFO);
|
||||
}
|
||||
|
||||
static inline txctrl_t& txctrl_reg(){
|
||||
return *reinterpret_cast<txctrl_t*>(BASE_ADDR+UART_REG_TXCTRL);
|
||||
}
|
||||
|
||||
static inline rxctrl_t& rxctrl_reg(){
|
||||
return *reinterpret_cast<rxctrl_t*>(BASE_ADDR+UART_REG_RXCTRL);
|
||||
}
|
||||
|
||||
static inline ie_t& ie_reg(){
|
||||
return *reinterpret_cast<ie_t*>(BASE_ADDR+UART_REG_IE);
|
||||
}
|
||||
|
||||
static inline ip_t& ip_reg(){
|
||||
return *reinterpret_cast<ip_t*>(BASE_ADDR+UART_REG_IP);
|
||||
}
|
||||
|
||||
static inline div_t& div_reg(){
|
||||
return *reinterpret_cast<div_t*>(BASE_ADDR+UART_REG_DIV);
|
||||
}
|
||||
|
||||
};
|
||||
|
||||
#endif /* SPI_H_ */
|
|
@ -1,157 +0,0 @@
|
|||
#include "raven_spn.h"
|
||||
#include "spn_regs.h"
|
||||
#include "dma_regs.h"
|
||||
#include "init.h"
|
||||
#include "spn_checker_regs.h"
|
||||
|
||||
using spn = spn_regs<0x90000000>;
|
||||
using dma = dma_regs<0xB0000000>;
|
||||
using spn_checker = spn_checker_regs<0x10040000>;
|
||||
|
||||
void run_xspn(int in_addr, int out_addr, int num_samples, int in_beats, int out_beats) {
|
||||
spn::mode_reg() = 0;
|
||||
spn::input_length_reg() = num_samples; // each sample consists of 5 uint8 values
|
||||
spn::input_addr_reg() = in_addr;
|
||||
spn::output_addr_reg() = out_addr;
|
||||
spn::num_of_in_beats_reg() = in_beats; // Number of AXI4 burst beats needed to load all input data
|
||||
spn::num_of_out_beats_reg() = out_beats; // Number of AXI4 burst beats needed to store all result data
|
||||
printf("Starting XSPN\n");
|
||||
spn::start_reg() = 1;
|
||||
}
|
||||
|
||||
void fpga_dma(int direction, int fpga_address, int sc_address, int num_bytes) {
|
||||
dma::operation_reg() = direction;
|
||||
dma::fpga_address_reg() = fpga_address;
|
||||
dma::sc_address_reg() = sc_address;
|
||||
dma::bytes_reg() = num_bytes;
|
||||
dma::start_reg() = 1;
|
||||
wait_for_dma_interrupt();
|
||||
dma::clear_interrupt_reg() = 1;
|
||||
}
|
||||
|
||||
int fpga_alloc(int num_bytes) {
|
||||
dma::operation_reg() = 2;
|
||||
dma::bytes_reg() = num_bytes;
|
||||
dma::start_reg() = 1;
|
||||
wait_for_dma_interrupt();
|
||||
dma::clear_interrupt_reg() = 1;
|
||||
return dma::alloc_address_reg();
|
||||
}
|
||||
|
||||
void fpga_free(int address) {
|
||||
dma::operation_reg() = 3;
|
||||
dma::fpga_address_reg() = address;
|
||||
dma::start_reg() = 1;
|
||||
wait_for_dma_interrupt();
|
||||
dma::clear_interrupt_reg() = 1;
|
||||
}
|
||||
|
||||
static void spn_interrupt_handler(){
|
||||
printf("spn_interrupt_handler\n");
|
||||
hw_interrupt = false;
|
||||
}
|
||||
|
||||
static void dma_interrupt_handler(){
|
||||
printf("dma_interrupt_handler\n");
|
||||
dma_interrupt = false;
|
||||
}
|
||||
|
||||
/*! \brief main function
|
||||
*
|
||||
*/
|
||||
int main() {
|
||||
|
||||
|
||||
platform_init();
|
||||
configure_irq(2, spn_interrupt_handler);
|
||||
configure_irq(22, dma_interrupt_handler);
|
||||
|
||||
|
||||
|
||||
uint32_t batch_size = spn_checker::batch_size_reg();
|
||||
uint32_t iterations = spn_checker::num_iterations_reg();
|
||||
|
||||
printf("BATCH SIZE: %d\n", batch_size);
|
||||
printf("ITERATIONS: %d\n", iterations);
|
||||
|
||||
|
||||
|
||||
int in_addr = 0x30000000; // place input samples in the SPI memory
|
||||
int out_addr = 0x3C000000;
|
||||
int out_addr2 = 0x3E000000;
|
||||
|
||||
|
||||
|
||||
spn::mode_reg() = 1;
|
||||
spn::start_reg() = 1;
|
||||
wait_for_spn_interrupt();
|
||||
spn::interrupt_reg() = 1;
|
||||
uint32_t readout = spn::readout_reg();
|
||||
printf("READOUT HW:0x%x\n", readout);
|
||||
|
||||
uint32_t axi_bytes = readout;
|
||||
axi_bytes = axi_bytes & 0xff;
|
||||
axi_bytes = 1 << axi_bytes;
|
||||
|
||||
printf("AXI Bytes: %d\n", axi_bytes);
|
||||
|
||||
uint32_t sample_bytes = readout;
|
||||
sample_bytes = sample_bytes >> 16;
|
||||
sample_bytes = sample_bytes / 8;
|
||||
|
||||
printf("Sample Bytes: %d\n", sample_bytes);
|
||||
|
||||
uint32_t result_bytes = 8;
|
||||
|
||||
printf("Result Bytes: %d\n", result_bytes);
|
||||
|
||||
uint32_t in_bytes = batch_size * sample_bytes;
|
||||
uint32_t out_bytes = batch_size * result_bytes;
|
||||
|
||||
uint32_t total_in = in_bytes * iterations;
|
||||
|
||||
if (total_in > (out_addr - in_addr)) {
|
||||
printf("ERROR: input data requires %d bytes, only %d bytes available\n", total_in, out_addr - in_addr);
|
||||
return 1;
|
||||
}
|
||||
if (out_bytes > (out_addr2 - out_addr)) {
|
||||
printf("ERROR: output data requires %d bytes, only %d bytes available\n", out_bytes, out_addr2 - out_addr);
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
uint32_t in_beats = in_bytes / axi_bytes;
|
||||
if (in_beats * axi_bytes < batch_size * sample_bytes) in_beats++;
|
||||
uint32_t out_beats = out_bytes / axi_bytes;
|
||||
if (out_beats * axi_bytes < batch_size * result_bytes) out_beats++;
|
||||
|
||||
uint32_t current_in_addr = in_addr;
|
||||
int fpga_address_in = fpga_alloc(batch_size * sample_bytes + 64);
|
||||
int fpga_address_out = fpga_alloc(batch_size * result_bytes + 64);
|
||||
|
||||
// inject SPN input data
|
||||
spn_checker::input_addr_reg() = current_in_addr;
|
||||
spn_checker::num_input_samples_reg() = sample_bytes * batch_size * iterations;
|
||||
spn_checker::start_data_trans_reg() = 1;
|
||||
spn_checker::output_addr_reg() = out_addr;
|
||||
|
||||
//run_xspn(in_addr, out_addr);
|
||||
for (int k = 0; k < iterations*batch_size; k+=batch_size) {
|
||||
fpga_dma(1, fpga_address_in, current_in_addr, batch_size * sample_bytes);
|
||||
run_xspn(fpga_address_in, fpga_address_out, batch_size, in_beats, out_beats);
|
||||
wait_for_spn_interrupt();
|
||||
spn::interrupt_reg() = 1;
|
||||
printf("XSPN finished\n");
|
||||
fpga_dma(0, fpga_address_out, out_addr, batch_size * result_bytes);
|
||||
spn_checker::offset_reg() = k;
|
||||
spn_checker::length_reg() = batch_size;
|
||||
spn_checker::start_result_check_reg() = 1;
|
||||
|
||||
current_in_addr += batch_size * sample_bytes; // 5 bytes in each sample
|
||||
}
|
||||
|
||||
fpga_free(fpga_address_in);
|
||||
fpga_free(fpga_address_out);
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -1,6 +0,0 @@
|
|||
#ifndef RAVEN_SPN_H_
|
||||
#define RAVEN_SPN_H_
|
||||
|
||||
extern "C" void handle_m_ext_interrupt();
|
||||
|
||||
#endif /* RAVEN_SPN_H_ */
|
|
@ -1,125 +0,0 @@
|
|||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (C) 2017, MINRES Technologies GmbH
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
//
|
||||
// 1. Redistributions of source code must retain the above copyright notice,
|
||||
// this list of conditions and the following disclaimer.
|
||||
//
|
||||
// 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
// this list of conditions and the following disclaimer in the documentation
|
||||
// and/or other materials provided with the distribution.
|
||||
//
|
||||
// 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
// may be used to endorse or promote products derived from this software
|
||||
// without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
// POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Created on: Thu Oct 01 15:45:55 CEST 2020
|
||||
// * spn_regs.h Author: <RDL Generator>
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#pragma once
|
||||
|
||||
#include <util/bit_field.h>
|
||||
#include <cstdint>
|
||||
|
||||
#define SPN_CNTL_REG_START_RESULT_CHECK 0x00
|
||||
#define SPN_CNTL_REG_OFFSET 0x10
|
||||
#define SPN_CNTL_REG_LENGTH 0x20
|
||||
#define SPN_CNTL_REG_OUTPUT_ADDR 0x30
|
||||
#define SPN_CNTL_REG_INPUT_ADDR 0x40
|
||||
#define SPN_CNTL_REG_NUM_INPUT_SAMPLES 0x50
|
||||
#define SPN_CNTL_REG_START_DATA_TRANS 0x60
|
||||
#define SPN_CNTL_REG_OUTPUT_ADDR2 0x70
|
||||
#define SPN_CNTL_REG_XSPN_COUNT 0x80
|
||||
#define SPN_CNTL_REG_BATCH_SIZE 0x90
|
||||
#define SPN_CNTL_REG_NUM_ITERATIONS 0xA0
|
||||
|
||||
template<uint32_t BASE_ADDR>
|
||||
class spn_checker_regs {
|
||||
public:
|
||||
// storage declarations
|
||||
// BEGIN_BF_DECL(start_t, uint32_t);
|
||||
// BF_FIELD(start, 0, 1);
|
||||
// END_BF_DECL() r_start;
|
||||
uint32_t r_start_result_check;
|
||||
|
||||
uint32_t r_offset;
|
||||
|
||||
uint32_t r_length;
|
||||
|
||||
uint32_t r_output_addr;
|
||||
|
||||
uint32_t r_output_addr2;
|
||||
|
||||
uint32_t r_input_addr;
|
||||
|
||||
uint32_t r_num_input_samples;
|
||||
|
||||
uint32_t r_start_data_trans;
|
||||
|
||||
uint32_t r_xspn_count;
|
||||
|
||||
uint32_t r_batch_size;
|
||||
|
||||
uint32_t r_num_iterations;
|
||||
|
||||
static inline uint32_t& start_result_check_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_START_RESULT_CHECK);
|
||||
}
|
||||
|
||||
static inline uint32_t & offset_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_OFFSET);
|
||||
}
|
||||
|
||||
static inline uint32_t & length_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_LENGTH);
|
||||
}
|
||||
|
||||
static inline uint32_t & output_addr_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_OUTPUT_ADDR);
|
||||
}
|
||||
|
||||
static inline uint32_t & output_addr2_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_OUTPUT_ADDR2);
|
||||
}
|
||||
|
||||
static inline uint32_t & input_addr_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_INPUT_ADDR);
|
||||
}
|
||||
|
||||
static inline uint32_t & num_input_samples_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_NUM_INPUT_SAMPLES);
|
||||
}
|
||||
|
||||
static inline uint32_t& start_data_trans_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_START_DATA_TRANS);
|
||||
}
|
||||
|
||||
static inline uint32_t& xspn_count_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_XSPN_COUNT);
|
||||
}
|
||||
|
||||
static inline uint32_t& batch_size_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_BATCH_SIZE);
|
||||
}
|
||||
|
||||
static inline uint32_t& num_iterations_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_NUM_ITERATIONS);
|
||||
}
|
||||
|
||||
};
|
|
@ -1,116 +0,0 @@
|
|||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (C) 2017, MINRES Technologies GmbH
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
//
|
||||
// 1. Redistributions of source code must retain the above copyright notice,
|
||||
// this list of conditions and the following disclaimer.
|
||||
//
|
||||
// 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
// this list of conditions and the following disclaimer in the documentation
|
||||
// and/or other materials provided with the distribution.
|
||||
//
|
||||
// 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
// may be used to endorse or promote products derived from this software
|
||||
// without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
// POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Created on: Thu Oct 01 15:45:55 CEST 2020
|
||||
// * spn_regs.h Author: <RDL Generator>
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef _SPN_REGS_H_
|
||||
#define _SPN_REGS_H_
|
||||
|
||||
#include <util/bit_field.h>
|
||||
#include <cstdint>
|
||||
|
||||
#define SPN_REG_START 0x00
|
||||
#define SPN_REG_READOUT 0x10
|
||||
#define SPN_REG_MODE 0x20
|
||||
#define SPN_REG_INPUT_LENGTH 0x30
|
||||
#define SPN_REG_INPUT_ADDR 0x40
|
||||
#define SPN_REG_OUTPUT_ADDR 0x50
|
||||
#define SPN_REG_NUM_OF_INPUT_BEATS 0x60
|
||||
#define SPN_REG_NUM_OF_OUTPUT_BEATS 0x70
|
||||
#define SPN_REG_INTERRUPT 0x0C
|
||||
|
||||
template<uint32_t BASE_ADDR>
|
||||
class spn_regs {
|
||||
public:
|
||||
// storage declarations
|
||||
// BEGIN_BF_DECL(start_t, uint32_t);
|
||||
// BF_FIELD(start, 0, 1);
|
||||
// END_BF_DECL() r_start;
|
||||
uint32_t r_start;
|
||||
|
||||
uint32_t r_readout;
|
||||
|
||||
uint32_t r_mode;
|
||||
|
||||
uint32_t r_input_length;
|
||||
|
||||
uint32_t r_input_addr;
|
||||
|
||||
uint32_t r_output_addr;
|
||||
|
||||
uint32_t r_num_of_input_beats;
|
||||
|
||||
uint32_t r_num_of_output_beats;
|
||||
|
||||
// static inline start_t& start_reg(){
|
||||
// return *reinterpret_cast<start_t*>(BASE_ADDR+SPN_REG_START);
|
||||
// }
|
||||
static inline uint32_t& start_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_REG_START);
|
||||
}
|
||||
|
||||
static inline uint32_t & readout_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_REG_READOUT);
|
||||
}
|
||||
|
||||
static inline uint32_t & mode_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_REG_MODE);
|
||||
}
|
||||
|
||||
static inline uint32_t & input_length_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_REG_INPUT_LENGTH);
|
||||
}
|
||||
|
||||
static inline uint32_t & input_addr_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_REG_INPUT_ADDR);
|
||||
}
|
||||
|
||||
static inline uint32_t & output_addr_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_REG_OUTPUT_ADDR);
|
||||
}
|
||||
|
||||
static inline uint32_t & num_of_in_beats_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_REG_NUM_OF_INPUT_BEATS);
|
||||
}
|
||||
|
||||
static inline uint32_t & num_of_out_beats_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_REG_NUM_OF_OUTPUT_BEATS);
|
||||
}
|
||||
|
||||
static inline uint32_t & interrupt_reg(){
|
||||
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_REG_INTERRUPT);
|
||||
}
|
||||
|
||||
};
|
||||
|
||||
#endif // _SPN_REGS_H_
|
|
@ -1,179 +0,0 @@
|
|||
/*---------------------------------------------------------
|
||||
Copyright (c) 2015 Jeff Preshing
|
||||
|
||||
This software is provided 'as-is', without any express or implied
|
||||
warranty. In no event will the authors be held liable for any damages
|
||||
arising from the use of this software.
|
||||
|
||||
Permission is granted to anyone to use this software for any purpose,
|
||||
including commercial applications, and to alter it and redistribute it
|
||||
freely, subject to the following restrictions:
|
||||
|
||||
1. The origin of this software must not be misrepresented; you must not
|
||||
claim that you wrote the original software. If you use this software
|
||||
in a product, an acknowledgement in the product documentation would be
|
||||
appreciated but is not required.
|
||||
2. Altered source versions must be plainly marked as such, and must not be
|
||||
misrepresented as being the original software.
|
||||
3. This notice may not be removed or altered from any source distribution.
|
||||
---------------------------------------------------------*/
|
||||
|
||||
#ifndef BIT_FIELD_H_
|
||||
#define BIT_FIELD_H_
|
||||
|
||||
#ifndef __CPP11OM_BITFIELD_H__
|
||||
#define __CPP11OM_BITFIELD_H__
|
||||
|
||||
#include <cassert>
|
||||
|
||||
//---------------------------------------------------------
|
||||
// BitFieldMember<>: Used internally by ADD_BITFIELD_MEMBER macro.
|
||||
// All members are public to simplify compliance with sections 9.0.7 and
|
||||
// 9.5.1 of the C++11 standard, thereby avoiding undefined behavior.
|
||||
//---------------------------------------------------------
|
||||
template <typename T, int Offset, int Bits> struct BitFieldMember {
|
||||
T value;
|
||||
|
||||
static_assert(Offset + Bits <= (int)sizeof(T) * 8, "Member exceeds bitfield boundaries");
|
||||
static_assert(Bits < (int)sizeof(T) * 8, "Can't fill entire bitfield with one member");
|
||||
|
||||
static const T Maximum = (T(1) << Bits) - 1;
|
||||
static const T Mask = Maximum << Offset;
|
||||
T maximum() const { return Maximum; }
|
||||
T one() const { return T(1) << Offset; }
|
||||
|
||||
operator T() const { return (value >> Offset) & Maximum; }
|
||||
|
||||
BitFieldMember &operator=(T v) {
|
||||
assert(v <= Maximum); // v must fit inside the bitfield member
|
||||
value = (value & ~Mask) | (v << Offset);
|
||||
return *this;
|
||||
}
|
||||
|
||||
BitFieldMember &operator+=(T v) {
|
||||
assert(T(*this) + v <= Maximum); // result must fit inside the bitfield member
|
||||
value += v << Offset;
|
||||
return *this;
|
||||
}
|
||||
|
||||
BitFieldMember &operator-=(T v) {
|
||||
assert(T(*this) >= v); // result must not underflow
|
||||
value -= v << Offset;
|
||||
return *this;
|
||||
}
|
||||
|
||||
BitFieldMember &operator++() { return *this += 1; }
|
||||
BitFieldMember operator++(int) { // postfix form
|
||||
BitFieldMember tmp(*this);
|
||||
operator++();
|
||||
return tmp;
|
||||
}
|
||||
BitFieldMember &operator--() { return *this -= 1; }
|
||||
BitFieldMember operator--(int) { // postfix form
|
||||
BitFieldMember tmp(*this);
|
||||
operator--();
|
||||
return tmp;
|
||||
}
|
||||
};
|
||||
|
||||
//---------------------------------------------------------
|
||||
// BitFieldArray<>: Used internally by ADD_BITFIELD_ARRAY macro.
|
||||
// All members are public to simplify compliance with sections 9.0.7 and
|
||||
// 9.5.1 of the C++11 standard, thereby avoiding undefined behavior.
|
||||
//---------------------------------------------------------
|
||||
template <typename T, int BaseOffset, int BitsPerItem, int NumItems> class BitFieldArray {
|
||||
public:
|
||||
T value;
|
||||
|
||||
static_assert(BaseOffset + BitsPerItem * NumItems <= (int)sizeof(T) * 8, "Array exceeds bitfield boundaries");
|
||||
static_assert(BitsPerItem < (int)sizeof(T) * 8, "Can't fill entire bitfield with one array element");
|
||||
|
||||
static const T Maximum = (T(1) << BitsPerItem) - 1;
|
||||
T maximum() const { return Maximum; }
|
||||
int numItems() const { return NumItems; }
|
||||
|
||||
class Element {
|
||||
private:
|
||||
T &value;
|
||||
int offset;
|
||||
|
||||
public:
|
||||
Element(T &value, int offset)
|
||||
: value(value)
|
||||
, offset(offset) {}
|
||||
T mask() const { return Maximum << offset; }
|
||||
|
||||
operator T() const { return (value >> offset) & Maximum; }
|
||||
|
||||
Element &operator=(T v) {
|
||||
assert(v <= Maximum); // v must fit inside the bitfield member
|
||||
value = (value & ~mask()) | (v << offset);
|
||||
return *this;
|
||||
}
|
||||
|
||||
Element &operator+=(T v) {
|
||||
assert(T(*this) + v <= Maximum); // result must fit inside the bitfield member
|
||||
value += v << offset;
|
||||
return *this;
|
||||
}
|
||||
|
||||
Element &operator-=(T v) {
|
||||
assert(T(*this) >= v); // result must not underflow
|
||||
value -= v << offset;
|
||||
return *this;
|
||||
}
|
||||
|
||||
Element &operator++() { return *this += 1; }
|
||||
Element operator++(int) { // postfix form
|
||||
Element tmp(*this);
|
||||
operator++();
|
||||
return tmp;
|
||||
}
|
||||
Element &operator--() { return *this -= 1; }
|
||||
Element operator--(int) { // postfix form
|
||||
Element tmp(*this);
|
||||
operator--();
|
||||
return tmp;
|
||||
}
|
||||
};
|
||||
|
||||
Element operator[](int i) {
|
||||
assert(i >= 0 && i < NumItems); // array index must be in range
|
||||
return Element(value, BaseOffset + BitsPerItem * i);
|
||||
}
|
||||
|
||||
const Element operator[](int i) const {
|
||||
assert(i >= 0 && i < NumItems); // array index must be in range
|
||||
return Element(value, BaseOffset + BitsPerItem * i);
|
||||
}
|
||||
};
|
||||
|
||||
//---------------------------------------------------------
|
||||
// Bitfield definition macros.
|
||||
// All members are public to simplify compliance with sections 9.0.7 and
|
||||
// 9.5.1 of the C++11 standard, thereby avoiding undefined behavior.
|
||||
//---------------------------------------------------------
|
||||
#define BEGIN_BF_DECL(typeName, T) \
|
||||
union typeName { \
|
||||
struct Wrapper { \
|
||||
T value; \
|
||||
}; \
|
||||
Wrapper flat; \
|
||||
typeName(T v = 0) { flat.value = v; } \
|
||||
typeName &operator=(T v) { \
|
||||
flat.value = v; \
|
||||
return *this; \
|
||||
} \
|
||||
operator T &() { return flat.value; } \
|
||||
operator T() const { return flat.value; } \
|
||||
using StorageType = T;
|
||||
|
||||
#define BF_FIELD(memberName, offset, bits) BitFieldMember<StorageType, offset, bits> memberName;
|
||||
|
||||
#define BF_ARRAY(memberName, offset, bits, numItems) BitFieldArray<StorageType, offset, bits, numItems> memberName;
|
||||
|
||||
#define END_BF_DECL() }
|
||||
|
||||
#endif // __CPP11OM_BITFIELD_H__
|
||||
|
||||
#endif /* BIT_FIELD_H_ */
|
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Reference in New Issue