add entry_threadx.s

test_fw/entry_threadx.S

@@ -0,0 +1,53 @@
+// See LICENSE for license details
+
+#ifndef ENTRY_S
+#define ENTRY_S
+
+#include "encoding.h"
+#include "bits.h"
+
+msg:
+    .string "enter trap_entry of entry_threadx!\n"
+  .section      .text.entry	
+  .align 2
+  .global trap_entry
+  .extern  _tx_thread_context_save
+  .extern  _tx_thread_context_restore
+
+trap_entry:
+
+
+
+
+#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
+	addi sp, sp, -65*REGBYTES         // Allocate space for all registers - with floating point enabled
+#else
+	addi sp, sp, -32*REGBYTES         // Allocate space for all registers - without floating point enabled
+#endif
+
+	STORE   x1, 28*REGBYTES(sp)       // Store RA, 28*REGBYTES(because call will override ra [ra is a calle register in riscv])
+
+#la   a0, msg     # a0 = pointer to string
+#jal  ra, puts    # call puts(msg)
+
+    	call    _tx_thread_context_save    	
+
+#  la   a0, msg     # a0 = pointer to string
+#  jal  ra, puts    # call puts(msg)
+
+	csrr a0, mcause
+	csrr a1, mepc
+  mv a2, sp   // which sp is needed? sp of interrupted context or the sp of _tx_thread_context_save???
+	addi    sp, sp, -8
+  sd      ra, 0(sp)
+  call    handle_trap
+  ld      ra, 0(sp)
+  addi    sp, sp, 8
+	call _tx_thread_context_restore 
+
+//.weak handle_trap
+//handle_trap:
+//1:
+ // j 1b
+	
+#endif