add tgc_c_xrb_nn to tgc-sim
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parent
68b5697c8f
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11
src/main.cpp
11
src/main.cpp
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@ -44,6 +44,11 @@ using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
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#include "iss/arch/tgc_b.h"
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using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
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#endif
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#ifdef CORE_TGC_C_XRB_NN
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#include "iss/arch/riscv_hart_m_p.h"
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#include "iss/arch/tgc_c_xrb_nn.h"
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using tgc_c_xrb_nn_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c_xrb_nn>;
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#endif
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#ifdef CORE_TGC_D
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#include "iss/arch/riscv_hart_mu_p.h"
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#include "iss/arch/tgc_d.h"
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@ -152,6 +157,12 @@ int main(int argc, char *argv[]) {
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iss::create_cpu<tgc_b_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
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} else
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#endif
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#ifdef CORE_TGC_C_XRB_NN
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if (isa_opt == "tgc_c_xrb_nn") {
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std::tie(cpu, vm) =
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iss::create_cpu<tgc_c_xrb_nn_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
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} else
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#endif
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#ifdef CORE_TGC_D
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if (isa_opt == "tgc_d") {
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std::tie(cpu, vm) =
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