From ac86f14a54699647590b57455b437c337995f1d1 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Wed, 2 Feb 2022 21:33:42 +0100
Subject: [PATCH] add tgc_c_xrb_nn to tgc-sim

---
 src/main.cpp | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/src/main.cpp b/src/main.cpp
index ee978e3..88c9812 100644
--- a/src/main.cpp
+++ b/src/main.cpp
@@ -44,6 +44,11 @@ using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
 #include "iss/arch/tgc_b.h"
 using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
 #endif
+#ifdef CORE_TGC_C_XRB_NN
+#include "iss/arch/riscv_hart_m_p.h"
+#include "iss/arch/tgc_c_xrb_nn.h"
+using tgc_c_xrb_nn_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c_xrb_nn>;
+#endif
 #ifdef CORE_TGC_D
 #include "iss/arch/riscv_hart_mu_p.h"
 #include "iss/arch/tgc_d.h"
@@ -152,6 +157,12 @@ int main(int argc, char *argv[]) {
                 iss::create_cpu<tgc_b_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
         } else
 #endif
+#ifdef CORE_TGC_C_XRB_NN
+        if (isa_opt == "tgc_c_xrb_nn") {
+            std::tie(cpu, vm) =
+                iss::create_cpu<tgc_c_xrb_nn_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+        } else
+#endif
 #ifdef CORE_TGC_D
         if (isa_opt == "tgc_d") {
             std::tie(cpu, vm) =