DBT-RISE-TGC/gen_input/TGFS.core_desc

import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
import "CoreDSL-Instruction-Set-Description/RVC.core_desc"

Core TGC_B provides RV32I {
	architectural_state {
        unsigned XLEN=32;
        unsigned PCLEN=32;
        // definitions for the architecture wrapper
        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
        unsigned MISA_VAL = 0b01000000000000000000000100000000;
        unsigned PGSIZE = 0x1000; //1 << 12;
        unsigned PGMASK = 0xfff; //PGSIZE-1
	}
}

Core TGC_C provides RV32I, RV32M, RV32IC {
    architectural_state {
        unsigned XLEN=32;
        unsigned PCLEN=32;
        // definitions for the architecture wrapper
        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
        unsigned MISA_VAL = 0b01000000000000000001000100000100;
        unsigned PGSIZE = 0x1000; //1 << 12;
        unsigned PGMASK = 0xfff; //PGSIZE-1
    }
}

Core TGC_D provides RV32I, RV32M, RV32IC {
    architectural_state {
        unsigned XLEN=32;
        unsigned PCLEN=32;
        // definitions for the architecture wrapper
        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
        unsigned MISA_VAL = 0b01000000000000000001000100000100;
    }
}