Eyck Jentzsch
873e4257f2
This should enable the implementation of multi-threading of the compilation process
52 lines
1.8 KiB
Markdown
52 lines
1.8 KiB
Markdown
# DBT-RISE-RISCV
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Am instruction set simulator based on DBT-RISE implementing the RISC-V ISA
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**DBT-RISE-RISCV README**
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This is work in progress, so use at your own risk. Goal is to implement an open-source ISS which can easily embedded e.g. into SystemC Virtual Prototypes. It used code generation to allow easy extension and adaptation of the used instruction.
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The RISC-V ISS reaches about 30MIPS running on Intel Core i7-2600K.
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The implementation is based on LLVM 4.0. Eclipse CDT 4.7 (Oxygen) is recommended as IDE.
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DBT-RISE-RISCV uses libGIS (https://github.com/vsergeev/libGIS) as well as ELFIO (http://elfio.sourceforge.net/), both under MIT license
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**What's missing**
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* F & D standard extensions for 32bit to be implemented
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* MACF &D standard extensions for 64bit to be implemented and verified
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**Planned features**
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* add platform peripherals beyond programmers view to resemble E300 platform
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* QSPI
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* PWM
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* ...
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* and more
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**Quick start**
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* you need to have a decent compiler, make, python, and cmake installed
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* install LLVM 4.0 according to http://apt.llvm.org/ (if it is not already provided by your distribution e.g by Ubuntu 17.04)
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* install conan.io (see also http://docs.conan.io/en/latest/installation.html):
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```
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pip install conan
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```
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* setup conan to use the minres repo:
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```
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conan remote add minres https://api.bintray.com/conan/minres/conan-repo
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```
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* checkout source from git
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* start an out-of-source build:
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```
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cd DBT-RISE-RiscV
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mkdir build
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cd build
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cmake ..
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cmake --build .
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```
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* if you encounter issues when linking wrt. c++11 symbols you might have run into GCC ABI incompatibility introduced from GCC 5.0 onwards. You can fix this by adding '-s compiler.libcxx=libstdc++11' to the conan call or changing compiler.libcxx to
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```
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compiler.libcxx=libstdc++11
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```
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in $HOME/.conan/profiles/default
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