44 lines
1.6 KiB
Markdown
44 lines
1.6 KiB
Markdown
# DBT-RISE-RiscV
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Am instruction set simulator based on DBT-RISE implementing the Risc-V ISA
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**DBT-RISE-RiscV README**
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This is work in progress, so use at your own risk. Goal is to implement an open-source ISS which can easily embedded e.g. into SystemC Virtual Prototypes. It used code generation to allow easy extension and adaptation of the used instruction.
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The Risc-V ISS reaches about 20MIPS at an Intel Core i7-2600K.
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The implementation is based on LLVM 4.0. Eclipse CDT 4.7 (Oxygen) is recommended as IDE.
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DBT-RISE-RiscV uses libGIS (https://github.com/vsergeev/libGIS) as well as ELFIO (http://elfio.sourceforge.net/), both under MIT license
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**What's missing**
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* RV64I is only preliminary verified
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* F & D standard extensions to be implemented
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**Planned features**
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* add platform peripherals to resemble E300 platform
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* PLIC
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* gpio
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* ...
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* and more
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**Quick start**
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* you need to have a decent compiler, make and cmake installed
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* install LLVM 4.0 according to http://apt.llvm.org/
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* download and install SystemC from http://accellera.org/downloads/standards/systemc
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* optionally download and install SystemC Verification Library (SCV) from Accelera into the same location
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* checkout source from git
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* start an out-of-source build like so (e.g. when using LLVM 3.9 and bash)
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```
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cd DBT-RISE-RiscV
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mkdir build
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cd build
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cmake ..
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make
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```
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* if the SystemC installation is not found by cmake you can optionally specify the location by either setting the following environment variables pointing to the installation
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- SYSTEMC_HOME
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- SYSTEMC_PREFIX
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