292 lines
12 KiB
Plaintext
292 lines
12 KiB
Plaintext
/*******************************************************************************
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* Copyright (C) 2020 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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#include <iss/arch/${coreDef.name.toLowerCase()}.h>
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#include <iss/arch/riscv_hart_msu_vp.h>
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#include <iss/debugger/gdb_session.h>
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#include <iss/debugger/server.h>
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#include <iss/iss.h>
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#include <iss/tcc/vm_base.h>
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#include <util/logging.h>
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#include <sstream>
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#ifndef FMT_HEADER_ONLY
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#define FMT_HEADER_ONLY
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#endif
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#include <fmt/format.h>
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#include <array>
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#include <iss/debugger/riscv_target_adapter.h>
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namespace iss {
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namespace tcc {
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namespace ${coreDef.name.toLowerCase()} {
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using namespace iss::arch;
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using namespace iss::debugger;
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template <typename ARCH> class vm_impl : public iss::tcc::vm_base<ARCH> {
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public:
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using super = typename iss::tcc::vm_base<ARCH>;
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using virt_addr_t = typename super::virt_addr_t;
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using phys_addr_t = typename super::phys_addr_t;
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using code_word_t = typename super::code_word_t;
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using addr_t = typename super::addr_t;
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using tu_builder = typename super::tu_builder;
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vm_impl();
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vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
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void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
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target_adapter_if *accquire_target_adapter(server_if *srv) override {
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debugger_if::dbg_enabled = true;
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if (vm_base<ARCH>::tgt_adapter == nullptr)
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vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
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return vm_base<ARCH>::tgt_adapter;
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}
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protected:
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using vm_base<ARCH>::get_reg_ptr;
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using this_class = vm_impl<ARCH>;
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using compile_ret_t = std::tuple<continuation_e>;
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using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, tu_builder&);
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inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
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void setup_module(std::string m) override {
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super::setup_module(m);
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}
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compile_ret_t gen_single_inst_behavior(virt_addr_t &, unsigned int &, tu_builder&) override;
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void gen_trap_behavior(tu_builder& tu) override;
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void gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause);
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void gen_leave_trap(tu_builder& tu, unsigned lvl);
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void gen_wait(tu_builder& tu, unsigned type);
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inline void gen_trap_check(tu_builder& tu) {
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tu("if(*trap_state!=0) goto trap_entry;");
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}
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inline void gen_set_pc(tu_builder& tu, virt_addr_t pc, unsigned reg_num) {
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switch(reg_num){
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case traits<ARCH>::NEXT_PC:
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tu("*next_pc = {:#x};", pc.val);
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break;
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case traits<ARCH>::PC:
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tu("*pc = {:#x};", pc.val);
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break;
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default:
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if(!tu.defined_regs[reg_num]){
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tu("reg_t* reg{:02d} = (reg_t*){:#x};", reg_num, reinterpret_cast<uintptr_t>(get_reg_ptr(reg_num)));
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tu.defined_regs[reg_num]=true;
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}
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tu("*reg{:02d} = {:#x};", reg_num, pc.val);
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}
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}
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// some compile time constants
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// enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
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enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
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enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
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enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
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std::array<compile_func, LUT_SIZE> lut;
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std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
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std::array<compile_func, LUT_SIZE> lut_11;
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std::array<compile_func *, 4> qlut;
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std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
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void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
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compile_func f) {
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if (pos < 0) {
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lut[idx] = f;
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} else {
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auto bitmask = 1UL << pos;
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if ((mask & bitmask) == 0) {
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expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
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} else {
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if ((valid & bitmask) == 0) {
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expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
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expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
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} else {
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auto new_val = idx << 1;
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if ((value & bitmask) != 0) new_val++;
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expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
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}
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}
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}
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}
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inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
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uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
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if (pos >= 0) {
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auto bitmask = 1UL << pos;
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if ((mask & bitmask) == 0) {
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lut_val = extract_fields(pos - 1, val, mask, lut_val);
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} else {
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auto new_val = lut_val << 1;
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if ((val & bitmask) != 0) new_val++;
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lut_val = extract_fields(pos - 1, val, mask, new_val);
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}
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}
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return lut_val;
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}
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private:
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/****************************************************************************
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* start opcode definitions
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****************************************************************************/
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struct InstructionDesriptor {
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size_t length;
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uint32_t value;
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uint32_t mask;
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compile_func op;
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};
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const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
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/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
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/* instruction ${instr.instruction.name} */
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{${instr.length}, ${instr.value}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
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}};
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/* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
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/* instruction ${idx}: ${instr.name} */
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compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, tu_builder& tu){<%instr.code.eachLine{%>
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${it}<%}%>
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}
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<%}%>
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/****************************************************************************
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* end opcode definitions
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****************************************************************************/
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compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr, tu_builder& tu) {
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vm_impl::gen_sync(tu, iss::PRE_SYNC, instr_descr.size());
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pc = pc + ((instr & 3) == 3 ? 4 : 2);
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gen_raise_trap(tu, 0, 2); // illegal instruction trap
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vm_impl::gen_sync(tu, iss::POST_SYNC, instr_descr.size());
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vm_impl::gen_trap_check(tu);
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return BRANCH;
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}
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};
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template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
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volatile CODE_WORD x = insn;
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insn = 2 * x;
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}
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template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
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template <typename ARCH>
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vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
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: vm_base<ARCH>(core, core_id, cluster_id) {
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qlut[0] = lut_00.data();
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qlut[1] = lut_01.data();
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qlut[2] = lut_10.data();
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qlut[3] = lut_11.data();
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for (auto instr : instr_descr) {
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auto quantrant = instr.value & 0x3;
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expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
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}
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}
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template <typename ARCH>
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std::tuple<continuation_e>
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vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, tu_builder& tu) {
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// we fetch at max 4 byte, alignment is 2
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enum {TRAP_ID=1<<16};
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code_word_t insn = 0;
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const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
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phys_addr_t paddr(pc);
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auto *const data = (uint8_t *)&insn;
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paddr = this->core.v2p(pc);
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if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
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auto res = this->core.read(paddr, 2, data);
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if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
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if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
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res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
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}
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} else {
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auto res = this->core.read(paddr, 4, data);
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if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
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}
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if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
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// curr pc on stack
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++inst_cnt;
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auto lut_val = extract_fields(insn);
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auto f = qlut[insn & 0x3][lut_val];
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if (f == nullptr) {
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f = &this_class::illegal_intruction;
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}
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return (this->*f)(pc, insn, tu);
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}
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template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) {
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tu(" *trap_state = {:#x};", 0x80 << 24 | (cause << 16) | trap_id);
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tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
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}
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template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsigned lvl) {
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tu("leave_trap(core_ptr, {});", lvl);
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tu.store(tu.read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN),traits<ARCH>::NEXT_PC);
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tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
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}
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template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned type) {
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}
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template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
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tu("trap_entry:");
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tu("enter_trap(core_ptr, *trap_state, *pc);");
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tu.store(tu.constant(std::numeric_limits<uint32_t>::max(),32),traits<ARCH>::LAST_BRANCH);
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tu("return *next_pc;");
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}
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} // namespace mnrv32
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template <>
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std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
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auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
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if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
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return std::unique_ptr<vm_if>(ret);
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}
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}
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} // namespace iss
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