changes time handling at sockets

contrib/tgc_import_tb.tcl

@@ -5,9 +5,9 @@ set FW_name ${scriptDir}/hello.elf
 puts "instantiate testbench elements"
 ::paultra::add_hw_instance GenericIPlib:Memory_Generic -inst_name i_Memory_Generic
 ::pct::set_param_value i_Memory_Generic/MEM:protocol {Protocol Common Parameters} address_width 30
-#::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/LT/clock_period_in_ns 1
+::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/LT/clock_period_in_ns 1
-#::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/read/cmd_accept_cycles 1
+::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/read/cmd_accept_cycles 1
-#::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/write/cmd_accept_cycles 1
+::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/write/cmd_accept_cycles 1
 ::pct::set_bounds i_Memory_Generic 1000 300 100 100
 
 ::paultra::add_hw_instance Bus:Bus -inst_name i_Bus

src/sysc/core_complex.cpp

@@ -107,7 +107,8 @@ public:
     heart_state_t &get_state() { return this->state; }
 
     void notify_phase(iss::arch_if::exec_phase p) override {
-        if (p == iss::arch_if::ISTART) owner->sync(this->icount);
+        if (p == iss::arch_if::ISTART)
+            owner->sync(this->instr_if.get_total_cycles());
     }
 
     sync_type needed_sync() const override { return PRE_SYNC; }
@@ -547,8 +548,12 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data,
             gp.set_extension(preExt);
         }
         sckt->b_transport(gp, delay);
-        quantum_keeper.set(delay);
+        auto incr = delay-quantum_keeper.get_local_time();
-        SCCTRACE(this->name()) << "read_mem(0x" << std::hex << addr << ") : 0x" << (length==4?*(uint32_t*)data:length==2?*(uint16_t*)data:(unsigned)*data);
+        if(is_fetch)
+            ibus_inc+=incr;
+        else
+            dbus_inc+=incr;
+        SCCTRACE(this->name()) << "[local time: "<<delay<<"]: finish read_mem(0x" << std::hex << addr << ") : 0x" << (length==4?*(uint32_t*)data:length==2?*(uint16_t*)data:(unsigned)*data);
         if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
             return false;
         }
@@ -589,8 +594,8 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
             gp.set_extension(preExt);
         }
         dbus->b_transport(gp, delay);
-        quantum_keeper.set(delay);
+        dbus_inc+=delay-quantum_keeper.get_local_time();
-        SCCTRACE() << "write_mem(0x" << std::hex << addr << ") : 0x" << (length==4?*(uint32_t*)data:length==2?*(uint16_t*)data:(unsigned)*data);
+        SCCTRACE() << "[local time: "<<delay<<"]: finish write_mem(0x" << std::hex << addr << ") : 0x" << (length==4?*(uint32_t*)data:length==2?*(uint16_t*)data:(unsigned)*data);
         if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
             return false;
         }

src/sysc/core_complex.h

@@ -157,13 +157,16 @@ public:
     ~core_complex();
 
     inline void sync(uint64_t cycle) {
-        auto time = curr_clk * (cycle - last_sync_cycle);
+        auto core_inc = curr_clk * (cycle - last_sync_cycle);
-        quantum_keeper.inc(time);
+        auto incr = std::max(core_inc, std::max(ibus_inc, dbus_inc));
+        quantum_keeper.inc(incr);
         if (quantum_keeper.need_sync()) {
             wait(quantum_keeper.get_local_time());
             quantum_keeper.reset();
         }
         last_sync_cycle = cycle;
+        ibus_inc = SC_ZERO_TIME;
+        dbus_inc = SC_ZERO_TIME;
     }
 
     bool read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch);
@@ -195,6 +198,7 @@ protected:
     std::vector<uint8_t> write_buf;
     core_wrapper* cpu{nullptr};
     sc_core::sc_signal<sc_core::sc_time> curr_clk;
+    sc_core::sc_time ibus_inc, dbus_inc;
     core_trace* trc{nullptr};
     std::unique_ptr<scc::tick2time> t2t;
 private:
@@ -202,7 +206,7 @@ private:
     std::vector<iss::vm_plugin *> plugin_list;
 
 };
-} /* namespace SiFive */
+} /* namespace tgfs */
 } /* namespace sysc */
 
 #endif /* _SYSC_CORE_COMPLEX_H_ */