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8 Commits
bfa2182f8e
...
featture/i
Author | SHA1 | Date | |
---|---|---|---|
071cb4fdac | |||
dd937710a7 | |||
047e2e12b0 | |||
fe3ed49519 | |||
1afd77a942 | |||
cdf5038e59 | |||
651897e1e4 | |||
a1803c61c1 |
@ -12,6 +12,7 @@ include(flink)
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find_package(elfio QUIET)
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find_package(jsoncpp)
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find_package(Boost COMPONENTS coroutine REQUIRED)
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find_package(absl REQUIRED)
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add_subdirectory(softfloat)
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@ -104,7 +105,7 @@ if(NOT(DBT_CORE_DEFS STREQUAL DBT_CORE_DEFS-NOTFOUND))
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target_compile_definitions(${PROJECT_NAME} INTERFACE ${DBT_CORE_DEFS})
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endif()
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target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio softfloat scc-util Boost::coroutine)
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target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio softfloat scc-util Boost::coroutine abseil::abseil)
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if(TARGET yaml-cpp::yaml-cpp)
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target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_PLUGINS)
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@ -40,7 +40,11 @@
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#include <iss/instruction_decoder.h>
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<%def fcsr = registers.find {it.name=='FCSR'}
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if(fcsr != null) {%>
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#include <vm/fp_functions.h><%}%>
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#include <vm/fp_functions.h><%}
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def aes = functions.find { it.contains('aes') }
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if(aes != null) {%>
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#include <vm/aes_sbox.h>
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<%}%>
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#ifndef FMT_HEADER_ONLY
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#define FMT_HEADER_ONLY
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#endif
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@ -49,6 +53,22 @@ if(fcsr != null) {%>
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#include <array>
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#include <iss/debugger/riscv_target_adapter.h>
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#ifndef _MSC_VER
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using int128_t = __int128;
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using uint128_t = unsigned __int128;
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namespace std {
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template <> struct make_unsigned<__int128> { typedef unsigned __int128 type; };
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template <> class __make_unsigned_selector<__int128 unsigned, false, false> {
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public:
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typedef unsigned __int128 __type;
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};
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template <> struct is_signed<int128_t> { static constexpr bool value = true; };
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template <> struct is_signed<uint128_t> { static constexpr bool value = false; };
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template <> struct is_unsigned<int128_t> { static constexpr bool value = false; };
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template <> struct is_unsigned<uint128_t> { static constexpr bool value = true; };
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} // namespace std
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#endif
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namespace iss {
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namespace asmjit {
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@ -116,38 +136,14 @@ protected:
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auto sign_mask = 1ULL<<(W-1);
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return (from & mask) | ((from & sign_mask) ? ~mask : 0);
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}
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inline void raise(uint16_t trap_id, uint16_t cause){
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auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id;
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this->core.reg.trap_state = trap_val;
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}
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<%functions.each{ it.eachLine { %>
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${it}<%}
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}
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if(fcsr != null) {%>
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x86_reg_t NaNBox16(jit_holder& jh , x86_reg_t NaNBox16_val){
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x86::Compiler& cc = jh.cc;
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if(static_cast<uint32_t>(traits::FLEN) == 16)
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return gen_ext(cc, NaNBox16_val, traits::FLEN, false);
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else {
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auto box = gen_operation(cc, bnot, (gen_ext(cc, 0, traits::FLEN, false)));
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return gen_ext(cc, (gen_operation(jh.cc, bor, gen_ext(jh.cc, gen_operation(jh.cc, shl, box, 16), traits::FLEN, false), gen_ext(jh.cc, NaNBox16_val, traits::FLEN, false))), traits::FLEN, false);
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}
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}
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x86_reg_t NaNBox32(jit_holder& jh , x86_reg_t NaNBox32_val){
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x86::Compiler& cc = jh.cc;
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if(static_cast<uint32_t>(traits::FLEN) == 32)
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return gen_ext(cc, NaNBox32_val, traits::FLEN, false);
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else {
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auto box = gen_operation(cc, bnot, (gen_ext(cc, 0, /* we need to shift for 32 so need larger dt*/ 64, false)));
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return gen_ext(cc, (gen_operation(jh.cc, bor, gen_ext(jh.cc, gen_operation(jh.cc, shl, box, 32), traits::FLEN, false), gen_ext(jh.cc, NaNBox32_val, traits::FLEN, false))), traits::FLEN, false);
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}
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}
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x86_reg_t NaNBox64(jit_holder& jh , x86_reg_t NaNBox64_val){
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x86::Compiler& cc = jh.cc;
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if(static_cast<uint32_t>(traits::FLEN) == 64)
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return gen_ext(cc, NaNBox64_val, traits::FLEN, false);
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else {
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auto box = gen_operation(cc, bnot, (gen_ext(cc, 0, /* we need to shift for 32 so need larger dt*/ 128, false)));
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return gen_ext(cc, (gen_operation(jh.cc, bor, gen_ext(jh.cc, gen_operation(jh.cc, shl, box, 64), traits::FLEN, false), gen_ext(jh.cc, NaNBox64_val, traits::FLEN, false))), traits::FLEN, false);
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}
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}
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<%}%>
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}%>
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private:
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/****************************************************************************
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* start opcode definitions
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@ -195,7 +191,6 @@ private:
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mov(cc, jh.next_pc, pc.val);
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gen_instr_prologue(jh);
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cc.comment("//behavior:");
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/*generate behavior*/
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<%instr.behavior.eachLine{%>${it}
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<%}%>
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@ -226,7 +221,6 @@ private:
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pc = pc + ((instr & 3) == 3 ? 4 : 2);
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mov(cc, jh.next_pc, pc.val);
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gen_instr_prologue(jh);
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cc.comment("//behavior:");
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gen_raise(jh, 0, 2);
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gen_sync(jh, POST_SYNC, instr_descr.size());
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gen_instr_epilogue(jh);
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@ -272,24 +266,25 @@ template <typename ARCH>
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void vm_impl<ARCH>::gen_instr_prologue(jit_holder& jh) {
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auto& cc = jh.cc;
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cc.comment("//gen_instr_prologue");
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x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE);
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mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
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mov(cc, get_ptr_for(jh, traits::PENDING_TRAP), current_trap_state);
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cc.comment("//Instruction prologue end");
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}
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template <typename ARCH>
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void vm_impl<ARCH>::gen_instr_epilogue(jit_holder& jh) {
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auto& cc = jh.cc;
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cc.comment("//gen_instr_epilogue");
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cc.comment("//Instruction epilogue begin");
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x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE);
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mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
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cmp(cc, current_trap_state, 0);
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cc.jne(jh.trap_entry);
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cc.inc(get_ptr_for(jh, traits::ICOUNT));
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cc.inc(get_ptr_for(jh, traits::CYCLE));
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cc.comment("//Instruction epilogue end");
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}
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template <typename ARCH>
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void vm_impl<ARCH>::gen_block_prologue(jit_holder& jh){
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@ -301,7 +296,7 @@ void vm_impl<ARCH>::gen_block_prologue(jit_holder& jh){
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template <typename ARCH>
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void vm_impl<ARCH>::gen_block_epilogue(jit_holder& jh){
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x86::Compiler& cc = jh.cc;
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cc.comment("//gen_block_epilogue");
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cc.comment("//block epilogue begin");
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cc.ret(jh.next_pc);
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cc.bind(jh.trap_entry);
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@ -313,7 +308,6 @@ void vm_impl<ARCH>::gen_block_epilogue(jit_holder& jh){
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x86::Gp current_pc = get_reg_for_Gp(cc, traits::PC);
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mov(cc, current_pc, get_ptr_for(jh, traits::PC));
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cc.comment("//enter trap call;");
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InvokeNode* call_enter_trap;
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cc.invoke(&call_enter_trap, &enter_trap, FuncSignature::build<uint64_t, void*, uint64_t, uint64_t, uint64_t>());
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call_enter_trap->setArg(0, jh.arch_if_ptr);
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@ -331,7 +325,6 @@ void vm_impl<ARCH>::gen_block_epilogue(jit_holder& jh){
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template <typename ARCH>
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inline void vm_impl<ARCH>::gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause) {
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auto& cc = jh.cc;
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cc.comment("//gen_raise");
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auto tmp1 = get_reg_for(cc, traits::TRAP_STATE);
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mov(cc, tmp1, 0x80ULL << 24 | (cause << 16) | trap_id);
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mov(cc, get_ptr_for(jh, traits::TRAP_STATE), tmp1);
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@ -31,12 +31,14 @@
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*******************************************************************************/
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// clang-format off
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#include <iss/arch/${coreDef.name.toLowerCase()}.h>
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// vm_base needs to be included before gdb_session as termios.h (via boost and gdb_server) has a define which clashes with a variable
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// name in ConstantRange.h
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#include <iss/llvm/vm_base.h>
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#include <iss/iss.h>
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#include <iss/debugger/gdb_session.h>
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#include <iss/debugger/server.h>
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#include <iss/iss.h>
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#include <iss/llvm/vm_base.h>
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#include <util/logging.h>
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#include <iss/instruction_decoder.h>
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#include <util/logging.h>
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<%def fcsr = registers.find {it.name=='FCSR'}
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if(fcsr != null) {%>
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#include <vm/fp_functions.h><%}%>
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@ -360,6 +360,7 @@ template <typename ARCH> void vm_impl<ARCH>::add_prologue(tu_builder& tu){
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os << "uint64_t (*fmadd_d)(uint64_t v1, uint64_t v2, uint64_t v3, uint32_t op, uint8_t mode)=" << (uintptr_t)&fmadd_d << ";\\n";
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os << "uint64_t (*fsel_d)(uint64_t v1, uint64_t v2, uint32_t op)=" << (uintptr_t)&fsel_d << ";\\n";
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os << "uint64_t (*fclass_d)(uint64_t v1 )=" << (uintptr_t)&fclass_d << ";\\n";
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os << "uint64_t (*unbox_d)(uint8_t FLEN, uint64_t v)=" << (uintptr_t)&unbox_d << ";\\n";
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os << "uint32_t (*f64tof32)(uint64_t v1, uint8_t mode)=" << (uintptr_t)&f64tof32 << ";\\n";
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os << "uint64_t (*f32tof64)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&f32tof64 << ";\\n";
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@ -37,6 +37,7 @@
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#include "mstatus.h"
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#include "util/delegate.h"
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#include <absl/container/flat_hash_map.h>
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#include <array>
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#include <cstdint>
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#include <elfio/elfio.hpp>
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@ -259,8 +260,8 @@ template <typename WORD_TYPE> struct priv_if {
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std::function<iss::status(unsigned, WORD_TYPE)> write_csr;
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std::function<iss::status(uint8_t const*)> exec_htif;
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std::function<void(uint16_t, uint16_t, WORD_TYPE)> raise_trap; // trap_id, cause, fault_data
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std::unordered_map<unsigned, rd_csr_f>& csr_rd_cb;
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std::unordered_map<unsigned, wr_csr_f>& csr_wr_cb;
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absl::flat_hash_map<unsigned, rd_csr_f>& csr_rd_cb;
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absl::flat_hash_map<unsigned, wr_csr_f>& csr_wr_cb;
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hart_state<WORD_TYPE>& state;
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uint8_t& PRIV;
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WORD_TYPE& PC;
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@ -775,7 +776,7 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
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this->fault_data = fault_data;
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},
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.csr_rd_cb{this->csr_rd_cb},
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.csr_wr_cb{csr_wr_cb},
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.csr_wr_cb{this->csr_wr_cb},
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.state{this->state},
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.PRIV{this->reg.PRIV},
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.PC{this->reg.PC},
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@ -893,8 +894,8 @@ protected:
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using csr_page_type = typename csr_type::page_type;
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csr_type csr;
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std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
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std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
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absl::flat_hash_map<unsigned, rd_csr_f> csr_rd_cb;
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absl::flat_hash_map<unsigned, wr_csr_f> csr_wr_cb;
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reg_t mhartid_reg{0x0};
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uint64_t mcycle_csr{0};
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@ -134,7 +134,7 @@ protected:
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hart_state<reg_t> state;
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std::unordered_map<uint64_t, uint8_t> atomic_reservation;
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absl::flat_hash_map<uint64_t, uint8_t> atomic_reservation;
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iss::status read_status(unsigned addr, reg_t& val);
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iss::status write_status(unsigned addr, reg_t val);
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|
@ -48,9 +48,9 @@
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#ifndef FMT_HEADER_ONLY
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#define FMT_HEADER_ONLY
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#endif
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#include <fmt/format.h>
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#include <iss/mem/memory_with_htif.h>
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#include <iss/mem/mmu.h>
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#include <fmt/format.h>
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#include <type_traits>
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#include <unordered_map>
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@ -150,7 +150,7 @@ protected:
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hart_state<reg_t> state;
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std::unordered_map<uint64_t, uint8_t> atomic_reservation;
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absl::flat_hash_map<uint64_t, uint8_t> atomic_reservation;
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iss::status read_status(unsigned addr, reg_t& val);
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iss::status write_status(unsigned addr, reg_t val);
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|
@ -160,7 +160,7 @@ protected:
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hart_state<reg_t> state;
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std::unordered_map<uint64_t, uint8_t> atomic_reservation;
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absl::flat_hash_map<uint64_t, uint8_t> atomic_reservation;
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iss::status read_status(unsigned addr, reg_t& val);
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iss::status write_status(unsigned addr, reg_t val);
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|
@ -32,9 +32,9 @@
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* eyck@minres.com - initial implementation
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******************************************************************************/
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#include "memory_if.h"
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#include "iss/arch/riscv_hart_common.h"
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#include "iss/vm_types.h"
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#include "memory_if.h"
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#include <util/logging.h>
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namespace iss {
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@ -238,7 +238,7 @@ private:
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protected:
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reg_t satp;
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std::unordered_map<reg_t, uint64_t> ptw;
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absl::flat_hash_map<reg_t, uint64_t> ptw;
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std::array<vm_info, 2> vmt;
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std::array<address_type, 4> addr_mode;
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|
@ -35,7 +35,7 @@
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#ifndef _VM_AES_SBOX_H_
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#define _VM_AES_SBOX_H_
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#include <cstdint>
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extern "C" {
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const uint8_t AES_ENC_SBOX[] = {
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0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5, 0x30, 0x01, 0x67, 0x2B, 0xFE, 0xD7, 0xAB, 0x76, 0xCA, 0x82, 0xC9, 0x7D, 0xFA, 0x59,
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0x47, 0xF0, 0xAD, 0xD4, 0xA2, 0xAF, 0x9C, 0xA4, 0x72, 0xC0, 0xB7, 0xFD, 0x93, 0x26, 0x36, 0x3F, 0xF7, 0xCC, 0x34, 0xA5, 0xE5, 0xF1,
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@ -65,5 +65,6 @@ const uint8_t AES_DEC_SBOX[] = {
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0x93, 0xC9, 0x9C, 0xEF, 0xA0, 0xE0, 0x3B, 0x4D, 0xAE, 0x2A, 0xF5, 0xB0, 0xC8, 0xEB, 0xBB, 0x3C, 0x83, 0x53, 0x99, 0x61, 0x17, 0x2B,
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0x04, 0x7E, 0xBA, 0x77, 0xD6, 0x26, 0xE1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0C, 0x7D};
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uint8_t inline aes_sbox_inv(uint8_t index) { return AES_DEC_SBOX[index]; }
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}
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#endif /* _VM_AES_SBOX_H_ */
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|
@ -47,6 +47,22 @@
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#include <array>
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#include <iss/debugger/riscv_target_adapter.h>
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#ifndef _MSC_VER
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using int128_t = __int128;
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using uint128_t = unsigned __int128;
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namespace std {
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template <> struct make_unsigned<__int128> { typedef unsigned __int128 type; };
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template <> class __make_unsigned_selector<__int128 unsigned, false, false> {
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public:
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typedef unsigned __int128 __type;
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};
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template <> struct is_signed<int128_t> { static constexpr bool value = true; };
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template <> struct is_signed<uint128_t> { static constexpr bool value = false; };
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template <> struct is_unsigned<int128_t> { static constexpr bool value = false; };
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template <> struct is_unsigned<uint128_t> { static constexpr bool value = true; };
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} // namespace std
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#endif
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namespace iss {
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namespace asmjit {
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@ -112,6 +128,11 @@ protected:
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auto sign_mask = 1ULL<<(W-1);
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return (from & mask) | ((from & sign_mask) ? ~mask : 0);
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}
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inline void raise(uint16_t trap_id, uint16_t cause){
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auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id;
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this->core.reg.trap_state = trap_val;
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}
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|
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private:
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/****************************************************************************
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||||
@ -335,7 +356,6 @@ private:
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mov(cc, jh.next_pc, pc.val);
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gen_instr_prologue(jh);
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cc.comment("//behavior:");
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/*generate behavior*/
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if(rd>=static_cast<uint32_t>(traits::RFS)){
|
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gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
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@ -382,7 +402,6 @@ private:
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mov(cc, jh.next_pc, pc.val);
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gen_instr_prologue(jh);
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cc.comment("//behavior:");
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/*generate behavior*/
|
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if(rd>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -429,7 +448,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
mov(jh.cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(NO_JUMP));
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)){
|
||||
@ -488,7 +506,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
mov(jh.cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(NO_JUMP));
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
@ -561,7 +578,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
mov(jh.cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(NO_JUMP));
|
||||
if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
@ -625,7 +641,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
mov(jh.cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(NO_JUMP));
|
||||
if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
@ -689,7 +704,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
mov(jh.cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(NO_JUMP));
|
||||
if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
@ -755,7 +769,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
mov(jh.cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(NO_JUMP));
|
||||
if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
@ -821,7 +834,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
mov(jh.cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(NO_JUMP));
|
||||
if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
@ -885,7 +897,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
mov(jh.cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(NO_JUMP));
|
||||
if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
@ -949,7 +960,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -1003,7 +1013,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -1057,7 +1066,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -1111,7 +1119,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -1164,7 +1171,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -1217,7 +1223,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -1266,7 +1271,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -1315,7 +1319,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -1364,7 +1367,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -1414,7 +1416,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -1475,7 +1476,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -1535,7 +1535,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -1584,7 +1583,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -1633,7 +1631,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -1682,7 +1679,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -1731,7 +1727,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -1780,7 +1775,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -1831,7 +1825,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -1881,7 +1874,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -1931,7 +1923,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -1981,7 +1972,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -2043,7 +2033,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -2103,7 +2092,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -2152,7 +2140,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -2202,7 +2189,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -2254,7 +2240,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -2303,7 +2288,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -2354,7 +2338,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
gen_write_mem(jh, traits::FENCE, static_cast<uint32_t>(traits::fence), (uint8_t)pred<<4|succ, 4);
|
||||
auto returnValue = CONT;
|
||||
@ -2390,7 +2373,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
mov(jh.cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(NO_JUMP));
|
||||
gen_raise(jh, 0, 11);
|
||||
@ -2427,7 +2409,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
mov(jh.cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(NO_JUMP));
|
||||
gen_raise(jh, 0, 3);
|
||||
@ -2464,7 +2445,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
mov(jh.cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(NO_JUMP));
|
||||
gen_leave(jh, 3);
|
||||
@ -2501,11 +2481,9 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
InvokeNode* call_wait_5;
|
||||
jh.cc.comment("//call_wait");
|
||||
jh.cc.invoke(&call_wait_5, &wait, FuncSignature::build<void, uint32_t>());
|
||||
jh.cc.invoke(&call_wait_5, &wait, FuncSignature::build<void, uint32_t>());
|
||||
setArg(call_wait_5, 0, 1);
|
||||
auto returnValue = CONT;
|
||||
|
||||
@ -2544,7 +2522,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -2598,7 +2575,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -2652,7 +2628,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -2706,7 +2681,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -2756,7 +2730,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -2809,7 +2782,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -2862,7 +2834,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
gen_write_mem(jh, traits::FENCE, static_cast<uint32_t>(traits::fencei), imm, 4);
|
||||
auto returnValue = FLUSH;
|
||||
@ -2902,7 +2873,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -2955,7 +2925,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -3009,7 +2978,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -3062,7 +3030,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -3114,7 +3081,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -3203,7 +3169,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -3270,7 +3235,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -3363,7 +3327,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -3429,7 +3392,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(imm){
|
||||
mov(cc, get_ptr_for(jh, traits::X0+ rd+8),
|
||||
@ -3477,7 +3439,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
auto offs = gen_ext(cc,
|
||||
(gen_operation(cc, add, load_reg_from_mem(jh, traits::X0 + rs1+8), uimm)
|
||||
@ -3523,7 +3484,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
auto offs = gen_ext(cc,
|
||||
(gen_operation(cc, add, load_reg_from_mem(jh, traits::X0 + rs1+8), uimm)
|
||||
@ -3566,7 +3526,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -3613,7 +3572,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
auto returnValue = CONT;
|
||||
|
||||
@ -3650,7 +3608,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
mov(jh.cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(NO_JUMP));
|
||||
mov(cc, get_ptr_for(jh, traits::X0+ 1),
|
||||
@ -3694,7 +3651,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -3741,7 +3697,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(imm==0||rd>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -3785,7 +3740,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(nzimm){
|
||||
mov(cc, get_ptr_for(jh, traits::X0+ 2),
|
||||
@ -3830,7 +3784,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
auto returnValue = CONT;
|
||||
@ -3869,7 +3822,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
mov(cc, get_ptr_for(jh, traits::X0+ rs1+8),
|
||||
gen_operation(cc, shr, load_reg_from_mem(jh, traits::X0 + rs1+8), shamt)
|
||||
@ -3910,7 +3862,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(shamt){
|
||||
mov(cc, get_ptr_for(jh, traits::X0+ rs1+8),
|
||||
@ -3964,7 +3915,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
mov(cc, get_ptr_for(jh, traits::X0+ rs1+8),
|
||||
gen_ext(cc,
|
||||
@ -4006,7 +3956,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
mov(cc, get_ptr_for(jh, traits::X0+ rd+8),
|
||||
gen_ext(cc,
|
||||
@ -4048,7 +3997,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
mov(cc, get_ptr_for(jh, traits::X0+ rd+8),
|
||||
gen_operation(cc, bxor, load_reg_from_mem(jh, traits::X0 + rd+8), load_reg_from_mem(jh, traits::X0 + rs2+8))
|
||||
@ -4089,7 +4037,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
mov(cc, get_ptr_for(jh, traits::X0+ rd+8),
|
||||
gen_operation(cc, bor, load_reg_from_mem(jh, traits::X0 + rd+8), load_reg_from_mem(jh, traits::X0 + rs2+8))
|
||||
@ -4130,7 +4077,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
mov(cc, get_ptr_for(jh, traits::X0+ rd+8),
|
||||
gen_operation(cc, band, load_reg_from_mem(jh, traits::X0 + rd+8), load_reg_from_mem(jh, traits::X0 + rs2+8))
|
||||
@ -4170,7 +4116,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
mov(jh.cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(NO_JUMP));
|
||||
auto PC_val_v = (uint32_t)(PC+(int16_t)sext<12>(imm));
|
||||
@ -4212,7 +4157,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
mov(jh.cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(NO_JUMP));
|
||||
{
|
||||
@ -4263,7 +4207,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
mov(jh.cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(NO_JUMP));
|
||||
{
|
||||
@ -4314,7 +4257,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -4362,7 +4304,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)||rd==0){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -4412,7 +4353,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -4458,7 +4398,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
mov(jh.cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(NO_JUMP));
|
||||
if(rs1&&rs1<static_cast<uint32_t>(traits::RFS)){
|
||||
@ -4504,7 +4443,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
gen_raise(jh, 0, 2);
|
||||
auto returnValue = CONT;
|
||||
@ -4543,7 +4481,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rd>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -4591,7 +4528,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
mov(jh.cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(NO_JUMP));
|
||||
if(rs1>=static_cast<uint32_t>(traits::RFS)){
|
||||
@ -4640,7 +4576,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
gen_raise(jh, 0, 3);
|
||||
auto returnValue = CONT;
|
||||
@ -4679,7 +4614,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
if(rs2>=static_cast<uint32_t>(traits::RFS)){
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
@ -4724,7 +4658,6 @@ private:
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
gen_raise(jh, 0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
auto returnValue = CONT;
|
||||
@ -4756,7 +4689,6 @@ private:
|
||||
pc = pc + ((instr & 3) == 3 ? 4 : 2);
|
||||
mov(cc, jh.next_pc, pc.val);
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
gen_raise(jh, 0, 2);
|
||||
gen_sync(jh, POST_SYNC, instr_descr.size());
|
||||
gen_instr_epilogue(jh);
|
||||
@ -4802,24 +4734,25 @@ template <typename ARCH>
|
||||
void vm_impl<ARCH>::gen_instr_prologue(jit_holder& jh) {
|
||||
auto& cc = jh.cc;
|
||||
|
||||
cc.comment("//gen_instr_prologue");
|
||||
|
||||
x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE);
|
||||
mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
|
||||
mov(cc, get_ptr_for(jh, traits::PENDING_TRAP), current_trap_state);
|
||||
cc.comment("//Instruction prologue end");
|
||||
|
||||
}
|
||||
template <typename ARCH>
|
||||
void vm_impl<ARCH>::gen_instr_epilogue(jit_holder& jh) {
|
||||
auto& cc = jh.cc;
|
||||
|
||||
cc.comment("//gen_instr_epilogue");
|
||||
cc.comment("//Instruction epilogue begin");
|
||||
x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE);
|
||||
mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
|
||||
cmp(cc, current_trap_state, 0);
|
||||
cc.jne(jh.trap_entry);
|
||||
cc.inc(get_ptr_for(jh, traits::ICOUNT));
|
||||
cc.inc(get_ptr_for(jh, traits::CYCLE));
|
||||
cc.comment("//Instruction epilogue end");
|
||||
|
||||
}
|
||||
template <typename ARCH>
|
||||
void vm_impl<ARCH>::gen_block_prologue(jit_holder& jh){
|
||||
@ -4831,7 +4764,7 @@ void vm_impl<ARCH>::gen_block_prologue(jit_holder& jh){
|
||||
template <typename ARCH>
|
||||
void vm_impl<ARCH>::gen_block_epilogue(jit_holder& jh){
|
||||
x86::Compiler& cc = jh.cc;
|
||||
cc.comment("//gen_block_epilogue");
|
||||
cc.comment("//block epilogue begin");
|
||||
cc.ret(jh.next_pc);
|
||||
|
||||
cc.bind(jh.trap_entry);
|
||||
@ -4843,7 +4776,6 @@ void vm_impl<ARCH>::gen_block_epilogue(jit_holder& jh){
|
||||
x86::Gp current_pc = get_reg_for_Gp(cc, traits::PC);
|
||||
mov(cc, current_pc, get_ptr_for(jh, traits::PC));
|
||||
|
||||
cc.comment("//enter trap call;");
|
||||
InvokeNode* call_enter_trap;
|
||||
cc.invoke(&call_enter_trap, &enter_trap, FuncSignature::build<uint64_t, void*, uint64_t, uint64_t, uint64_t>());
|
||||
call_enter_trap->setArg(0, jh.arch_if_ptr);
|
||||
@ -4861,7 +4793,6 @@ void vm_impl<ARCH>::gen_block_epilogue(jit_holder& jh){
|
||||
template <typename ARCH>
|
||||
inline void vm_impl<ARCH>::gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause) {
|
||||
auto& cc = jh.cc;
|
||||
cc.comment("//gen_raise");
|
||||
auto tmp1 = get_reg_for(cc, traits::TRAP_STATE);
|
||||
mov(cc, tmp1, 0x80ULL << 24 | (cause << 16) | trap_id);
|
||||
mov(cc, get_ptr_for(jh, traits::TRAP_STATE), tmp1);
|
||||
|
@ -38,14 +38,17 @@
|
||||
#include <iss/iss.h>
|
||||
#include <iss/interp/vm_base.h>
|
||||
|
||||
#include <stdexcept>
|
||||
#include <unordered_map>
|
||||
#include <util/logging.h>
|
||||
#include <boost/coroutine2/all.hpp>
|
||||
#include <functional>
|
||||
#include <exception>
|
||||
#include <utility>
|
||||
#include <vector>
|
||||
#include <sstream>
|
||||
#include <iss/instruction_decoder.h>
|
||||
|
||||
#include <absl/container/flat_hash_map.h>
|
||||
|
||||
#ifndef FMT_HEADER_ONLY
|
||||
#define FMT_HEADER_ONLY
|
||||
@ -255,6 +258,11 @@ private:
|
||||
return iss::Err;
|
||||
return iss::Ok;
|
||||
}
|
||||
|
||||
struct translation_buffer {
|
||||
std::vector<std::tuple<opcode_e, uint64_t, uint32_t>> entries;
|
||||
} tb;
|
||||
absl::flat_hash_map<uint64_t, translation_buffer> tb_lut;
|
||||
};
|
||||
|
||||
template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
|
||||
@ -312,27 +320,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto& instr = this->core.reg.instruction;
|
||||
// we fetch at max 4 byte, alignment is 2
|
||||
auto *const data = reinterpret_cast<uint8_t*>(&instr);
|
||||
|
||||
while(!this->core.should_stop() &&
|
||||
!(is_icount_limit_enabled(cond) && icount >= count_limit) &&
|
||||
!(is_fcount_limit_enabled(cond) && fetch_count >= count_limit)){
|
||||
if(this->debugging_enabled())
|
||||
this->tgt_adapter->check_continue(*PC);
|
||||
pc.val=*PC;
|
||||
if(fetch_ins(pc, data)!=iss::Ok){
|
||||
if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());
|
||||
process_spawn_blocks();
|
||||
if(this->sync_exec && POST_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());
|
||||
pc.val = super::core.enter_trap(arch::traits<ARCH>::RV_CAUSE_FETCH_ACCESS<<16, pc.val, 0);
|
||||
} else {
|
||||
if (is_jump_to_self_enabled(cond) &&
|
||||
(instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
|
||||
uint32_t inst_index = instr_decoder.decode_instr(instr);
|
||||
opcode_e inst_id = arch::traits<ARCH>::opcode_e::MAX_OPCODE;;
|
||||
if(inst_index <instr_descr.size())
|
||||
inst_id = instr_descr[inst_index].op;
|
||||
|
||||
// pre execution stuff
|
||||
auto exec = [this, PC, NEXT_PC](opcode_e inst_id, uint64_t pc, uint32_t instr) {
|
||||
// pre execution stuff
|
||||
this->core.reg.last_branch = 0;
|
||||
if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
|
||||
try{
|
||||
@ -345,7 +334,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -372,7 +361,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -399,7 +388,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -436,7 +425,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -474,7 +463,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"),
|
||||
fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -510,7 +499,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"),
|
||||
fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -546,7 +535,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"),
|
||||
fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -582,7 +571,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"),
|
||||
fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -618,7 +607,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"),
|
||||
fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -654,7 +643,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"),
|
||||
fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -690,7 +679,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -722,7 +711,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -754,7 +743,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -786,7 +775,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -818,7 +807,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -850,7 +839,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"),
|
||||
fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -878,7 +867,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"),
|
||||
fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -906,7 +895,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"),
|
||||
fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -934,7 +923,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -962,7 +951,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -990,7 +979,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -1018,7 +1007,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -1046,7 +1035,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -1074,7 +1063,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -1102,7 +1091,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -1130,7 +1119,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -1158,7 +1147,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -1186,7 +1175,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -1214,7 +1203,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -1242,7 +1231,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -1270,7 +1259,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -1298,7 +1287,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -1326,7 +1315,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -1354,7 +1343,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -1382,7 +1371,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -1410,7 +1399,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -1438,7 +1427,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -1468,7 +1457,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {pred}, {succ} ({fm} , {rs1}, {rd})", fmt::arg("mnemonic", "fence"),
|
||||
fmt::arg("pred", pred), fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
// calculate next pc value
|
||||
@ -1485,7 +1474,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
/* generate console output when executing the command */
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = "ecall";
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
// calculate next pc value
|
||||
@ -1501,7 +1490,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
/* generate console output when executing the command */
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = "ebreak";
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
// calculate next pc value
|
||||
@ -1517,7 +1506,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
/* generate console output when executing the command */
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = "mret";
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
// calculate next pc value
|
||||
@ -1533,7 +1522,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
/* generate console output when executing the command */
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = "wfi";
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
// calculate next pc value
|
||||
@ -1553,7 +1542,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -1591,7 +1580,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -1627,7 +1616,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -1663,7 +1652,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -1696,7 +1685,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -1731,7 +1720,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -1766,7 +1755,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"),
|
||||
fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
// calculate next pc value
|
||||
@ -1787,7 +1776,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mul"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -1816,7 +1805,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulh"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -1845,7 +1834,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhsu"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -1874,7 +1863,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhu"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -1903,7 +1892,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "div"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -1944,7 +1933,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divu"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -1979,7 +1968,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "rem"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -2022,7 +2011,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remu"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -2056,7 +2045,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.addi4spn"),
|
||||
fmt::arg("rd", name(8+rd)), fmt::arg("imm", imm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -2082,7 +2071,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.lw"),
|
||||
fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -2106,7 +2095,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.sw"),
|
||||
fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -2128,7 +2117,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.addi"),
|
||||
fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -2153,7 +2142,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
/* generate console output when executing the command */
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = "c.nop";
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
// calculate next pc value
|
||||
@ -2170,7 +2159,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.jal"),
|
||||
fmt::arg("imm", imm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -2192,7 +2181,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.li"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -2219,7 +2208,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.lui"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -2243,7 +2232,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c.addi16sp"),
|
||||
fmt::arg("nzimm", nzimm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -2266,7 +2255,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
/* generate console output when executing the command */
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = ".reserved_clui";
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
// calculate next pc value
|
||||
@ -2285,7 +2274,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srli"),
|
||||
fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -2305,7 +2294,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srai"),
|
||||
fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -2332,7 +2321,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.andi"),
|
||||
fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -2352,7 +2341,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.sub"),
|
||||
fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -2372,7 +2361,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.xor"),
|
||||
fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -2392,7 +2381,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.or"),
|
||||
fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -2412,7 +2401,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.and"),
|
||||
fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -2431,7 +2420,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.j"),
|
||||
fmt::arg("imm", imm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
// calculate next pc value
|
||||
@ -2451,7 +2440,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.beqz"),
|
||||
fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -2474,7 +2463,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.bnez"),
|
||||
fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -2497,7 +2486,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c.slli"),
|
||||
fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -2524,7 +2513,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c.lwsp"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -2552,7 +2541,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.mv"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -2578,7 +2567,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jr"),
|
||||
fmt::arg("rs1", name(rs1)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -2602,7 +2591,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
/* generate console output when executing the command */
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = ".reserved_cmv";
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
// calculate next pc value
|
||||
@ -2621,7 +2610,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.add"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -2647,7 +2636,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jalr"),
|
||||
fmt::arg("rs1", name(rs1)));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -2673,7 +2662,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
/* generate console output when executing the command */
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = "c.ebreak";
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
// calculate next pc value
|
||||
@ -2692,7 +2681,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c.swsp"),
|
||||
fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
@ -2716,7 +2705,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
/* generate console output when executing the command */
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = "dii";
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
this->core.disass_output(pc, mnemonic);
|
||||
}
|
||||
// used registers
|
||||
// calculate next pc value
|
||||
@ -2739,16 +2728,54 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// if(!this->core.reg.trap_state) // update trap state if there is a pending interrupt
|
||||
// this->core.reg.trap_state = this->core.reg.pending_trap;
|
||||
// trap check
|
||||
if(trap_state!=0){
|
||||
if(this->core.reg.trap_state!=0){
|
||||
//In case of Instruction address misaligned (cause = 0 and trapid = 0) need the targeted addr (in tval)
|
||||
auto mcause = (trap_state>>16) & 0xff;
|
||||
super::core.enter_trap(trap_state, pc.val, mcause ? instr:tval);
|
||||
auto mcause = (this->core.reg.trap_state>>16) & 0xff;
|
||||
super::core.enter_trap(this->core.reg.trap_state, pc, mcause ? instr:tval);
|
||||
} else {
|
||||
icount++;
|
||||
instret++;
|
||||
this->core.reg.icount++;
|
||||
this->core.reg.instret++;
|
||||
}
|
||||
*PC = *NEXT_PC;
|
||||
this->core.reg.trap_state = this->core.reg.pending_trap;
|
||||
|
||||
};
|
||||
while(!this->core.should_stop() &&
|
||||
!(is_icount_limit_enabled(cond) && icount >= count_limit) &&
|
||||
!(is_fcount_limit_enabled(cond) && fetch_count >= count_limit)){
|
||||
if(this->debugging_enabled())
|
||||
this->tgt_adapter->check_continue(*PC);
|
||||
pc.val=*PC;
|
||||
auto current_tb = tb_lut.find(pc.val);
|
||||
if(current_tb==tb_lut.end()) {
|
||||
auto res = tb_lut.insert(std::make_pair(pc.val,translation_buffer{}));
|
||||
if(!res.second)
|
||||
throw std::runtime_error("");
|
||||
current_tb=res.first;
|
||||
do {
|
||||
if(fetch_ins(pc, data)!=iss::Ok){
|
||||
if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());
|
||||
process_spawn_blocks();
|
||||
if(this->sync_exec && POST_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());
|
||||
pc.val = super::core.enter_trap(arch::traits<ARCH>::RV_CAUSE_FETCH_ACCESS<<16, pc.val, 0);
|
||||
break;
|
||||
} else {
|
||||
if (is_jump_to_self_enabled(cond) &&
|
||||
(instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
|
||||
uint32_t inst_index = instr_decoder.decode_instr(instr);
|
||||
opcode_e inst_id = arch::traits<ARCH>::opcode_e::MAX_OPCODE;;
|
||||
if(inst_index <instr_descr.size())
|
||||
inst_id = instr_descr[inst_index].op;
|
||||
if(is_jump_to_self_enabled(cond) &&
|
||||
inst_id==arch::traits<ARCH>::opcode_e::JAL && !bit_sub<7, 25>(instr) ||
|
||||
inst_id == arch::traits<ARCH>::opcode_e::C__J && !bit_sub<2, 11>(instr))
|
||||
throw simulation_stopped(0);
|
||||
exec(inst_id, pc.val, instr);
|
||||
}
|
||||
} while(this->core.reg.last_branch==0);
|
||||
} else {
|
||||
for(auto& e:current_tb->second.entries)
|
||||
exec(std::get<0>(e), std::get<1>(e), std::get<2>(e));
|
||||
}
|
||||
fetch_count++;
|
||||
cycle++;
|
||||
|
@ -102,6 +102,7 @@ void add_fp_functions_2_module(Module* mod, uint32_t flen, uint32_t xlen) {
|
||||
FDECL(fmadd_s, INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
|
||||
FDECL(fsel_s, INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(32));
|
||||
FDECL(fclass_s, INT_TYPE(32), INT_TYPE(32));
|
||||
FDECL(unbox_s, INT_TYPE(32), INT_TYPE(32), INT_TYPE(64)); // technically the first arg is only 8 bits
|
||||
|
||||
FDECL(f32toi32, INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
|
||||
FDECL(f32toui32, INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
|
||||
@ -112,7 +113,6 @@ void add_fp_functions_2_module(Module* mod, uint32_t flen, uint32_t xlen) {
|
||||
FDECL(i64tof32, INT_TYPE(32), INT_TYPE(64), INT_TYPE(8));
|
||||
FDECL(ui64tof32, INT_TYPE(32), INT_TYPE(64), INT_TYPE(8));
|
||||
if(flen > 32) {
|
||||
FDECL(unbox_s, INT_TYPE(32), INT_TYPE(32), INT_TYPE(64)); // technically the first arg is only 8 bits
|
||||
|
||||
FDECL(fadd_d, INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
|
||||
FDECL(fsub_d, INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
|
||||
@ -134,6 +134,8 @@ void add_fp_functions_2_module(Module* mod, uint32_t flen, uint32_t xlen) {
|
||||
FDECL(ui32tof64, INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
|
||||
FDECL(f64toi32, INT_TYPE(32), INT_TYPE(64), INT_TYPE(8));
|
||||
FDECL(f64toui32, INT_TYPE(32), INT_TYPE(64), INT_TYPE(8));
|
||||
|
||||
FDECL(unbox_d, INT_TYPE(64), INT_TYPE(32), INT_TYPE(64)); // technically the first arg is only 8 bits
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -31,10 +31,12 @@
|
||||
*******************************************************************************/
|
||||
// clang-format off
|
||||
#include <iss/arch/tgc5c.h>
|
||||
// vm_base needs to be included before gdb_session as termios.h (via boost and gdb_server) has a define which clashes with a variable
|
||||
// name in ConstantRange.h
|
||||
#include <iss/llvm/vm_base.h>
|
||||
#include <iss/debugger/gdb_session.h>
|
||||
#include <iss/debugger/server.h>
|
||||
#include <iss/iss.h>
|
||||
#include <iss/llvm/vm_base.h>
|
||||
#include <util/logging.h>
|
||||
#include <iss/instruction_decoder.h>
|
||||
|
||||
|
Reference in New Issue
Block a user