Compare commits
4 Commits
ad60449073
...
75e81ce236
Author | SHA1 | Date | |
---|---|---|---|
75e81ce236 | |||
82a70efdb8 | |||
978c3db06e | |||
0e88664ff7 |
@ -354,7 +354,7 @@ protected:
|
|||||||
using csr_page_type = typename csr_type::page_type;
|
using csr_page_type = typename csr_type::page_type;
|
||||||
mem_type mem;
|
mem_type mem;
|
||||||
csr_type csr;
|
csr_type csr;
|
||||||
std::stringstream uart_buf;
|
std::stringstream io_buf;
|
||||||
std::unordered_map<reg_t, uint64_t> ptw;
|
std::unordered_map<reg_t, uint64_t> ptw;
|
||||||
std::unordered_map<uint64_t, uint8_t> atomic_reservation;
|
std::unordered_map<uint64_t, uint8_t> atomic_reservation;
|
||||||
std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
|
std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
|
||||||
@ -446,7 +446,7 @@ riscv_hart_m_p<BASE, FEAT, LOGCAT>::riscv_hart_m_p(feature_config cfg)
|
|||||||
csr[marchid] = traits<BASE>::MARCHID_VAL;
|
csr[marchid] = traits<BASE>::MARCHID_VAL;
|
||||||
csr[mimpid] = 1;
|
csr[mimpid] = 1;
|
||||||
|
|
||||||
uart_buf.str("");
|
io_buf.str("");
|
||||||
if(traits<BASE>::FLEN > 0) {
|
if(traits<BASE>::FLEN > 0) {
|
||||||
csr_rd_cb[fcsr] = &this_class::read_fcsr;
|
csr_rd_cb[fcsr] = &this_class::read_fcsr;
|
||||||
csr_wr_cb[fcsr] = &this_class::write_fcsr;
|
csr_wr_cb[fcsr] = &this_class::write_fcsr;
|
||||||
@ -720,7 +720,7 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write(const address_type type, c
|
|||||||
return iss::Err;
|
return iss::Err;
|
||||||
}
|
}
|
||||||
try {
|
try {
|
||||||
if(length > 1 && (addr & (length - 1)) && (access & access_type::DEBUG) != access_type::DEBUG) {
|
if(length > 1 && (addr & (length - 1)) && !is_debug(access)) {
|
||||||
this->reg.trap_state = (1UL << 31) | 6 << 16;
|
this->reg.trap_state = (1UL << 31) | 6 << 16;
|
||||||
fault_data = addr;
|
fault_data = addr;
|
||||||
return iss::Err;
|
return iss::Err;
|
||||||
@ -740,7 +740,7 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write(const address_type type, c
|
|||||||
} else {
|
} else {
|
||||||
res = write_mem(phys_addr, length, data);
|
res = write_mem(phys_addr, length, data);
|
||||||
}
|
}
|
||||||
if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
|
if(unlikely(res != iss::Ok && !is_debug(access))) {
|
||||||
this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault)
|
this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault)
|
||||||
fault_data = addr;
|
fault_data = addr;
|
||||||
}
|
}
|
||||||
@ -756,10 +756,10 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write(const address_type type, c
|
|||||||
switch(addr) {
|
switch(addr) {
|
||||||
case 0x10013000: // UART0 base, TXFIFO reg
|
case 0x10013000: // UART0 base, TXFIFO reg
|
||||||
case 0x10023000: // UART1 base, TXFIFO reg
|
case 0x10023000: // UART1 base, TXFIFO reg
|
||||||
uart_buf << (char)data[0];
|
io_buf << (char)data[0];
|
||||||
if(((char)data[0]) == '\n' || data[0] == 0) {
|
if(((char)data[0]) == '\n' || data[0] == 0) {
|
||||||
std::cout << uart_buf.str();
|
std::cout << io_buf.str();
|
||||||
uart_buf.str("");
|
io_buf.str("");
|
||||||
}
|
}
|
||||||
return iss::Ok;
|
return iss::Ok;
|
||||||
case 0x10008000: { // HFROSC base, hfrosccfg reg
|
case 0x10008000: { // HFROSC base, hfrosccfg reg
|
||||||
@ -1094,59 +1094,79 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read_mem(phys_addr_t paddr, unsi
|
|||||||
|
|
||||||
template <typename BASE, features_e FEAT, typename LOGCAT>
|
template <typename BASE, features_e FEAT, typename LOGCAT>
|
||||||
iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) {
|
iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) {
|
||||||
switch(paddr.val) {
|
mem_type::page_type& p = mem(paddr.val / mem.page_size);
|
||||||
// TODO remove UART, Peripherals should not be part of the ISS
|
std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
|
||||||
case 0xFFFF0000: // UART0 base, TXFIFO reg
|
// tohost handling in case of riscv-test
|
||||||
if(((char)data[0]) == '\n' || data[0] == 0) {
|
// according to https://github.com/riscv-software-src/riscv-isa-sim/issues/364#issuecomment-607657754:
|
||||||
CPPLOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'";
|
if(paddr.access && iss::access_type::FUNC) {
|
||||||
uart_buf.str("");
|
if(paddr.val == tohost) {
|
||||||
} else if(((char)data[0]) != '\r')
|
if(traits<BASE>::XLEN == 32)
|
||||||
uart_buf << (char)data[0];
|
tohost &= 0x00000000ffffffff;
|
||||||
break;
|
// Extract Device (bits 63:56)
|
||||||
default: {
|
uint8_t device = (tohost >> 56) & 0xFF;
|
||||||
mem_type::page_type& p = mem(paddr.val / mem.page_size);
|
// Extract Command (bits 55:48)
|
||||||
std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
|
uint8_t command = (tohost >> 48) & 0xFF;
|
||||||
// tohost handling in case of riscv-test
|
// Extract payload (bits 47:0)
|
||||||
if(paddr.access && iss::access_type::FUNC) {
|
uint64_t payload = tohost & 0xFFFFFFFFFFFFULL;
|
||||||
auto tohost_upper =
|
if(payload & 1) {
|
||||||
(traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4)) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
|
CPPLOG(FATAL) << "tohost value is 0x" << std::hex << payload << std::dec << " (" << payload << "), stopping simulation";
|
||||||
auto tohost_lower = (traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
|
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
|
||||||
if(tohost_lower || tohost_upper) {
|
this->interrupt_sim = payload;
|
||||||
uint64_t hostvar = *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask));
|
return iss::Ok;
|
||||||
// in case of 32 bit system, two writes to tohost are needed, only evaluate on the second (high) write
|
} else if(device == 0 && command == 0) {
|
||||||
if(tohost_upper && (tohost_lower || tohost_lower_written)) {
|
reg_t payload_addr;
|
||||||
switch(hostvar >> 48) {
|
// payload contains the addr of the struct containing information about the syscall
|
||||||
case 0:
|
read(address_type::PHYSICAL, access_type::READ, traits<BASE>::MEM, payload, sizeof(reg_t),
|
||||||
if(hostvar != 0x1) {
|
reinterpret_cast<uint8_t*>(&payload_addr));
|
||||||
CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
|
// If the payload_addr is missaligned end simulation
|
||||||
<< "), stopping simulation";
|
if(payload_addr & 1) {
|
||||||
} else {
|
CPPLOG(FATAL) << "tohost payload value is 0x" << std::hex << payload_addr << std::dec << " (" << payload_addr
|
||||||
CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
|
<< "), stopping simulation";
|
||||||
<< "), stopping simulation";
|
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
|
||||||
}
|
this->interrupt_sim = payload;
|
||||||
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
|
return iss::Ok;
|
||||||
this->interrupt_sim = hostvar;
|
}
|
||||||
break;
|
// read the entire struct into an array
|
||||||
case 0x0101: {
|
reg_t loaded_payload[8];
|
||||||
char c = static_cast<char>(hostvar & 0xff);
|
read(address_type::PHYSICAL, access_type::READ, traits<BASE>::MEM, payload_addr, sizeof(loaded_payload),
|
||||||
if(c == '\n' || c == 0) {
|
reinterpret_cast<uint8_t*>(loaded_payload));
|
||||||
CPPLOG(INFO) << "tohost send '" << uart_buf.str() << "'";
|
reg_t syscall_num = loaded_payload[0];
|
||||||
uart_buf.str("");
|
if(syscall_num == 64) { // SYS_WRITE
|
||||||
|
reg_t fd = loaded_payload[1];
|
||||||
|
reg_t buf_ptr = loaded_payload[2];
|
||||||
|
reg_t len = loaded_payload[3];
|
||||||
|
std::vector<char> buf(len);
|
||||||
|
read(address_type::PHYSICAL, access_type::READ, traits<BASE>::MEM, buf_ptr, len,
|
||||||
|
reinterpret_cast<uint8_t*>(buf.data()));
|
||||||
|
// we disregard the fd and just log to stdout
|
||||||
|
for(size_t i = 0; i < len; i++) {
|
||||||
|
if(buf[i] == '\n') {
|
||||||
|
CPPLOG(INFO) << "tohost send '" << io_buf.str() << "'";
|
||||||
|
io_buf.str("");
|
||||||
} else
|
} else
|
||||||
uart_buf << c;
|
io_buf << buf[i];
|
||||||
} break;
|
|
||||||
default:
|
|
||||||
break;
|
|
||||||
}
|
}
|
||||||
tohost_lower_written = false;
|
// Not sure what the correct return value should be
|
||||||
} else if(tohost_lower)
|
uint8_t ret_val = 1;
|
||||||
tohost_lower_written = true;
|
write(address_type::PHYSICAL, access_type::WRITE, traits<BASE>::MEM, fromhost, 1, &ret_val);
|
||||||
} else if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
|
} else {
|
||||||
uint64_t fhostvar = *reinterpret_cast<uint64_t*>(p.data() + (fromhost & mem.page_addr_mask));
|
CPPLOG(ERR) << "tohost syscall with number " << std::hex << syscall_num << std::dec << " (" << syscall_num
|
||||||
*reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
|
<< ") not implemented";
|
||||||
|
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
|
||||||
|
this->interrupt_sim = payload;
|
||||||
|
return iss::Ok;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
CPPLOG(ERR) << "tohost functionality not implemented for device " << device << " and command " << command;
|
||||||
|
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
|
||||||
|
this->interrupt_sim = payload;
|
||||||
|
return iss::Ok;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
|
||||||
|
uint64_t fhostvar = *reinterpret_cast<uint64_t*>(p.data() + (fromhost & mem.page_addr_mask));
|
||||||
|
*reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
return iss::Ok;
|
return iss::Ok;
|
||||||
}
|
}
|
||||||
|
@ -404,7 +404,7 @@ protected:
|
|||||||
mem_type mem;
|
mem_type mem;
|
||||||
csr_type csr;
|
csr_type csr;
|
||||||
void update_vm_info();
|
void update_vm_info();
|
||||||
std::stringstream uart_buf;
|
std::stringstream io_buf;
|
||||||
std::unordered_map<reg_t, uint64_t> ptw;
|
std::unordered_map<reg_t, uint64_t> ptw;
|
||||||
std::unordered_map<uint64_t, uint8_t> atomic_reservation;
|
std::unordered_map<uint64_t, uint8_t> atomic_reservation;
|
||||||
std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
|
std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
|
||||||
@ -459,7 +459,7 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
|
|||||||
csr[marchid] = traits<BASE>::MARCHID_VAL;
|
csr[marchid] = traits<BASE>::MARCHID_VAL;
|
||||||
csr[mimpid] = 1;
|
csr[mimpid] = 1;
|
||||||
|
|
||||||
uart_buf.str("");
|
io_buf.str("");
|
||||||
for(unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr) {
|
for(unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr) {
|
||||||
csr_rd_cb[addr] = &this_class::read_null;
|
csr_rd_cb[addr] = &this_class::read_null;
|
||||||
csr_wr_cb[addr] = &this_class::write_csr_reg;
|
csr_wr_cb[addr] = &this_class::write_csr_reg;
|
||||||
@ -727,12 +727,12 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
|
|||||||
switch(paddr.val) {
|
switch(paddr.val) {
|
||||||
case 0x10013000: // UART0 base, TXFIFO reg
|
case 0x10013000: // UART0 base, TXFIFO reg
|
||||||
case 0x10023000: // UART1 base, TXFIFO reg
|
case 0x10023000: // UART1 base, TXFIFO reg
|
||||||
uart_buf << (char)data[0];
|
io_buf << (char)data[0];
|
||||||
if(((char)data[0]) == '\n' || data[0] == 0) {
|
if(((char)data[0]) == '\n' || data[0] == 0) {
|
||||||
// CPPLOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
|
// CPPLOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
|
||||||
// '"<<uart_buf.str()<<"'";
|
// '"<<io_buf.str()<<"'";
|
||||||
std::cout << uart_buf.str();
|
std::cout << io_buf.str();
|
||||||
uart_buf.str("");
|
io_buf.str("");
|
||||||
}
|
}
|
||||||
return iss::Ok;
|
return iss::Ok;
|
||||||
case 0x10008000: { // HFROSC base, hfrosccfg reg
|
case 0x10008000: { // HFROSC base, hfrosccfg reg
|
||||||
@ -1024,61 +1024,79 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_mem(phys_addr
|
|||||||
}
|
}
|
||||||
|
|
||||||
template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) {
|
template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) {
|
||||||
switch(paddr.val) {
|
mem_type::page_type& p = mem(paddr.val / mem.page_size);
|
||||||
case 0xFFFF0000: // UART0 base, TXFIFO reg
|
std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
|
||||||
if(((char)data[0]) == '\n' || data[0] == 0) {
|
// tohost handling in case of riscv-test
|
||||||
CPPLOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'";
|
// according to https://github.com/riscv-software-src/riscv-isa-sim/issues/364#issuecomment-607657754:
|
||||||
uart_buf.str("");
|
if(paddr.access && iss::access_type::FUNC) {
|
||||||
} else if(((char)data[0]) != '\r')
|
if(paddr.val == tohost) {
|
||||||
uart_buf << (char)data[0];
|
if(traits<BASE>::XLEN == 32)
|
||||||
break;
|
tohost &= 0x00000000ffffffff;
|
||||||
default: {
|
// Extract Device (bits 63:56)
|
||||||
mem_type::page_type& p = mem(paddr.val / mem.page_size);
|
uint8_t device = (tohost >> 56) & 0xFF;
|
||||||
std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
|
// Extract Command (bits 55:48)
|
||||||
// tohost handling in case of riscv-test
|
uint8_t command = (tohost >> 48) & 0xFF;
|
||||||
if(paddr.access && iss::access_type::FUNC) {
|
// Extract payload (bits 47:0)
|
||||||
auto tohost_upper =
|
uint64_t payload = tohost & 0xFFFFFFFFFFFFULL;
|
||||||
(traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4)) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
|
if(payload & 1) {
|
||||||
auto tohost_lower = (traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
|
CPPLOG(FATAL) << "tohost value is 0x" << std::hex << payload << std::dec << " (" << payload << "), stopping simulation";
|
||||||
if(tohost_lower || tohost_upper) {
|
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
|
||||||
uint64_t hostvar = *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask));
|
this->interrupt_sim = payload;
|
||||||
// in case of 32 bit system, two writes to tohost are needed, only evaluate on the second (high) write
|
return iss::Ok;
|
||||||
if(tohost_upper && (tohost_lower || tohost_lower_written)) {
|
} else if(device == 0 && command == 0) {
|
||||||
switch(hostvar >> 48) {
|
reg_t payload_addr;
|
||||||
case 0:
|
// payload contains the addr of the struct containing information about the syscall
|
||||||
if(hostvar != 0x1) {
|
read(address_type::PHYSICAL, access_type::READ, traits<BASE>::MEM, payload, sizeof(reg_t),
|
||||||
CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
|
reinterpret_cast<uint8_t*>(&payload_addr));
|
||||||
<< "), stopping simulation";
|
// If the payload_addr is missaligned end simulation
|
||||||
} else {
|
if(payload_addr & 1) {
|
||||||
CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
|
CPPLOG(FATAL) << "tohost payload value is 0x" << std::hex << payload_addr << std::dec << " (" << payload_addr
|
||||||
<< "), stopping simulation";
|
<< "), stopping simulation";
|
||||||
}
|
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
|
||||||
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
|
this->interrupt_sim = payload;
|
||||||
this->interrupt_sim = hostvar;
|
return iss::Ok;
|
||||||
#ifndef WITH_TCC
|
}
|
||||||
throw(iss::simulation_stopped(hostvar));
|
// read the entire struct into an array
|
||||||
#endif
|
reg_t loaded_payload[8];
|
||||||
break;
|
read(address_type::PHYSICAL, access_type::READ, traits<BASE>::MEM, payload_addr, sizeof(loaded_payload),
|
||||||
case 0x0101: {
|
reinterpret_cast<uint8_t*>(loaded_payload));
|
||||||
char c = static_cast<char>(hostvar & 0xff);
|
reg_t syscall_num = loaded_payload[0];
|
||||||
if(c == '\n' || c == 0) {
|
if(syscall_num == 64) { // SYS_WRITE
|
||||||
CPPLOG(INFO) << "tohost send '" << uart_buf.str() << "'";
|
reg_t fd = loaded_payload[1];
|
||||||
uart_buf.str("");
|
reg_t buf_ptr = loaded_payload[2];
|
||||||
|
reg_t len = loaded_payload[3];
|
||||||
|
std::vector<char> buf(len);
|
||||||
|
read(address_type::PHYSICAL, access_type::READ, traits<BASE>::MEM, buf_ptr, len,
|
||||||
|
reinterpret_cast<uint8_t*>(buf.data()));
|
||||||
|
// we disregard the fd and just log to stdout
|
||||||
|
for(size_t i = 0; i < len; i++) {
|
||||||
|
if(buf[i] == '\n') {
|
||||||
|
CPPLOG(INFO) << "tohost send '" << io_buf.str() << "'";
|
||||||
|
io_buf.str("");
|
||||||
} else
|
} else
|
||||||
uart_buf << c;
|
io_buf << buf[i];
|
||||||
} break;
|
|
||||||
default:
|
|
||||||
break;
|
|
||||||
}
|
}
|
||||||
tohost_lower_written = false;
|
// Not sure what the correct return value should be
|
||||||
} else if(tohost_lower)
|
uint8_t ret_val = 1;
|
||||||
tohost_lower_written = true;
|
write(address_type::PHYSICAL, access_type::WRITE, traits<BASE>::MEM, fromhost, 1, &ret_val);
|
||||||
} else if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
|
} else {
|
||||||
uint64_t fhostvar = *reinterpret_cast<uint64_t*>(p.data() + (fromhost & mem.page_addr_mask));
|
CPPLOG(ERR) << "tohost syscall with number " << std::hex << syscall_num << std::dec << " (" << syscall_num
|
||||||
*reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
|
<< ") not implemented";
|
||||||
|
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
|
||||||
|
this->interrupt_sim = payload;
|
||||||
|
return iss::Ok;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
CPPLOG(ERR) << "tohost functionality not implemented for device " << device << " and command " << command;
|
||||||
|
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
|
||||||
|
this->interrupt_sim = payload;
|
||||||
|
return iss::Ok;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
|
||||||
|
uint64_t fhostvar = *reinterpret_cast<uint64_t*>(p.data() + (fromhost & mem.page_addr_mask));
|
||||||
|
*reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
return iss::Ok;
|
return iss::Ok;
|
||||||
}
|
}
|
||||||
|
@ -380,7 +380,7 @@ protected:
|
|||||||
using csr_page_type = typename csr_type::page_type;
|
using csr_page_type = typename csr_type::page_type;
|
||||||
mem_type mem;
|
mem_type mem;
|
||||||
csr_type csr;
|
csr_type csr;
|
||||||
std::stringstream uart_buf;
|
std::stringstream io_buf;
|
||||||
std::unordered_map<reg_t, uint64_t> ptw;
|
std::unordered_map<reg_t, uint64_t> ptw;
|
||||||
std::unordered_map<uint64_t, uint8_t> atomic_reservation;
|
std::unordered_map<uint64_t, uint8_t> atomic_reservation;
|
||||||
std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
|
std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
|
||||||
@ -475,7 +475,7 @@ riscv_hart_mu_p<BASE, FEAT, LOGCAT>::riscv_hart_mu_p(feature_config cfg)
|
|||||||
csr[marchid] = traits<BASE>::MARCHID_VAL;
|
csr[marchid] = traits<BASE>::MARCHID_VAL;
|
||||||
csr[mimpid] = 1;
|
csr[mimpid] = 1;
|
||||||
|
|
||||||
uart_buf.str("");
|
io_buf.str("");
|
||||||
if(traits<BASE>::FLEN > 0) {
|
if(traits<BASE>::FLEN > 0) {
|
||||||
csr_rd_cb[fcsr] = &this_class::read_fcsr;
|
csr_rd_cb[fcsr] = &this_class::read_fcsr;
|
||||||
csr_wr_cb[fcsr] = &this_class::write_fcsr;
|
csr_wr_cb[fcsr] = &this_class::write_fcsr;
|
||||||
@ -938,10 +938,10 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::write(const address_type type,
|
|||||||
switch(addr) {
|
switch(addr) {
|
||||||
case 0x10013000: // UART0 base, TXFIFO reg
|
case 0x10013000: // UART0 base, TXFIFO reg
|
||||||
case 0x10023000: // UART1 base, TXFIFO reg
|
case 0x10023000: // UART1 base, TXFIFO reg
|
||||||
uart_buf << (char)data[0];
|
io_buf << (char)data[0];
|
||||||
if(((char)data[0]) == '\n' || data[0] == 0) {
|
if(((char)data[0]) == '\n' || data[0] == 0) {
|
||||||
std::cout << uart_buf.str();
|
std::cout << io_buf.str();
|
||||||
uart_buf.str("");
|
io_buf.str("");
|
||||||
}
|
}
|
||||||
return iss::Ok;
|
return iss::Ok;
|
||||||
case 0x10008000: { // HFROSC base, hfrosccfg reg
|
case 0x10008000: { // HFROSC base, hfrosccfg reg
|
||||||
@ -1312,65 +1312,81 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::read_mem(phys_addr_t paddr, uns
|
|||||||
}
|
}
|
||||||
return iss::Ok;
|
return iss::Ok;
|
||||||
}
|
}
|
||||||
|
|
||||||
template <typename BASE, features_e FEAT, typename LOGCAT>
|
template <typename BASE, features_e FEAT, typename LOGCAT>
|
||||||
iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) {
|
iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) {
|
||||||
switch(paddr.val) {
|
mem_type::page_type& p = mem(paddr.val / mem.page_size);
|
||||||
// TODO remove UART, Peripherals should not be part of the ISS
|
std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
|
||||||
case 0xFFFF0000: // UART0 base, TXFIFO reg
|
// tohost handling in case of riscv-test
|
||||||
if(((char)data[0]) == '\n' || data[0] == 0) {
|
// according to https://github.com/riscv-software-src/riscv-isa-sim/issues/364#issuecomment-607657754:
|
||||||
CPPLOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'";
|
if(paddr.access && iss::access_type::FUNC) {
|
||||||
uart_buf.str("");
|
if(paddr.val == tohost) {
|
||||||
} else if(((char)data[0]) != '\r')
|
if(traits<BASE>::XLEN == 32)
|
||||||
uart_buf << (char)data[0];
|
tohost &= 0x00000000ffffffff;
|
||||||
break;
|
// Extract Device (bits 63:56)
|
||||||
default: {
|
uint8_t device = (tohost >> 56) & 0xFF;
|
||||||
mem_type::page_type& p = mem(paddr.val / mem.page_size);
|
// Extract Command (bits 55:48)
|
||||||
std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
|
uint8_t command = (tohost >> 48) & 0xFF;
|
||||||
// tohost handling in case of riscv-test
|
// Extract payload (bits 47:0)
|
||||||
if(paddr.access && iss::access_type::FUNC) {
|
uint64_t payload = tohost & 0xFFFFFFFFFFFFULL;
|
||||||
auto tohost_upper =
|
if(payload & 1) {
|
||||||
(traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4)) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
|
CPPLOG(FATAL) << "tohost value is 0x" << std::hex << payload << std::dec << " (" << payload << "), stopping simulation";
|
||||||
auto tohost_lower = (traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
|
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
|
||||||
if(tohost_lower || tohost_upper) {
|
this->interrupt_sim = payload;
|
||||||
uint64_t hostvar = *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask));
|
return iss::Ok;
|
||||||
// in case of 32 bit system, two writes to tohost are needed, only evaluate on the second (high) write
|
} else if(device == 0 && command == 0) {
|
||||||
if(tohost_upper && (tohost_lower || tohost_lower_written)) {
|
reg_t payload_addr;
|
||||||
switch(hostvar >> 48) {
|
// payload contains the addr of the struct containing information about the syscall
|
||||||
case 0:
|
read(address_type::PHYSICAL, access_type::READ, traits<BASE>::MEM, payload, sizeof(reg_t),
|
||||||
if(hostvar != 0x1) {
|
reinterpret_cast<uint8_t*>(&payload_addr));
|
||||||
CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
|
// If the payload_addr is missaligned end simulation
|
||||||
<< "), stopping simulation";
|
if(payload_addr & 1) {
|
||||||
} else {
|
CPPLOG(FATAL) << "tohost payload value is 0x" << std::hex << payload_addr << std::dec << " (" << payload_addr
|
||||||
CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
|
<< "), stopping simulation";
|
||||||
<< "), stopping simulation";
|
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
|
||||||
}
|
this->interrupt_sim = payload;
|
||||||
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
|
return iss::Ok;
|
||||||
this->interrupt_sim = hostvar;
|
}
|
||||||
#ifndef WITH_TCC
|
// read the entire struct into an array
|
||||||
throw(iss::simulation_stopped(hostvar));
|
reg_t loaded_payload[8];
|
||||||
#endif
|
read(address_type::PHYSICAL, access_type::READ, traits<BASE>::MEM, payload_addr, sizeof(loaded_payload),
|
||||||
break;
|
reinterpret_cast<uint8_t*>(loaded_payload));
|
||||||
case 0x0101: {
|
reg_t syscall_num = loaded_payload[0];
|
||||||
char c = static_cast<char>(hostvar & 0xff);
|
if(syscall_num == 64) { // SYS_WRITE
|
||||||
if(c == '\n' || c == 0) {
|
reg_t fd = loaded_payload[1];
|
||||||
CPPLOG(INFO) << "tohost send '" << uart_buf.str() << "'";
|
reg_t buf_ptr = loaded_payload[2];
|
||||||
uart_buf.str("");
|
reg_t len = loaded_payload[3];
|
||||||
|
std::vector<char> buf(len);
|
||||||
|
read(address_type::PHYSICAL, access_type::READ, traits<BASE>::MEM, buf_ptr, len,
|
||||||
|
reinterpret_cast<uint8_t*>(buf.data()));
|
||||||
|
// we disregard the fd and just log to stdout
|
||||||
|
for(size_t i = 0; i < len; i++) {
|
||||||
|
if(buf[i] == '\n') {
|
||||||
|
CPPLOG(INFO) << "tohost send '" << io_buf.str() << "'";
|
||||||
|
io_buf.str("");
|
||||||
} else
|
} else
|
||||||
uart_buf << c;
|
io_buf << buf[i];
|
||||||
} break;
|
|
||||||
default:
|
|
||||||
break;
|
|
||||||
}
|
}
|
||||||
tohost_lower_written = false;
|
// Not sure what the correct return value should be
|
||||||
} else if(tohost_lower)
|
uint8_t ret_val = 1;
|
||||||
tohost_lower_written = true;
|
write(address_type::PHYSICAL, access_type::WRITE, traits<BASE>::MEM, fromhost, 1, &ret_val);
|
||||||
} else if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
|
} else {
|
||||||
uint64_t fhostvar = *reinterpret_cast<uint64_t*>(p.data() + (fromhost & mem.page_addr_mask));
|
CPPLOG(ERR) << "tohost syscall with number " << std::hex << syscall_num << std::dec << " (" << syscall_num
|
||||||
*reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
|
<< ") not implemented";
|
||||||
|
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
|
||||||
|
this->interrupt_sim = payload;
|
||||||
|
return iss::Ok;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
CPPLOG(ERR) << "tohost functionality not implemented for device " << device << " and command " << command;
|
||||||
|
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
|
||||||
|
this->interrupt_sim = payload;
|
||||||
|
return iss::Ok;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
|
||||||
|
uint64_t fhostvar = *reinterpret_cast<uint64_t*>(p.data() + (fromhost & mem.page_addr_mask));
|
||||||
|
*reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
return iss::Ok;
|
return iss::Ok;
|
||||||
}
|
}
|
||||||
|
Loading…
Reference in New Issue
Block a user