DBT-RISE/DBT-RISE-TGC
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base: DBT-RISE:a6691bcd3c041c0f336105805acb302a2a3bcab2
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DBT-RISE:main DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter
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compare: DBT-RISE:ac8eab6e255561e071a643360f7552af6ff9a369
Branches Tags
DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:main DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter

3 Commits
a6691bcd3c ... ac8eab6e25

Author SHA1 Message Date
Eyck Jentzsch
ac8eab6e25 update RISC-V desciptions 2021-03-10 17:31:10 +00:00
Eyck Jentzsch
768716b064 fix another missing XLEN 2021-03-09 11:07:56 +00:00
Eyck Jentzsch
bea0dcc387 update missing XLEN 2021-03-09 11:03:37 +00:00
2 changed files with 3 additions and 3 deletions
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2
gen_input/CoreDSL-Instruction-Set-Description

Submodule gen_input/CoreDSL-Instruction-Set-Description updated: e7f694c726...8f72c66a57

4
src/vm/interp/vm_tgf_c.cpp
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@ -3148,7 +3148,7 @@ private:
*NEXT_PC = *PC + 2; *NEXT_PC = *PC + 2;
// execute instruction // execute instruction
if(rd) { if(rd) {
uint8_t offs = *(X+2) + uimm; uint32_t offs = *(X+2) + uimm;
*(X+rd) = (int32_t)readSpace4(traits::MEM, offs); *(X+rd) = (int32_t)readSpace4(traits::MEM, offs);
} }
else raise(0, 2); else raise(0, 2);
@ -3341,7 +3341,7 @@ private:
*NEXT_PC = *PC + 2; *NEXT_PC = *PC + 2;
// execute instruction // execute instruction
{ {
uint8_t offs = *(X+2) + uimm; uint32_t offs = *(X+2) + uimm;
writeSpace4(traits::MEM, offs, (uint32_t)*(X+rs2)); writeSpace4(traits::MEM, offs, (uint32_t)*(X+rs2));
} }
// post execution stuff // post execution stuff