scc update: scv4tlm -> scv

CMakeLists.txt

@@ -1,6 +1,6 @@
 cmake_minimum_required(VERSION 3.12)
 
-project(tgc VERSION 1.0.0)
+project("riscv" VERSION 1.0.0)
 
 include(GNUInstallDirs)
 
@@ -28,81 +28,77 @@ add_subdirectory(softfloat)
 
 # library files
 FILE(GLOB RiscVSCHeaders ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/*.h ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/*/*.h)
-set(LIB_HEADERS tgfscVSCHeaders} )
+set(LIB_HEADERS ${RiscVSCHeaders} )
 set(LIB_SOURCES 
+	src/iss/tgf_b.cpp
+	src/iss/tgf_c.cpp
 	src/vm/fp_functions.cpp
+	src/vm/tcc/vm_tgf_b.cpp
+	src/vm/tcc/vm_tgf_c.cpp
+	src/vm/interp/vm_tgf_b.cpp
+	src/vm/interp/vm_tgf_c.cpp
     src/plugin/instruction_count.cpp
     src/plugin/cycle_estimate.cpp
 )
-if(EXISTS src/iss/tgf_b.cpp)
-    set(LIB_SOURCES ${LIB_SOURCES}  src/iss/tgf_b.cpp src/vm/interp/vm_tgf_b.cpp)
-endif()
-if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/src/iss/tgf_c.cpp)
-    set(LIB_SOURCES ${LIB_SOURCES}  src/iss/tgf_c.cpp src/vm/interp/vm_tgf_c.cpp)
-endif()
 if(WITH_LLVM)
 set(LIB_SOURCES ${LIB_SOURCES}
 	src/vm/llvm/fp_impl.cpp
-#	src/vm/llvm/vm_tgf_b.cpp
+	src/vm/llvm/vm_tgf_b.cpp
-#	src/vm/llvm/vm_tgf_c.cpp
+	src/vm/llvm/vm_tgf_c.cpp
 )
 endif()
 
 # Define the library
-add_library(${PROJECT_NAME} SHARED ${LIB_SOURCES})
+add_library(riscv SHARED ${LIB_SOURCES})
-# list code gen dependencies
+target_compile_options(riscv PRIVATE -Wno-shift-count-overflow)
-if(TARGET ${CORE_NAME}_src)
+target_include_directories(riscv PUBLIC incl ../external/elfio)
-    add_dependencies(${PROJECT_NAME} ${CORE_NAME}_src)
+target_link_libraries(riscv PUBLIC softfloat scc-util jsoncpp)
-endif()
+target_link_libraries(riscv PUBLIC -Wl,--whole-archive dbt-core -Wl,--no-whole-archive)
-
+set_target_properties(riscv PROPERTIES
-target_compile_options(${PROJECT_NAME} PRIVATE -Wno-shift-count-overflow)
-target_include_directories(${PROJECT_NAME} PUBLIC incl)
-target_link_libraries(${PROJECT_NAME} PUBLIC softfloat scc-util jsoncpp)
-target_link_libraries(${PROJECT_NAME} PUBLIC -Wl,--whole-archive dbt-core -Wl,--no-whole-archive)
-target_link_libraries(${PROJECT_NAME} PUBLIC ${Boost_LIBRARIES} )
-set_target_properties(${PROJECT_NAME} PROPERTIES
   VERSION ${PROJECT_VERSION}
   FRAMEWORK FALSE
   PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
 )
 
 if(SystemC_FOUND)
-	add_library(${PROJECT_NAME}_sc src/sysc/core_complex.cpp)
+	add_library(riscv_sc src/sysc/core_complex.cpp)
-	target_compile_definitions(${PROJECT_NAME}_sc PUBLIC WITH_SYSTEMC) 
+	target_compile_definitions(riscv_sc PUBLIC WITH_SYSTEMC) 
-	target_include_directories(${PROJECT_NAME}_sc PUBLIC ../incl ${SystemC_INCLUDE_DIRS} ${CCI_INCLUDE_DIRS})
+	target_include_directories(riscv_sc PUBLIC ../incl ${SystemC_INCLUDE_DIRS} ${CCI_INCLUDE_DIRS})
 	
 	if(SCV_FOUND)   
-	    target_compile_definitions(${PROJECT_NAME}_sc PUBLIC WITH_SCV)
+	    target_compile_definitions(riscv_sc PUBLIC WITH_SCV)
-	    target_include_directories(${PROJECT_NAME}_sc PUBLIC ${SCV_INCLUDE_DIRS})
+	    target_include_directories(riscv_sc PUBLIC ${SCV_INCLUDE_DIRS})
 	endif()
-	target_link_libraries(${PROJECT_NAME}_sc PUBLIC ${PROJECT_NAME} scc)
+	target_link_libraries(riscv_sc PUBLIC riscv scc )
 	if(WITH_LLVM)
-		target_link_libraries(${PROJECT_NAME}_sc PUBLIC ${llvm_libs})
+		target_link_libraries(riscv_sc PUBLIC ${llvm_libs})
 	endif()
-	set_target_properties(${PROJECT_NAME}_sc PROPERTIES
+	target_link_libraries(riscv_sc PUBLIC ${Boost_LIBRARIES} )
+	set_target_properties(riscv_sc PROPERTIES
 	  VERSION ${PROJECT_VERSION}
 	  FRAMEWORK FALSE
 	  PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
 	)
 endif()
 
-project("tgc-sim")
+project("riscv-sim")
-add_executable(${PROJECT_NAME} src/main.cpp)
+add_executable(riscv-sim src/main.cpp)
 # This sets the include directory for the reference project. This is the -I flag in gcc.
-
+target_include_directories(riscv-sim PRIVATE ../external/libGIS)
 if(WITH_LLVM)
-	target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_LLVM)
+	target_compile_definitions(riscv-sim PRIVATE WITH_LLVM)
-	target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
+	target_link_libraries(riscv-sim PUBLIC ${llvm_libs})
 endif()
 # Links the target exe against the libraries
-target_link_libraries(${PROJECT_NAME} tgc)
+target_link_libraries(riscv-sim riscv)
-target_link_libraries(${PROJECT_NAME} jsoncpp)
+target_link_libraries(riscv-sim jsoncpp)
-target_link_libraries(${PROJECT_NAME} ${Boost_LIBRARIES} )
+target_link_libraries(riscv-sim external)
+target_link_libraries(riscv-sim ${Boost_LIBRARIES} )
 if (Tcmalloc_FOUND)
-    target_link_libraries(${PROJECT_NAME} ${Tcmalloc_LIBRARIES})
+    target_link_libraries(riscv-sim ${Tcmalloc_LIBRARIES})
 endif(Tcmalloc_FOUND)
 
-install(TARGETS tgc tgc-sim
+install(TARGETS riscv riscv-sim
   EXPORT ${PROJECT_NAME}Targets            # for downstream dependencies
   ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs   # static lib
   RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} COMPONENT libs   # binaries
@@ -124,4 +120,4 @@ install(TARGETS tgc tgc-sim
 # CMAKE PACKAGING (for other CMake projects to use this one easily)
 # _____________________________________________________________________________
 
-#include(PackageConfigurator)
+#include(PackageConfigurator)

gen_input/TGFS.core_desc

@@ -3,25 +3,26 @@ import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
 import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
 
 Core TGF_B provides RV32I {
-	architectural_state {
+	constants {
-        unsigned XLEN=32;
+        XLEN:=32;
-        unsigned PCLEN=32;
+        PCLEN:=32;
         // definitions for the architecture wrapper
-        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        unsigned MISA_VAL = 0b01000000000000000000000100000000;
+        MISA_VAL:=0b01000000000000000000000100000000;
-        unsigned PGSIZE = 0x1000; //1 << 12;
+        PGSIZE := 0x1000; //1 << 12;
-        unsigned PGMASK = 0xfff; //PGSIZE-1
+        PGMASK := 0xfff; //PGSIZE-1
 	}
 }
 
 Core TGF_C provides RV32I, RV32M, RV32IC {
-    architectural_state {
+    constants {
-        unsigned XLEN=32;
+        XLEN:=32;
-        unsigned PCLEN=32;
+        PCLEN:=32;
+        MUL_LEN:=64;
         // definitions for the architecture wrapper
-        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        unsigned MISA_VAL = 0b01000000000000000001000100000100;
+        MISA_VAL:=0b01000000000000000001000100000100;
-        unsigned PGSIZE = 0x1000; //1 << 12;
+        PGSIZE := 0x1000; //1 << 12;
-        unsigned PGMASK = 0xfff; //PGSIZE-1
+        PGMASK := 0xfff; //PGSIZE-1
     }
-}
+}

gen_input/minres_rv.core_desc

@@ -0,0 +1,74 @@
+import "RV32I.core_desc"
+import "RV64I.core_desc"
+import "RVM.core_desc"
+import "RVA.core_desc"
+import "RVC.core_desc"
+import "RVF.core_desc"
+import "RVD.core_desc"
+
+
+Core MNRV32 provides RV32I, RV32IC {
+    constants {
+        XLEN:=32;
+        PCLEN:=32;
+        // definitions for the architecture wrapper
+        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        MISA_VAL:=0b01000000000101000001000100000101;
+        PGSIZE := 0x1000; //1 << 12;
+        PGMASK := 0xfff; //PGSIZE-1
+    }
+}
+
+Core RV32IMAC provides RV32I, RV32M, RV32A, RV32IC {
+    constants {
+        XLEN:=32;
+        PCLEN:=32;
+        MUL_LEN:=64;
+        // definitions for the architecture wrapper
+        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        MISA_VAL:=0b01000000000101000001000100000101;
+        PGSIZE := 0x1000; //1 << 12;
+        PGMASK := 0xfff; //PGSIZE-1
+    }
+}
+
+Core RV32GC provides RV32I, RV32M, RV32A, RV32F, RV32D, RV32IC, RV32FC, RV32DC {
+    constants {
+        XLEN:=32;
+        FLEN:=64;
+        PCLEN:=32;
+        MUL_LEN:=64;
+        // definitions for the architecture wrapper
+        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        MISA_VAL:=0b01000000000101000001000100101101;
+        PGSIZE := 0x1000; //1 << 12;
+        PGMASK := 0xfff; //PGSIZE-1
+    }
+}
+
+Core RV64I provides RV64I {
+    constants {
+        XLEN:=64;
+        PCLEN:=64;
+        // definitions for the architecture wrapper
+        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        MISA_VAL:=0b10000000000001000000000100000000;
+        PGSIZE := 0x1000; //1 << 12;
+        PGMASK := 0xfff; //PGSIZE-1
+    }
+}
+
+Core RV64GC provides RV64I, RV64M, RV64A, RV64F, RV64D, RV32FC, RV32DC, RV64IC {
+    constants {
+        XLEN:=64;
+        FLEN:=64;
+        PCLEN:=64;
+        MUL_LEN:=128;
+        // definitions for the architecture wrapper
+        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        MISA_VAL:=0b01000000000101000001000100101101;
+        PGSIZE := 0x1000; //1 << 12;
+        PGMASK := 0xfff; //PGSIZE-1
+    }
+}
+

gen_input/templates/interp/incl-CORENAME.h.gtl

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017 - 2021 MINRES Technologies GmbH
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -29,38 +29,47 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
-<%
-import com.minres.coredsl.util.BigIntegerWithRadix
 
-def nativeTypeSize(int size){
+<% 
-    if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
+import com.minres.coredsl.coreDsl.Register
+import com.minres.coredsl.coreDsl.RegisterFile
+import com.minres.coredsl.coreDsl.RegisterAlias
+def getTypeSize(size){
+	if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
 }
-def getRegisterSizes(){
+def getOriginalName(reg){
-    def regs = registers.collect{nativeTypeSize(it.size)}
+    if( reg.original instanceof RegisterFile) {
-    regs+=[32,32, 64] // append TRAP_STATE, PENDING_TRAP, ICOUNT
+    	if( reg.index != null ) {
-    return regs
+        	return reg.original.name+generator.generateHostCode(reg.index)
-}
+        } else {
-def getRegisterOffsets(){
+        	return reg.original.name
-    def offset = 0
+        }
-    def offsets = []
+    } else if(reg.original instanceof Register){
-    getRegisterSizes().each { size ->
+        return reg.original.name
-        offsets<<offset
-        offset+=size/8
     }
-    return offsets
 }
-def byteSize(int size){
+def getRegisterNames(){
-    if(size<=8) return 8;
+	def regNames = []
-    if(size<=16) return 16;
+ 	allRegs.each { reg -> 
-    if(size<=32) return 32;
+		if( reg instanceof RegisterFile) {
-    if(size<=64) return 64;
+			(reg.range.right..reg.range.left).each{
-    return 128;
+    			regNames+=reg.name.toLowerCase()+it
+            }
+        } else if(reg instanceof Register){
+    		regNames+=reg.name.toLowerCase()
+        }
+    }
+    return regNames
 }
-def getCString(def val){
+def getRegisterAliasNames(){
-    if(val instanceof BigIntegerWithRadix)
+	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
-        return ((BigIntegerWithRadix)val).toCString()
+ 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
-    else
+		if( reg instanceof RegisterFile) {
-        return val.toString()
+			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
+        } else if(reg instanceof Register){
+    		regMap[reg.name]?:reg.name.toLowerCase()
+        }
+ 	}.flatten()
 }
 %>
 #ifndef _${coreDef.name.toUpperCase()}_H_
@@ -78,26 +87,43 @@ struct ${coreDef.name.toLowerCase()};
 
 template <> struct traits<${coreDef.name.toLowerCase()}> {
 
-    constexpr static char const* const core_type = "${coreDef.name}";
+	constexpr static char const* const core_type = "${coreDef.name}";
     
-    static constexpr std::array<const char*, ${registers.size}> reg_names{
+  	static constexpr std::array<const char*, ${getRegisterNames().size}> reg_names{
-        {"${registers.collect{it.name}.join('", "')}"}};
+ 		{"${getRegisterNames().join("\", \"")}"}};
  
-    static constexpr std::array<const char*, ${registers.size}> reg_aliases{
+  	static constexpr std::array<const char*, ${getRegisterAliasNames().size}> reg_aliases{
-        {"${registers.collect{it.alias}.join('", "')}"}};
+ 		{"${getRegisterAliasNames().join("\", \"")}"}};
 
-    enum constants {${constants.collect{c -> c.name+"="+getCString(c.value)}.join(', ')}};
+    enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
 
-    constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0};
+    constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
 
-    enum reg_e {
+    enum reg_e {<%
-        ${registers.collect{it.name}.join(', ')}, NUM_REGS,
+     	allRegs.each { reg -> 
-        TRAP_STATE=NUM_REGS,
+    		if( reg instanceof RegisterFile) {
+    			(reg.range.right..reg.range.left).each{%>
+        ${reg.name}${it},<%
+                }
+            } else if(reg instanceof Register){ %>
+        ${reg.name},<%  
+            }
+        }%>
+        NUM_REGS,
+        NEXT_${pc.name}=NUM_REGS,
+        TRAP_STATE,
         PENDING_TRAP,
-        ICOUNT
+        MACHINE_STATE,
+        LAST_BRANCH,
+        ICOUNT<% 
+     	allRegs.each { reg -> 
+    		if(reg instanceof RegisterAlias){ def aliasname=getOriginalName(reg)%>,
+        ${reg.name} = ${aliasname}<%
+            }
+        }%>
     };
 
-    using reg_t = uint${addrDataWidth}_t;
+    using reg_t = uint${regDataWidth}_t;
 
     using addr_t = uint${addrDataWidth}_t;
 
@@ -107,22 +133,17 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
 
     using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
 
-    static constexpr std::array<const uint32_t, ${getRegisterSizes().size}> reg_bit_widths{
+ 	static constexpr std::array<const uint32_t, ${regSizes.size}> reg_bit_widths{
-        {${getRegisterSizes().join(',')}}};
+ 		{${regSizes.join(",")}}};
 
-    static constexpr std::array<const uint32_t, ${getRegisterOffsets().size}> reg_byte_offsets{
+    static constexpr std::array<const uint32_t, ${regOffsets.size}> reg_byte_offsets{
-        {${getRegisterOffsets().join(',')}}};
+    	{${regOffsets.join(",")}}};
 
     static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
 
     enum sreg_flag_e { FLAGS };
 
-    enum mem_type_e { ${spaces.collect{it.name}.join(', ')} };
+    enum mem_type_e { ${allSpaces.collect{s -> s.name}.join(', ')} };
-    
-    enum class opcode_e : unsigned short {<%instructions.eachWithIndex{instr, index -> %>
-        ${instr.instruction.name} = ${index},<%}%>
-        MAX_OPCODE
-    };
 };
 
 struct ${coreDef.name.toLowerCase()}: public arch_if {
@@ -168,27 +189,32 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
     inline uint32_t get_last_branch() { return reg.last_branch; }
 
 protected:
-#pragma pack(push, 1)
     struct ${coreDef.name}_regs {<%
-        registers.each { reg -> if(reg.size>0) {%> 
+     	allRegs.each { reg -> 
-        uint${byteSize(reg.size)}_t ${reg.name} = 0;<%
+    		if( reg instanceof RegisterFile) {
-        }}%>
+    			(reg.range.right..reg.range.left).each{%>
-        uint32_t trap_state = 0, pending_trap = 0;
+        uint${generator.getSize(reg)}_t ${reg.name}${it} = 0;<%
+                }
+            } else if(reg instanceof Register){ %>
+        uint${generator.getSize(reg)}_t ${reg.name} = 0;<%
+            }
+        }%>
+        uint${generator.getSize(pc)}_t NEXT_${pc.name} = 0;
+        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
         uint64_t icount = 0;
-        uint32_t last_branch;
     } reg;
-#pragma pack(pop)
+
     std::array<address_type, 4> addr_mode;
     
     uint64_t interrupt_sim=0;
 <%
-def fcsr = registers.find {it.name=='FCSR'}
+def fcsr = allRegs.find {it.name=='FCSR'}
 if(fcsr != null) {%>
-    uint${fcsr.size}_t get_fcsr(){return reg.FCSR;}
+	uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
-    void set_fcsr(uint${fcsr.size}_t val){reg.FCSR = val;}      
+	void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}		
 <%} else { %>
-    uint32_t get_fcsr(){return 0;}
+	uint32_t get_fcsr(){return 0;}
-    void set_fcsr(uint32_t val){}
+	void set_fcsr(uint32_t val){}
 <%}%>
 };
 

gen_input/templates/interp/src-CORENAME.cpp.gtl

@@ -0,0 +1,107 @@
+/*******************************************************************************
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+ <% 
+import com.minres.coredsl.coreDsl.Register
+import com.minres.coredsl.coreDsl.RegisterFile
+import com.minres.coredsl.coreDsl.RegisterAlias
+def getOriginalName(reg){
+    if( reg.original instanceof RegisterFile) {
+    	if( reg.index != null ) {
+        	return reg.original.name+generator.generateHostCode(reg.index)
+        } else {
+        	return reg.original.name
+        }
+    } else if(reg.original instanceof Register){
+        return reg.original.name
+    }
+}
+def getRegisterNames(){
+	def regNames = []
+ 	allRegs.each { reg -> 
+		if( reg instanceof RegisterFile) {
+			(reg.range.right..reg.range.left).each{
+    			regNames+=reg.name.toLowerCase()+it
+            }
+        } else if(reg instanceof Register){
+    		regNames+=reg.name.toLowerCase()
+        }
+    }
+    return regNames
+}
+def getRegisterAliasNames(){
+	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
+ 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
+		if( reg instanceof RegisterFile) {
+			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
+        } else if(reg instanceof Register){
+    		regMap[reg.name]?:reg.name.toLowerCase()
+        }
+ 	}.flatten()
+}
+%>
+#include "util/ities.h"
+#include <util/logging.h>
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <cstdio>
+#include <cstring>
+#include <fstream>
+
+using namespace iss::arch;
+
+constexpr std::array<const char*, ${getRegisterNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
+constexpr std::array<const char*, ${getRegisterAliasNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
+constexpr std::array<const uint32_t, ${regSizes.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
+constexpr std::array<const uint32_t, ${regOffsets.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
+
+${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
+    reg.icount = 0;
+}
+
+${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
+
+void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
+    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
+    reg.PC=address;
+    reg.NEXT_PC=reg.PC;
+    reg.trap_state=0;
+    reg.machine_state=0x3;
+    reg.icount=0;
+}
+
+uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
+	return reinterpret_cast<uint8_t*>(&reg);
+}
+
+${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
+    return phys_addr_t(pc); // change logical address to physical address
+}
+

gen_input/templates/interp/vm-vm_CORENAME.cpp.gtl

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2021 MINRES Technologies GmbH
+ * Copyright (C) 2020 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -56,14 +56,13 @@ using namespace iss::debugger;
 
 template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
 public:
-    using traits = arch::traits<ARCH>;
+    using super = typename iss::interp::vm_base<ARCH>;
-    using super       = typename iss::interp::vm_base<ARCH>;
     using virt_addr_t = typename super::virt_addr_t;
     using phys_addr_t = typename super::phys_addr_t;
     using code_word_t = typename super::code_word_t;
-    using addr_t      = typename super::addr_t;
+    using addr_t = typename super::addr_t;
-    using reg_t       = typename traits::reg_t;
+    using reg_t = typename traits<ARCH>::reg_t;
-    using mem_type_e  = typename traits::mem_type_e;
+    using iss::interp::vm_base<ARCH>::get_reg;
 
     vm_impl();
 
@@ -83,9 +82,9 @@ protected:
     using compile_ret_t = virt_addr_t;
     using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
 
-    inline const char *name(size_t index){return traits::reg_aliases.at(index);}
+    inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
 
-    virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;
+    virt_addr_t execute_inst(virt_addr_t start, std::function<bool(void)> pred) override;
 
     // some compile time constants
     // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
@@ -139,38 +138,23 @@ protected:
         return lut_val;
     }
 
-    inline void raise(uint16_t trap_id, uint16_t cause){
+    void raise_trap(uint16_t trap_id, uint16_t cause){
         auto trap_val =  0x80ULL << 24 | (cause << 16) | trap_id;
-        this->template get_reg<uint32_t>(traits::TRAP_STATE) = trap_val;
+        this->template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE) = trap_val;
-        this->template get_reg<uint32_t>(traits::NEXT_PC) = std::numeric_limits<uint32_t>::max();
+        this->template get_reg<uint32_t>(arch::traits<ARCH>::NEXT_PC) = std::numeric_limits<uint32_t>::max();
     }
 
-    inline void leave(unsigned lvl){
+    void leave_trap(unsigned lvl){
         this->core.leave_trap(lvl);
-        auto pc_val = super::template read_mem<reg_t>(traits::CSR, (lvl << 8) + 0x41);
+        auto pc_val = super::template read_mem<reg_t>(traits<ARCH>::CSR, (lvl << 8) + 0x41);
-        this->template get_reg<reg_t>(traits::NEXT_PC) = pc_val;
+        this->template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc_val;
+        this->template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH) = std::numeric_limits<uint32_t>::max();
     }
 
-    inline void wait(unsigned type){
+    void wait(unsigned type){
         this->core.wait_until(type);
     }
 
-    template<typename T>
-    T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;}
-    inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint8_t>(space, addr);}
-    inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint16_t>(space, addr);}
-    inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint32_t>(space, addr);}
-    inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint64_t>(space, addr);}
-    inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){super::write_mem(space, addr, data);}
-    inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){super::write_mem(space, addr, data);}
-    inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){super::write_mem(space, addr, data);}
-    inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){super::write_mem(space, addr, data);}
-    template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
-    inline S sext(U from) {
-        auto mask = (1ULL<<W) - 1;
-        auto sign_mask = 1ULL<<(W-1);
-        return (from & mask) | ((from & sign_mask) ? ~mask : 0);
-    }
 
 private:
     /****************************************************************************
@@ -186,74 +170,22 @@ private:
     const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
          /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
         /* instruction ${instr.instruction.name} */
-        {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
+        {${instr.length}, ${instr.value}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
     }};
  
     /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
     /* instruction ${idx}: ${instr.name} */
-    compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr){
+    compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr){<%instr.code.eachLine{%>
-        // pre execution stuff
+        ${it}<%}%>
-        this->do_sync(PRE_SYNC, ${idx});
-        <%instr.fields.eachLine{%>${it}
-        <%}%>if(this->disass_enabled){
-            /* generate console output when executing the command */
-            <%instr.disass.eachLine{%>${it}
-            <%}%>
-        }
-        // prepare execution
-        uint${addrDataWidth}_t* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        uint${addrDataWidth}_t* NEXT_PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        // used registers<%instr.usedVariables.each{ k,v->
-            if(v.isArray) {%>
-        uint${v.type.size}_t* ${k} = reinterpret_cast<uint${v.type.size}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %> 
-        uint${v.type.size}_t* ${k} = reinterpret_cast<uint${v.type.size}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
-        <%}}%>// calculate next pc value
-        *NEXT_PC = *PC + ${instr.length/8};
-        // execute instruction
-        <%instr.behavior.eachLine{%>${it}
-        <%}%>// post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, ${idx});
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val);
-        }
-        pc.val=*NEXT_PC;
-        return pc;
     }
     <%}%>
     /****************************************************************************
      * end opcode definitions
      ****************************************************************************/
     compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr) {
-        this->do_sync(PRE_SYNC, static_cast<unsigned>(arch::traits<ARCH>::opcode_e::MAX_OPCODE));
+        pc = pc + ((instr & 3) == 3 ? 4 : 2);
-        uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
-        raise(0,  11);
-        // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(arch::traits<ARCH>::opcode_e::MAX_OPCODE));
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val);
-        }
-        pc.val=*NEXT_PC;
         return pc;
     }
-
-    static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK;
-    iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
-        auto phys_pc = this->core.v2p(pc);
-        //if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
-        //    if (this->core.read(phys_pc, 2, data) != iss::Ok) return iss::Err;
-        //    if ((data[0] & 0x3) == 0x3) // this is a 32bit instruction
-        //        if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok) return iss::Err;
-        //} else {
-            if (this->core.read(phys_pc, 4, data) != iss::Ok)  return iss::Err;
-        //}
-        return iss::Ok;
-    }
 };
 
 template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
@@ -276,26 +208,24 @@ vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
     }
 }
 
-inline bool is_count_limit_enabled(finish_cond_e cond){
-    return (cond & finish_cond_e::COUNT_LIMIT) == finish_cond_e::COUNT_LIMIT;
-}
 template <typename ARCH>
-typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
+typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(virt_addr_t start, std::function<bool(void)> pred) {
     // we fetch at max 4 byte, alignment is 2
     enum {TRAP_ID=1<<16};
+    const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
     code_word_t insn = 0;
     auto *const data = (uint8_t *)&insn;
     auto pc=start;
-    while(!this->core.should_stop() &&
+    while(pred){
-            !(is_count_limit_enabled(cond) && this->core.get_icount() >= icount_limit)){
+        auto paddr = this->core.v2p(pc);
-        auto res = fetch_ins(pc, data);
+        if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
-        if(res!=iss::Ok){
+            if (this->core.read(paddr, 2, data) != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-            auto new_pc = super::core.enter_trap(TRAP_ID, pc.val);
+            if ((insn & 0x3) == 0x3) // this is a 32bit instruction
-            res = fetch_ins(virt_addr_t{access_type::FETCH, new_pc}, data);
+                if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-            if(res!=iss::Ok) throw simulation_stopped(0);
+        } else {
+            if (this->core.read(paddr, 4, data) != iss::Ok) throw trap_access(TRAP_ID, pc.val);
         }
-        if ((cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF &&
+        if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
-                (insn == 0x0000006f || (insn&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
         auto lut_val = extract_fields(insn);
         auto f = qlut[insn & 0x3][lut_val];
         if (!f)

incl/iss/arch/.gitignore

@@ -1 +0,0 @@
-/tgf_b.h

incl/iss/arch/riscv_hart_m_p.h

@@ -50,7 +50,6 @@
 #include <sstream>
 #include <type_traits>
 #include <unordered_map>
-#include <functional>
 #include <util/bit_field.h>
 #include <util/ities.h>
 #include <util/sparse_array.h>
@@ -309,6 +308,8 @@ public:
 
         T satp;
 
+        static constexpr T get_misa() { return (1UL << 30) | ISA_I | ISA_M | ISA_A | ISA_U | ISA_S | ISA_M; }
+
         static constexpr uint32_t get_mask() {
             return 0x807ff9ddUL; // 0b1000 0000 0111 1111 1111 1001 1011 1011  // only machine mode is supported
         }
@@ -343,19 +344,7 @@ public:
     };
 
     iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
-
+ 
-    void setMemReadCb(std::function<iss::status(phys_addr_t, unsigned, uint8_t* const)> const& memReadCb) {
-        mem_read_cb = memReadCb;
-    }
-
-    void setMemWriteCb(std::function<iss::status(phys_addr_t, unsigned, const uint8_t* const)> const& memWriteCb) {
-        mem_write_cb = memWriteCb;
-    }
-
-    void set_csr(unsigned addr, reg_t val){
-        csr[addr & csr.page_addr_mask] = val;
-    }
-
 protected:
     struct riscv_instrumentation_if : public iss::instrumentation_if {
 
@@ -407,8 +396,6 @@ protected:
     std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
 
 private:
-    iss::status read_reg(unsigned addr, reg_t &val);
-    iss::status write_reg(unsigned addr, reg_t val);
     iss::status read_cycle(unsigned addr, reg_t &val);
     iss::status read_time(unsigned addr, reg_t &val);
     iss::status read_status(unsigned addr, reg_t &val);
@@ -419,9 +406,7 @@ private:
     iss::status write_ip(unsigned addr, reg_t val);
     iss::status read_hartid(unsigned addr, reg_t &val);
 
-    reg_t mhartid_reg{0x0};
+    reg_t mhartid_reg{0xF};
-    std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
-    std::function<iss::status(phys_addr_t, unsigned, const uint8_t *const)> mem_write_cb;
 
 protected:
     void check_interrupt();
@@ -432,8 +417,10 @@ riscv_hart_m_p<BASE>::riscv_hart_m_p()
 : state()
 , cycle_offset(0)
 , instr_if(*this) {
-    csr[misa] = traits<BASE>::MISA_VAL;
+    csr[misa] = hart_state<reg_t>::get_misa();
     uart_buf.str("");
+    // read-only registers
+    csr_wr_cb[misa] = nullptr;
     for (unsigned addr = mcycle; addr <= hpmcounter31; ++addr) csr_wr_cb[addr] = nullptr;
     for (unsigned addr = mcycleh; addr <= hpmcounter31h; ++addr) csr_wr_cb[addr] = nullptr;
     // special handling
@@ -452,15 +439,6 @@ riscv_hart_m_p<BASE>::riscv_hart_m_p()
     csr_rd_cb[mie] = &riscv_hart_m_p<BASE>::read_ie;
     csr_wr_cb[mie] = &riscv_hart_m_p<BASE>::write_ie;
     csr_rd_cb[mhartid] = &riscv_hart_m_p<BASE>::read_hartid;
-    // common regs
-    const std::array<unsigned, 6> addrs{{mepc, mtvec, mscratch, mcause, mtval, mscratch}};
-    for(auto addr: addrs) {
-        csr_rd_cb[addr] = &riscv_hart_m_p<BASE>::read_reg;
-        csr_wr_cb[addr] = &riscv_hart_m_p<BASE>::write_reg;
-    }
-    // read-only registers
-    csr_rd_cb[misa] = &riscv_hart_m_p<BASE>::read_reg;
-    csr_wr_cb[misa] = nullptr;
 }
 
 template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_file(std::string name, int type) {
@@ -675,35 +653,32 @@ iss::status riscv_hart_m_p<BASE>::write(const address_type type, const access_ty
 template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_csr(unsigned addr, reg_t &val) {
     if (addr >= csr.size()) return iss::Err;
     auto req_priv_lvl = (addr >> 8) & 0x3;
-    if (this->reg.PRIV < req_priv_lvl) // not having required privileges
+    if (this->reg.machine_state < req_priv_lvl) throw illegal_instruction_fault(this->fault_data);
-        throw illegal_instruction_fault(this->fault_data);
     auto it = csr_rd_cb.find(addr);
-    if (it == csr_rd_cb.end() || !it->second) // non existent register
+    if (it == csr_rd_cb.end()) {
-        throw illegal_instruction_fault(this->fault_data);
+        val = csr[addr & csr.page_addr_mask];
-    return (this->*(it->second))(addr, val);
+        return iss::Ok;
+    }
+    rd_csr_f f = it->second;
+    if (f == nullptr) throw illegal_instruction_fault(this->fault_data);
+    return (this->*f)(addr, val);
 }
 
 template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_csr(unsigned addr, reg_t val) {
     if (addr >= csr.size()) return iss::Err;
     auto req_priv_lvl = (addr >> 8) & 0x3;
-    if (this->reg.PRIV < req_priv_lvl) // not having required privileges
+    if (this->reg.machine_state < req_priv_lvl)
         throw illegal_instruction_fault(this->fault_data);
-    if((addr&0xc00)==0xc00) // writing to read-only region
+    if((addr&0xc00)==0xc00)
         throw illegal_instruction_fault(this->fault_data);
     auto it = csr_wr_cb.find(addr);
-    if (it == csr_wr_cb.end() || !it->second) // non existent register
+    if (it == csr_wr_cb.end()) {
-        throw illegal_instruction_fault(this->fault_data);
+        csr[addr & csr.page_addr_mask] = val;
-    return (this->*(it->second))(addr, val);
+        return iss::Ok;
-}
+    }
-
+    wr_csr_f f = it->second;
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_reg(unsigned addr, reg_t &val) {
+    if (f == nullptr) throw illegal_instruction_fault(this->fault_data);
-    val = csr[addr];
+    return (this->*f)(addr, val);
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_reg(unsigned addr, reg_t val) {
-    csr[addr] = val;
-    return iss::Ok;
 }
 
 template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_cycle(unsigned addr, reg_t &val) {
@@ -774,7 +749,6 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_ip(unsigned add
 template <typename BASE>
 iss::status riscv_hart_m_p<BASE>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
     if ((paddr.val + length) > mem.size()) return iss::Err;
-    if(mem_read_cb) return mem_read_cb(paddr, length, data);
     switch (paddr.val) {
     case 0x0200BFF8: { // CLINT base, mtime reg
         if (sizeof(reg_t) < length) return iss::Err;
@@ -800,7 +774,6 @@ iss::status riscv_hart_m_p<BASE>::read_mem(phys_addr_t paddr, unsigned length, u
 template <typename BASE>
 iss::status riscv_hart_m_p<BASE>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
     if ((paddr.val + length) > mem.size()) return iss::Err;
-    if(mem_write_cb) return mem_write_cb(paddr, length, data);
     switch (paddr.val) {
     case 0x10013000: // UART0 base, TXFIFO reg
     case 0x10023000: // UART1 base, TXFIFO reg
@@ -888,15 +861,12 @@ template <typename BASE> void riscv_hart_m_p<BASE>::check_interrupt() {
     auto ena_irq = csr[mip] & csr[mie];
 
     bool mie = state.mstatus.MIE;
-    auto m_enabled = this->reg.PRIV < PRIV_M || (this->reg.PRIV == PRIV_M && mie);
+    auto m_enabled = this->reg.machine_state < PRIV_M || (this->reg.machine_state == PRIV_M && mie);
     auto enabled_interrupts = m_enabled ? ena_irq & ~ideleg : 0;
 
     if (enabled_interrupts != 0) {
         int res = 0;
-        while ((enabled_interrupts & 1) == 0) {
+        while ((enabled_interrupts & 1) == 0) enabled_interrupts >>= 1, res++;
-        	enabled_interrupts >>= 1;
-        	res++;
-        }
         this->reg.pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id
     }
 }
@@ -936,7 +906,7 @@ template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flag
     this->reg.NEXT_PC = ivec & ~0x1UL;
     if ((ivec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
     // reset trap state
-    this->reg.PRIV = PRIV_M;
+    this->reg.machine_state = PRIV_M;
     this->reg.trap_state = 0;
     std::array<char, 32> buffer;
     sprintf(buffer.data(), "0x%016lx", addr);
@@ -948,7 +918,20 @@ template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flag
 }
 
 template <typename BASE> uint64_t riscv_hart_m_p<BASE>::leave_trap(uint64_t flags) {
-    state.mstatus.MIE = state.mstatus.MPIE;
+    auto cur_priv = this->reg.machine_state;
+    auto inst_priv = flags & 0x3;
+    auto status = state.mstatus;
+
+    // pop the relevant lower-privilege interrupt enable and privilege mode stack
+    // clear respective yIE
+    if (inst_priv == PRIV_M) {
+        this->reg.machine_state = state.mstatus.MPP;
+        state.mstatus.MPP = 0; // clear mpp to U mode
+        state.mstatus.MIE = state.mstatus.MPIE;
+    } else {
+    	CLOG(ERROR, disass) << "Unsupported mode:" << inst_priv;
+    }
+
     // sets the pc to the value stored in the x epc register.
     this->reg.NEXT_PC = csr[mepc];
     CLOG(INFO, disass) << "Executing xRET";

incl/iss/arch/tgf_b.h

@@ -0,0 +1,252 @@
+/*******************************************************************************
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+
+#ifndef _TGF_B_H_
+#define _TGF_B_H_
+
+#include <array>
+#include <iss/arch/traits.h>
+#include <iss/arch_if.h>
+#include <iss/vm_if.h>
+
+namespace iss {
+namespace arch {
+
+struct tgf_b;
+
+template <> struct traits<tgf_b> {
+
+	constexpr static char const* const core_type = "TGF_B";
+    
+  	static constexpr std::array<const char*, 33> reg_names{
+ 		{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc"}};
+ 
+  	static constexpr std::array<const char*, 33> reg_aliases{
+ 		{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc"}};
+
+    enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000000000000000100000000, PGSIZE=0x1000, PGMASK=0xfff};
+
+    constexpr static unsigned FP_REGS_SIZE = 0;
+
+    enum reg_e {
+        X0,
+        X1,
+        X2,
+        X3,
+        X4,
+        X5,
+        X6,
+        X7,
+        X8,
+        X9,
+        X10,
+        X11,
+        X12,
+        X13,
+        X14,
+        X15,
+        X16,
+        X17,
+        X18,
+        X19,
+        X20,
+        X21,
+        X22,
+        X23,
+        X24,
+        X25,
+        X26,
+        X27,
+        X28,
+        X29,
+        X30,
+        X31,
+        PC,
+        NUM_REGS,
+        NEXT_PC=NUM_REGS,
+        TRAP_STATE,
+        PENDING_TRAP,
+        MACHINE_STATE,
+        LAST_BRANCH,
+        ICOUNT,
+        ZERO = X0,
+        RA = X1,
+        SP = X2,
+        GP = X3,
+        TP = X4,
+        T0 = X5,
+        T1 = X6,
+        T2 = X7,
+        S0 = X8,
+        S1 = X9,
+        A0 = X10,
+        A1 = X11,
+        A2 = X12,
+        A3 = X13,
+        A4 = X14,
+        A5 = X15,
+        A6 = X16,
+        A7 = X17,
+        S2 = X18,
+        S3 = X19,
+        S4 = X20,
+        S5 = X21,
+        S6 = X22,
+        S7 = X23,
+        S8 = X24,
+        S9 = X25,
+        S10 = X26,
+        S11 = X27,
+        T3 = X28,
+        T4 = X29,
+        T5 = X30,
+        T6 = X31
+    };
+
+    using reg_t = uint32_t;
+
+    using addr_t = uint32_t;
+
+    using code_word_t = uint32_t; //TODO: check removal
+
+    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
+
+    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
+
+ 	static constexpr std::array<const uint32_t, 39> reg_bit_widths{
+ 		{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64}};
+
+    static constexpr std::array<const uint32_t, 40> reg_byte_offsets{
+    	{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,160}};
+
+    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
+
+    enum sreg_flag_e { FLAGS };
+
+    enum mem_type_e { MEM, CSR, FENCE, RES };
+};
+
+struct tgf_b: public arch_if {
+
+    using virt_addr_t = typename traits<tgf_b>::virt_addr_t;
+    using phys_addr_t = typename traits<tgf_b>::phys_addr_t;
+    using reg_t =  typename traits<tgf_b>::reg_t;
+    using addr_t = typename traits<tgf_b>::addr_t;
+
+    tgf_b();
+    ~tgf_b();
+
+    void reset(uint64_t address=0) override;
+
+    uint8_t* get_regs_base_ptr() override;
+    /// deprecated
+    void get_reg(short idx, std::vector<uint8_t>& value) override {}
+    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
+    /// deprecated
+    bool get_flag(int flag) override {return false;}
+    void set_flag(int, bool value) override {};
+    /// deprecated
+    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
+
+    inline uint64_t get_icount() { return reg.icount; }
+
+    inline bool should_stop() { return interrupt_sim; }
+
+    inline uint64_t stop_code() { return interrupt_sim; }
+
+    inline phys_addr_t v2p(const iss::addr_t& addr){
+        if (addr.space != traits<tgf_b>::MEM || addr.type == iss::address_type::PHYSICAL ||
+                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
+            return phys_addr_t(addr.access, addr.space, addr.val&traits<tgf_b>::addr_mask);
+        } else
+            return virt2phys(addr);
+    }
+
+    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
+
+    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
+
+    inline uint32_t get_last_branch() { return reg.last_branch; }
+
+protected:
+    struct TGF_B_regs {
+        uint32_t X0 = 0;
+        uint32_t X1 = 0;
+        uint32_t X2 = 0;
+        uint32_t X3 = 0;
+        uint32_t X4 = 0;
+        uint32_t X5 = 0;
+        uint32_t X6 = 0;
+        uint32_t X7 = 0;
+        uint32_t X8 = 0;
+        uint32_t X9 = 0;
+        uint32_t X10 = 0;
+        uint32_t X11 = 0;
+        uint32_t X12 = 0;
+        uint32_t X13 = 0;
+        uint32_t X14 = 0;
+        uint32_t X15 = 0;
+        uint32_t X16 = 0;
+        uint32_t X17 = 0;
+        uint32_t X18 = 0;
+        uint32_t X19 = 0;
+        uint32_t X20 = 0;
+        uint32_t X21 = 0;
+        uint32_t X22 = 0;
+        uint32_t X23 = 0;
+        uint32_t X24 = 0;
+        uint32_t X25 = 0;
+        uint32_t X26 = 0;
+        uint32_t X27 = 0;
+        uint32_t X28 = 0;
+        uint32_t X29 = 0;
+        uint32_t X30 = 0;
+        uint32_t X31 = 0;
+        uint32_t PC = 0;
+        uint32_t NEXT_PC = 0;
+        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
+        uint64_t icount = 0;
+    } reg;
+
+    std::array<address_type, 4> addr_mode;
+    
+    uint64_t interrupt_sim=0;
+
+	uint32_t get_fcsr(){return 0;}
+	void set_fcsr(uint32_t val){}
+
+};
+
+}
+}            
+#endif /* _TGF_B_H_ */

incl/iss/arch/tgf_c.h

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017 - 2021 MINRES Technologies GmbH
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -30,6 +30,7 @@
  *
  *******************************************************************************/
 
+
 #ifndef _TGF_C_H_
 #define _TGF_C_H_
 
@@ -45,23 +46,91 @@ struct tgf_c;
 
 template <> struct traits<tgf_c> {
 
-    constexpr static char const* const core_type = "TGF_C";
+	constexpr static char const* const core_type = "TGF_C";
     
-    static constexpr std::array<const char*, 35> reg_names{
+  	static constexpr std::array<const char*, 33> reg_names{
-        {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
+ 		{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc"}};
  
-    static constexpr std::array<const char*, 35> reg_aliases{
+  	static constexpr std::array<const char*, 33> reg_aliases{
-        {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
+ 		{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc"}};
 
-    enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b01000000000000000001000100000100, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, eei_aligned_addresses=1, MUL_LEN=64};
+    enum constants {XLEN=32, PCLEN=32, MUL_LEN=64, MISA_VAL=0b1000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0xfff};
 
     constexpr static unsigned FP_REGS_SIZE = 0;
 
     enum reg_e {
-        X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, NUM_REGS,
+        X0,
-        TRAP_STATE=NUM_REGS,
+        X1,
+        X2,
+        X3,
+        X4,
+        X5,
+        X6,
+        X7,
+        X8,
+        X9,
+        X10,
+        X11,
+        X12,
+        X13,
+        X14,
+        X15,
+        X16,
+        X17,
+        X18,
+        X19,
+        X20,
+        X21,
+        X22,
+        X23,
+        X24,
+        X25,
+        X26,
+        X27,
+        X28,
+        X29,
+        X30,
+        X31,
+        PC,
+        NUM_REGS,
+        NEXT_PC=NUM_REGS,
+        TRAP_STATE,
         PENDING_TRAP,
-        ICOUNT
+        MACHINE_STATE,
+        LAST_BRANCH,
+        ICOUNT,
+        ZERO = X0,
+        RA = X1,
+        SP = X2,
+        GP = X3,
+        TP = X4,
+        T0 = X5,
+        T1 = X6,
+        T2 = X7,
+        S0 = X8,
+        S1 = X9,
+        A0 = X10,
+        A1 = X11,
+        A2 = X12,
+        A3 = X13,
+        A4 = X14,
+        A5 = X15,
+        A6 = X16,
+        A7 = X17,
+        S2 = X18,
+        S3 = X19,
+        S4 = X20,
+        S5 = X21,
+        S6 = X22,
+        S7 = X23,
+        S8 = X24,
+        S9 = X25,
+        S10 = X26,
+        S11 = X27,
+        T3 = X28,
+        T4 = X29,
+        T5 = X30,
+        T6 = X31
     };
 
     using reg_t = uint32_t;
@@ -74,109 +143,17 @@ template <> struct traits<tgf_c> {
 
     using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
 
-    static constexpr std::array<const uint32_t, 38> reg_bit_widths{
+ 	static constexpr std::array<const uint32_t, 39> reg_bit_widths{
-        {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,64}};
+ 		{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64}};
 
-    static constexpr std::array<const uint32_t, 38> reg_byte_offsets{
+    static constexpr std::array<const uint32_t, 40> reg_byte_offsets{
-        {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145}};
+    	{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,160}};
 
     static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
 
     enum sreg_flag_e { FLAGS };
 
     enum mem_type_e { MEM, CSR, FENCE, RES };
-    
-    enum class opcode_e : unsigned short {
-        LUI = 0,
-        AUIPC = 1,
-        JAL = 2,
-        JALR = 3,
-        BEQ = 4,
-        BNE = 5,
-        BLT = 6,
-        BGE = 7,
-        BLTU = 8,
-        BGEU = 9,
-        LB = 10,
-        LH = 11,
-        LW = 12,
-        LBU = 13,
-        LHU = 14,
-        SB = 15,
-        SH = 16,
-        SW = 17,
-        ADDI = 18,
-        SLTI = 19,
-        SLTIU = 20,
-        XORI = 21,
-        ORI = 22,
-        ANDI = 23,
-        SLLI = 24,
-        SRLI = 25,
-        SRAI = 26,
-        ADD = 27,
-        SUB = 28,
-        SLL = 29,
-        SLT = 30,
-        SLTU = 31,
-        XOR = 32,
-        SRL = 33,
-        SRA = 34,
-        OR = 35,
-        AND = 36,
-        FENCE = 37,
-        FENCE_I = 38,
-        ECALL = 39,
-        EBREAK = 40,
-        URET = 41,
-        SRET = 42,
-        MRET = 43,
-        WFI = 44,
-        SFENCE_VMA = 45,
-        CSRRW = 46,
-        CSRRS = 47,
-        CSRRC = 48,
-        CSRRWI = 49,
-        CSRRSI = 50,
-        CSRRCI = 51,
-        MUL = 52,
-        MULH = 53,
-        MULHSU = 54,
-        MULHU = 55,
-        DIV = 56,
-        DIVU = 57,
-        REM = 58,
-        REMU = 59,
-        CADDI4SPN = 60,
-        CLW = 61,
-        CSW = 62,
-        CADDI = 63,
-        CNOP = 64,
-        CJAL = 65,
-        CLI = 66,
-        CLUI = 67,
-        CADDI16SP = 68,
-        CSRLI = 69,
-        CSRAI = 70,
-        CANDI = 71,
-        CSUB = 72,
-        CXOR = 73,
-        COR = 74,
-        CAND = 75,
-        CJ = 76,
-        CBEQZ = 77,
-        CBNEZ = 78,
-        CSLLI = 79,
-        CLWSP = 80,
-        CMV = 81,
-        CJR = 82,
-        CADD = 83,
-        CJALR = 84,
-        CEBREAK = 85,
-        CSWSP = 86,
-        DII = 87,
-        MAX_OPCODE
-    };
 };
 
 struct tgf_c: public arch_if {
@@ -222,54 +199,51 @@ struct tgf_c: public arch_if {
     inline uint32_t get_last_branch() { return reg.last_branch; }
 
 protected:
-#pragma pack(push, 1)
+    struct TGF_C_regs {
-    struct TGF_C_regs { 
+        uint32_t X0 = 0;
-        uint32_t X0 = 0; 
+        uint32_t X1 = 0;
-        uint32_t X1 = 0; 
+        uint32_t X2 = 0;
-        uint32_t X2 = 0; 
+        uint32_t X3 = 0;
-        uint32_t X3 = 0; 
+        uint32_t X4 = 0;
-        uint32_t X4 = 0; 
+        uint32_t X5 = 0;
-        uint32_t X5 = 0; 
+        uint32_t X6 = 0;
-        uint32_t X6 = 0; 
+        uint32_t X7 = 0;
-        uint32_t X7 = 0; 
+        uint32_t X8 = 0;
-        uint32_t X8 = 0; 
+        uint32_t X9 = 0;
-        uint32_t X9 = 0; 
+        uint32_t X10 = 0;
-        uint32_t X10 = 0; 
+        uint32_t X11 = 0;
-        uint32_t X11 = 0; 
+        uint32_t X12 = 0;
-        uint32_t X12 = 0; 
+        uint32_t X13 = 0;
-        uint32_t X13 = 0; 
+        uint32_t X14 = 0;
-        uint32_t X14 = 0; 
+        uint32_t X15 = 0;
-        uint32_t X15 = 0; 
+        uint32_t X16 = 0;
-        uint32_t X16 = 0; 
+        uint32_t X17 = 0;
-        uint32_t X17 = 0; 
+        uint32_t X18 = 0;
-        uint32_t X18 = 0; 
+        uint32_t X19 = 0;
-        uint32_t X19 = 0; 
+        uint32_t X20 = 0;
-        uint32_t X20 = 0; 
+        uint32_t X21 = 0;
-        uint32_t X21 = 0; 
+        uint32_t X22 = 0;
-        uint32_t X22 = 0; 
+        uint32_t X23 = 0;
-        uint32_t X23 = 0; 
+        uint32_t X24 = 0;
-        uint32_t X24 = 0; 
+        uint32_t X25 = 0;
-        uint32_t X25 = 0; 
+        uint32_t X26 = 0;
-        uint32_t X26 = 0; 
+        uint32_t X27 = 0;
-        uint32_t X27 = 0; 
+        uint32_t X28 = 0;
-        uint32_t X28 = 0; 
+        uint32_t X29 = 0;
-        uint32_t X29 = 0; 
+        uint32_t X30 = 0;
-        uint32_t X30 = 0; 
+        uint32_t X31 = 0;
-        uint32_t X31 = 0; 
+        uint32_t PC = 0;
-        uint32_t PC = 0; 
+        uint32_t NEXT_PC = 0;
-        uint32_t NEXT_PC = 0; 
+        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
-        uint8_t PRIV = 0;
-        uint32_t trap_state = 0, pending_trap = 0;
         uint64_t icount = 0;
-        uint32_t last_branch;
     } reg;
-#pragma pack(pop)
+
     std::array<address_type, 4> addr_mode;
     
     uint64_t interrupt_sim=0;
 
-    uint32_t get_fcsr(){return 0;}
+	uint32_t get_fcsr(){return 0;}
-    void set_fcsr(uint32_t val){}
+	void set_fcsr(uint32_t val){}
 
 };
 

incl/iss/debugger/riscv_target_adapter.h

@@ -183,8 +183,7 @@ status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t> &data, st
     data.clear();
     avail.clear();
     const uint8_t *reg_base = core->get_regs_base_ptr();
-    auto start_reg=arch::traits<ARCH>::X0;
+    for (size_t reg_no = 0; reg_no < arch::traits<ARCH>::NUM_REGS; ++reg_no) {
-    for (size_t reg_no = start_reg; reg_no < start_reg+33/*arch::traits<ARCH>::NUM_REGS*/; ++reg_no) {
         auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
         unsigned offset = traits<ARCH>::reg_byte_offsets[reg_no];
         for (size_t j = 0; j < reg_width; ++j) {
@@ -211,11 +210,11 @@ status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t> &data, st
 }
 
 template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(const std::vector<uint8_t> &data) {
-    auto start_reg=arch::traits<ARCH>::X0;
+    auto reg_count = arch::traits<ARCH>::NUM_REGS;
     auto *reg_base = core->get_regs_base_ptr();
     auto iter = data.data();
-    for (size_t reg_no = 0; reg_no < start_reg+33/*arch::traits<ARCH>::NUM_REGS*/; ++reg_no) {
+    for (size_t reg_no = 0; reg_no < reg_count; ++reg_no) {
-        auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
+        auto reg_width = arch::traits<ARCH>::reg_bit_widths[static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)] / 8;
         auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
         std::copy(iter, iter + reg_width, reg_base);
         iter += 4;

incl/iss/plugin/cycle_estimate.h

@@ -76,7 +76,7 @@ public:
 
     sync_type get_sync() override { return POST_SYNC; };
 
-    void callback(instr_info_t instr_info, exec_info const&) override;
+    void callback(instr_info_t instr_info) override;
 
 private:
     iss::instrumentation_if *arch_instr;

incl/iss/plugin/instruction_count.h

@@ -69,7 +69,7 @@ public:
 
     sync_type get_sync() override { return POST_SYNC; };
 
-    void callback(instr_info_t, exec_info const&) override;
+    void callback(instr_info_t instr_info) override;
 
 private:
     Json::Value root;

incl/sysc/core_complex.h

@@ -33,10 +33,10 @@
 #ifndef _SYSC_SIFIVE_FE310_H_
 #define _SYSC_SIFIVE_FE310_H_
 
+#include <tlm/scc/scv/tlm_rec_initiator_socket.h>
 #include "tlm/scc/initiator_mixin.h"
 #include "scc/traceable.h"
 #include "scc/utilities.h"
-#include "tlm/scc/scv/tlm_rec_initiator_socket.h"
 #include <cci_configuration>
 #include <tlm>
 #include <tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_core_ifs.h>
@@ -70,7 +70,7 @@ public:
     bool operator!=(const tlm_dmi_ext &o) const { return !operator==(o); }
 };
 
-namespace tgfs {
+namespace SiFive {
 class core_wrapper;
 
 class core_complex : public sc_core::sc_module, public scc::traceable {
@@ -97,7 +97,7 @@ public:
 
     cci::cci_param<uint64_t> reset_address{"reset_address", 0ULL};
 
-    cci::cci_param<std::string> backend{"backend", "interp"};
+    cci::cci_param<std::string> backend{"backend", "tcc"};
 
     cci::cci_param<unsigned short> gdb_server_port{"gdb_server_port", 0};
 

src/iss/.gitignore

@@ -1 +0,0 @@
-/tgf_b.cpp

src/iss/tgf_b.cpp

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017 - 2020 MINRES Technologies GmbH
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -29,48 +29,41 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
-<% 
+ 
-def getRegisterSizes(){
-	def regs = registers.collect{it.size}
-	regs[-1]=64 // correct for NEXT_PC
-	regs+=[32, 32, 64] // append TRAP_STATE, PENDING_TRAP, ICOUNT
-    return regs
-}
-%>
 #include "util/ities.h"
 #include <util/logging.h>
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <iss/arch/tgf_b.h>
 #include <cstdio>
 #include <cstring>
 #include <fstream>
 
 using namespace iss::arch;
 
-constexpr std::array<const char*, ${registers.size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
+constexpr std::array<const char*, 33>    iss::arch::traits<iss::arch::tgf_b>::reg_names;
-constexpr std::array<const char*, ${registers.size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
+constexpr std::array<const char*, 33>    iss::arch::traits<iss::arch::tgf_b>::reg_aliases;
-constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
+constexpr std::array<const uint32_t, 39> iss::arch::traits<iss::arch::tgf_b>::reg_bit_widths;
-constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
+constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgf_b>::reg_byte_offsets;
 
-${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
+tgf_b::tgf_b() {
     reg.icount = 0;
 }
 
-${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
+tgf_b::~tgf_b() = default;
 
-void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
+void tgf_b::reset(uint64_t address) {
-    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
+    for(size_t i=0; i<traits<tgf_b>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<tgf_b>::reg_t),0));
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
-    reg.PRIV=0x3;
     reg.trap_state=0;
+    reg.machine_state=0x3;
     reg.icount=0;
 }
 
-uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
+uint8_t *tgf_b::get_regs_base_ptr() {
 	return reinterpret_cast<uint8_t*>(&reg);
 }
 
-${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
+tgf_b::phys_addr_t tgf_b::virt2phys(const iss::addr_t &pc) {
     return phys_addr_t(pc); // change logical address to physical address
 }
 

src/iss/tgf_c.cpp

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017 - 2020 MINRES Technologies GmbH
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -29,7 +29,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
-
+ 
 #include "util/ities.h"
 #include <util/logging.h>
 #include <iss/arch/tgf_c.h>
@@ -39,10 +39,10 @@
 
 using namespace iss::arch;
 
-constexpr std::array<const char*, 35>    iss::arch::traits<iss::arch::tgf_c>::reg_names;
+constexpr std::array<const char*, 33>    iss::arch::traits<iss::arch::tgf_c>::reg_names;
-constexpr std::array<const char*, 35>    iss::arch::traits<iss::arch::tgf_c>::reg_aliases;
+constexpr std::array<const char*, 33>    iss::arch::traits<iss::arch::tgf_c>::reg_aliases;
-constexpr std::array<const uint32_t, 38> iss::arch::traits<iss::arch::tgf_c>::reg_bit_widths;
+constexpr std::array<const uint32_t, 39> iss::arch::traits<iss::arch::tgf_c>::reg_bit_widths;
-constexpr std::array<const uint32_t, 38> iss::arch::traits<iss::arch::tgf_c>::reg_byte_offsets;
+constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgf_c>::reg_byte_offsets;
 
 tgf_c::tgf_c() {
     reg.icount = 0;
@@ -54,8 +54,8 @@ void tgf_c::reset(uint64_t address) {
     for(size_t i=0; i<traits<tgf_c>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<tgf_c>::reg_t),0));
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
-    reg.PRIV=0x3;
     reg.trap_state=0;
+    reg.machine_state=0x3;
     reg.icount=0;
 }
 

src/main.cpp

@@ -36,9 +36,7 @@
 #include <boost/lexical_cast.hpp>
 #include <boost/program_options.hpp>
 #include <iss/arch/riscv_hart_m_p.h>
-#ifdef WITH_TGF_B
 #include <iss/arch/tgf_b.h>
-#endif
 #include <iss/arch/tgf_c.h>
 #ifdef WITH_LLVM
 #include <iss/llvm/jit_helper.h>
@@ -61,8 +59,8 @@ std::tuple<cpu_ptr, vm_ptr> create_cpu(std::string const& backend, unsigned gdb_
     if(backend == "llvm")
         return {cpu_ptr{lcpu}, vm_ptr{iss::llvm::create(lcpu, gdb_port)}};
 #endif
-//    if(backend == "tcc")
+    if(backend == "tcc")
-//        return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
+        return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
     return {nullptr, nullptr};
 }
 
@@ -85,7 +83,7 @@ int main(int argc, char *argv[]) {
         ("elf", po::value<std::vector<std::string>>(), "ELF file(s) to load")
         ("mem,m", po::value<std::string>(), "the memory input file")
         ("plugin,p", po::value<std::vector<std::string>>(), "plugin to activate")
-        ("backend", po::value<std::string>()->default_value("interp"), "the memory input file")
+        ("backend", po::value<std::string>()->default_value("tcc"), "the memory input file")
         ("isa", po::value<std::string>()->default_value("tgf_c"), "isa to use for simulation");
     // clang-format on
     auto parsed = po::command_line_parser(argc, argv).options(desc).allow_unregistered().run();
@@ -131,13 +129,10 @@ int main(int argc, char *argv[]) {
         vm_ptr vm{nullptr};
         cpu_ptr cpu{nullptr};
         std::string isa_opt(clim["isa"].as<std::string>());
-#ifdef WITH_TGF_B
         if (isa_opt == "tgf_b") {
             std::tie(cpu, vm) =
                 create_cpu<iss::arch::tgf_b>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
-        } else
+        } else if (isa_opt == "tgf_c") {
-#endif
-            if (isa_opt == "tgf_c") {
             std::tie(cpu, vm) =
                 create_cpu<iss::arch::tgf_c>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
         } else {
@@ -179,7 +174,7 @@ int main(int argc, char *argv[]) {
         }
         uint64_t start_address = 0;
         if (clim.count("mem"))
-            vm->get_arch()->load_file(clim["mem"].as<std::string>(), iss::arch::traits<iss::arch::tgf_c>::MEM);
+            vm->get_arch()->load_file(clim["mem"].as<std::string>(), iss::arch::traits<iss::arch::tgf_b>::MEM);
         if (clim.count("elf"))
             for (std::string input : clim["elf"].as<std::vector<std::string>>()) {
                 auto start_addr = vm->get_arch()->load_file(input);

src/plugin/cycle_estimate.cpp

@@ -83,7 +83,7 @@ bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if&
 
 }
 
-void iss::plugin::cycle_estimate::callback(instr_info_t instr_info, exec_info const&) {
+void iss::plugin::cycle_estimate::callback(instr_info_t instr_info) {
     assert(arch_instr && "No instrumentation interface available but callback executed");
 	auto entry = delays[instr_info.instr_id];
 	bool taken = (arch_instr->get_next_pc()-arch_instr->get_pc()) != (entry.size/8);

src/plugin/instruction_count.cpp

@@ -90,6 +90,6 @@ bool iss::plugin::instruction_count::registration(const char* const version, vm_
 	return true;
 }
 
-void iss::plugin::instruction_count::callback(instr_info_t instr_info, exec_info const&) {
+void iss::plugin::instruction_count::callback(instr_info_t instr_info) {
 	rep_counts[instr_info.instr_id]++;
 }

src/sysc/core_complex.cpp

@@ -49,7 +49,7 @@
 #endif
 
 namespace sysc {
-namespace tgfs {
+namespace SiFive {
 using namespace std;
 using namespace iss;
 using namespace logging;
@@ -96,7 +96,7 @@ public:
     core_wrapper(core_complex *owner)
     : owner(owner) { }
 
-    uint32_t get_mode() { return this->reg.PRIV; }
+    uint32_t get_mode() { return this->reg.machine_state; }
 
     inline void set_interrupt_execution(bool v) { this->interrupt_sim = v?1:0; }
 
@@ -113,7 +113,7 @@ public:
     void disass_output(uint64_t pc, const std::string instr) override {
         if (INFO <= Log<Output2FILE<disass>>::reporting_level() && Output2FILE<disass>::stream()) {
             std::stringstream s;
-            s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0')
+            s << "[p:" << lvl[this->reg.machine_state] << ";s:0x" << std::hex << std::setfill('0')
               << std::setw(sizeof(reg_t) * 2) << (reg_t)state.mstatus << std::dec << ";c:" << this->reg.icount << "]";
             Log<Output2FILE<disass>>().get(INFO, "disass")
                 << "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
@@ -191,8 +191,6 @@ public:
         } else
             this->csr[arch::mip] &= ~mask;
         this->check_interrupt();
-        if(value)
-            SCCTRACE(owner->name()) << "Triggering interrupt " << id << " Pending trap: " << this->reg.pending_trap;
     }
 
 private:
@@ -279,10 +277,8 @@ vm_ptr create_cpu(core_wrapper* cpu, std::string const& backend, unsigned gdb_po
     if(backend == "llvm")
         return vm_ptr{iss::llvm::create(lcpu, gdb_port)};
 #endif
-#ifdef WITH_TCC
     if(backend == "tcc")
         return vm_ptr{iss::tcc::create<core_type>(cpu, gdb_port)};
-#endif
     return {nullptr};
 }
 
@@ -292,7 +288,6 @@ void core_complex::before_end_of_elaboration() {
     cpu->set_mhartid(mhartid.get_value());
 
     vm = create_cpu(cpu.get(), backend.get_value(), gdb_server_port.get_value());
-    sc_assert(vm!=nullptr);
 #ifdef WITH_SCV
     vm->setDisassEnabled(enable_disass.get_value() || m_db != nullptr);
 #else
@@ -393,7 +388,7 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data,
             if (is_fetch && tr_handle.is_active()) {
                 tr_handle.end_transaction();
             }
-            auto preExt = new tlm::scc::scv::tlm_recording_extension(tr_handle, this);
+            auto preExt = new tlm::scc::scv4tlm::tlm_recording_extension(tr_handle, this);
             gp.set_extension(preExt);
         }
 #endif
@@ -439,7 +434,7 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
         sc_time delay{quantum_keeper.get_local_time()};
 #ifdef WITH_SCV
         if (m_db != nullptr && tr_handle.is_valid()) {
-            auto preExt = new tlm::scc::scv::tlm_recording_extension(tr_handle, this);
+            auto preExt = new tlm::scc::scv4tlm::tlm_recording_extension(tr_handle, this);
             gp.set_extension(preExt);
         }
 #endif

src/vm/interp/.gitignore

@@ -1 +0,0 @@
-/vm_tgf_b.cpp

src/vm/tcc/vm_tgf_b.cpp

@@ -377,6 +377,7 @@ private:
         auto is_cont_v = tu.choose(
             tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
             tu.constant(0U, 32), tu.constant(1U, 32));
+        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
         tu.close_scope();
         vm_base<ARCH>::gen_sync(tu, POST_SYNC, 2);
         gen_trap_check(tu);
@@ -423,6 +424,7 @@ private:
             new_pc_val,
             tu.l_not(tu.constant(0x1, 32U))), 32);
         tu.store(PC_val_v, traits<ARCH>::NEXT_PC);
+        tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32U), traits<ARCH>::LAST_BRANCH);
         tu.close_scope();
         tu.close_scope();
         vm_base<ARCH>::gen_sync(tu, POST_SYNC, 3);
@@ -464,6 +466,7 @@ private:
         auto is_cont_v = tu.choose(
             tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
             tu.constant(0U, 32), tu.constant(1U, 32));
+        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
         tu.close_scope();
         vm_base<ARCH>::gen_sync(tu, POST_SYNC, 4);
         gen_trap_check(tu);
@@ -504,6 +507,7 @@ private:
         auto is_cont_v = tu.choose(
             tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
             tu.constant(0U, 32), tu.constant(1U, 32));
+        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
         tu.close_scope();
         vm_base<ARCH>::gen_sync(tu, POST_SYNC, 5);
         gen_trap_check(tu);
@@ -548,6 +552,7 @@ private:
         auto is_cont_v = tu.choose(
             tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
             tu.constant(0U, 32), tu.constant(1U, 32));
+        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
         tu.close_scope();
         vm_base<ARCH>::gen_sync(tu, POST_SYNC, 6);
         gen_trap_check(tu);
@@ -592,6 +597,7 @@ private:
         auto is_cont_v = tu.choose(
             tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
             tu.constant(0U, 32), tu.constant(1U, 32));
+        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
         tu.close_scope();
         vm_base<ARCH>::gen_sync(tu, POST_SYNC, 7);
         gen_trap_check(tu);
@@ -632,6 +638,7 @@ private:
         auto is_cont_v = tu.choose(
             tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
             tu.constant(0U, 32), tu.constant(1U, 32));
+        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
         tu.close_scope();
         vm_base<ARCH>::gen_sync(tu, POST_SYNC, 8);
         gen_trap_check(tu);
@@ -672,6 +679,7 @@ private:
         auto is_cont_v = tu.choose(
             tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
             tu.constant(0U, 32), tu.constant(1U, 32));
+        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
         tu.close_scope();
         vm_base<ARCH>::gen_sync(tu, POST_SYNC, 9);
         gen_trap_check(tu);
@@ -1613,6 +1621,7 @@ private:
             tu.constant(1, 64U),
             tu.trunc(tu.constant(imm, 32U), 32));
         tu.close_scope();
+        tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
         gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
         vm_base<ARCH>::gen_sync(tu, POST_SYNC, 38);
         gen_trap_check(tu);
@@ -2046,11 +2055,13 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
 
 template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) {
     tu("  *trap_state = {:#x};", 0x80 << 24 | (cause << 16) | trap_id);
+    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
 }
 
 template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsigned lvl) {
     tu("leave_trap(core_ptr, {});", lvl);
     tu.store(tu.read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN),traits<ARCH>::NEXT_PC);
+    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
 }
 
 template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned type) {
@@ -2059,6 +2070,7 @@ template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned t
 template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
     tu("trap_entry:");
     tu("enter_trap(core_ptr, *trap_state, *pc);");
+    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(),32),traits<ARCH>::LAST_BRANCH);
     tu("return *next_pc;");
 }
 

src/vm/tcc/vm_tgf_c.cpp

@@ -449,6 +449,7 @@ private:
         auto is_cont_v = tu.choose(
             tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
             tu.constant(0U, 32), tu.constant(1U, 32));
+        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
         tu.close_scope();
         vm_base<ARCH>::gen_sync(tu, POST_SYNC, 2);
         gen_trap_check(tu);
@@ -486,6 +487,7 @@ private:
             new_pc_val,
             tu.l_not(tu.constant(0x1, 32U))), 32);
         tu.store(PC_val_v, traits<ARCH>::NEXT_PC);
+        tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32U), traits<ARCH>::LAST_BRANCH);
         tu.close_scope();
         vm_base<ARCH>::gen_sync(tu, POST_SYNC, 3);
         gen_trap_check(tu);
@@ -526,6 +528,7 @@ private:
         auto is_cont_v = tu.choose(
             tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
             tu.constant(0U, 32), tu.constant(1U, 32));
+        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
         tu.close_scope();
         vm_base<ARCH>::gen_sync(tu, POST_SYNC, 4);
         gen_trap_check(tu);
@@ -566,6 +569,7 @@ private:
         auto is_cont_v = tu.choose(
             tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
             tu.constant(0U, 32), tu.constant(1U, 32));
+        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
         tu.close_scope();
         vm_base<ARCH>::gen_sync(tu, POST_SYNC, 5);
         gen_trap_check(tu);
@@ -610,6 +614,7 @@ private:
         auto is_cont_v = tu.choose(
             tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
             tu.constant(0U, 32), tu.constant(1U, 32));
+        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
         tu.close_scope();
         vm_base<ARCH>::gen_sync(tu, POST_SYNC, 6);
         gen_trap_check(tu);
@@ -654,6 +659,7 @@ private:
         auto is_cont_v = tu.choose(
             tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
             tu.constant(0U, 32), tu.constant(1U, 32));
+        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
         tu.close_scope();
         vm_base<ARCH>::gen_sync(tu, POST_SYNC, 7);
         gen_trap_check(tu);
@@ -694,6 +700,7 @@ private:
         auto is_cont_v = tu.choose(
             tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
             tu.constant(0U, 32), tu.constant(1U, 32));
+        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
         tu.close_scope();
         vm_base<ARCH>::gen_sync(tu, POST_SYNC, 8);
         gen_trap_check(tu);
@@ -734,6 +741,7 @@ private:
         auto is_cont_v = tu.choose(
             tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
             tu.constant(0U, 32), tu.constant(1U, 32));
+        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
         tu.close_scope();
         vm_base<ARCH>::gen_sync(tu, POST_SYNC, 9);
         gen_trap_check(tu);
@@ -1675,6 +1683,7 @@ private:
             tu.constant(1, 64U),
             tu.trunc(tu.constant(imm, 32U), 32));
         tu.close_scope();
+        tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
         gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
         vm_base<ARCH>::gen_sync(tu, POST_SYNC, 38);
         gen_trap_check(tu);
@@ -2553,6 +2562,7 @@ private:
         auto is_cont_v = tu.choose(
             tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
             tu.constant(0U, 32), tu.constant(1U, 32));
+        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
         tu.close_scope();
         vm_base<ARCH>::gen_sync(tu, POST_SYNC, 65);
         gen_trap_check(tu);
@@ -2858,6 +2868,7 @@ private:
         auto is_cont_v = tu.choose(
             tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
             tu.constant(0U, 32), tu.constant(1U, 32));
+        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
         tu.close_scope();
         vm_base<ARCH>::gen_sync(tu, POST_SYNC, 76);
         gen_trap_check(tu);
@@ -2897,6 +2908,7 @@ private:
         auto is_cont_v = tu.choose(
             tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
             tu.constant(0U, 32), tu.constant(1U, 32));
+        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
         tu.close_scope();
         vm_base<ARCH>::gen_sync(tu, POST_SYNC, 77);
         gen_trap_check(tu);
@@ -2936,6 +2948,7 @@ private:
         auto is_cont_v = tu.choose(
             tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
             tu.constant(0U, 32), tu.constant(1U, 32));
+        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
         tu.close_scope();
         vm_base<ARCH>::gen_sync(tu, POST_SYNC, 78);
         gen_trap_check(tu);
@@ -3042,6 +3055,7 @@ private:
         tu.open_scope();
         auto PC_val_v = tu.assignment("PC_val", tu.load(rs1 + traits<ARCH>::X0, 0), 32);
         tu.store(PC_val_v, traits<ARCH>::NEXT_PC);
+        tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32U), traits<ARCH>::LAST_BRANCH);
         tu.close_scope();
         vm_base<ARCH>::gen_sync(tu, POST_SYNC, 82);
         gen_trap_check(tu);
@@ -3094,6 +3108,7 @@ private:
             tu.constant(2, 32U)), 1 + traits<ARCH>::X0);
         auto PC_val_v = tu.assignment("PC_val", tu.load(rs1 + traits<ARCH>::X0, 0), 32);
         tu.store(PC_val_v, traits<ARCH>::NEXT_PC);
+        tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32U), traits<ARCH>::LAST_BRANCH);
         tu.close_scope();
         vm_base<ARCH>::gen_sync(tu, POST_SYNC, 84);
         gen_trap_check(tu);
@@ -3232,11 +3247,13 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
 
 template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) {
     tu("  *trap_state = {:#x};", 0x80 << 24 | (cause << 16) | trap_id);
+    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
 }
 
 template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsigned lvl) {
     tu("leave_trap(core_ptr, {});", lvl);
     tu.store(tu.read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN),traits<ARCH>::NEXT_PC);
+    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
 }
 
 template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned type) {
@@ -3245,6 +3262,7 @@ template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned t
 template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
     tu("trap_entry:");
     tu("enter_trap(core_ptr, *trap_state, *pc);");
+    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(),32),traits<ARCH>::LAST_BRANCH);
     tu("return *next_pc;");
 }