fixes missing namespaces

.clang-format

@@ -1,3 +1,4 @@
+---
 Language:        Cpp
 # BasedOnStyle:  LLVM
 # should be in line with IndentWidth
@@ -12,8 +13,8 @@ AllowAllParametersOfDeclarationOnNextLine: true
 AllowShortBlocksOnASingleLine: false
 AllowShortCaseLabelsOnASingleLine: false
 AllowShortFunctionsOnASingleLine: All
-AllowShortIfStatementsOnASingleLine: false
+AllowShortIfStatementsOnASingleLine: true
-AllowShortLoopsOnASingleLine: false
+AllowShortLoopsOnASingleLine: true
 AlwaysBreakAfterDefinitionReturnType: None
 AlwaysBreakAfterReturnType: None
 AlwaysBreakBeforeMultilineStrings: false
@@ -38,8 +39,8 @@ BreakBeforeTernaryOperators: true
 BreakConstructorInitializersBeforeComma: true
 BreakAfterJavaFieldAnnotations: false
 BreakStringLiterals: true
-ColumnLimit:     140
+ColumnLimit:     120
-CommentPragmas:  '^( IWYU pragma:| @suppress)'
+CommentPragmas:  '^ IWYU pragma:'
 ConstructorInitializerAllOnOneLineOrOnePerLine: false
 ConstructorInitializerIndentWidth: 0
 ContinuationIndentWidth: 4
@@ -75,13 +76,13 @@ PenaltyBreakFirstLessLess: 120
 PenaltyBreakString: 1000
 PenaltyExcessCharacter: 1000000
 PenaltyReturnTypeOnItsOwnLine: 60
-PointerAlignment: Left
+PointerAlignment: Right
 ReflowComments:  true
 SortIncludes:    true
 SpaceAfterCStyleCast: false
 SpaceAfterTemplateKeyword: true
 SpaceBeforeAssignmentOperators: true
-SpaceBeforeParens: Never
+SpaceBeforeParens: ControlStatements
 SpaceInEmptyParentheses: false
 SpacesBeforeTrailingComments: 1
 SpacesInAngles:  false

.gitignore

@@ -1,6 +1,5 @@
 .DS_Store
 /*.il
-/.settings
 /avr-instr.html
 /blink.S
 /flash.*
@@ -15,6 +14,7 @@
 /*.ods
 /build*/
 /*.logs
+language.settings.xml
 /*.gtkw
 /Debug wo LLVM/
 /*.txdb

.settings/org.eclipse.cdt.codan.core.prefs

@@ -0,0 +1,73 @@
+eclipse.preferences.version=1
+org.eclipse.cdt.codan.checkers.errnoreturn=Warning
+org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return\\")",implicit\=>false}
+org.eclipse.cdt.codan.checkers.errreturnvalue=Error
+org.eclipse.cdt.codan.checkers.errreturnvalue.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused return value\\")"}
+org.eclipse.cdt.codan.checkers.nocommentinside=-Error
+org.eclipse.cdt.codan.checkers.nocommentinside.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Nesting comments\\")"}
+org.eclipse.cdt.codan.checkers.nolinecomment=-Error
+org.eclipse.cdt.codan.checkers.nolinecomment.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Line comments\\")"}
+org.eclipse.cdt.codan.checkers.noreturn=Error
+org.eclipse.cdt.codan.checkers.noreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return value\\")",implicit\=>false}
+org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation=Error
+org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Abstract class cannot be instantiated\\")"}
+org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem=Error
+org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Ambiguous problem\\")"}
+org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment in condition\\")"}
+org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem=Error
+org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment to itself\\")"}
+org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No break at end of case\\")",no_break_comment\=>"no break",last_case_param\=>false,empty_case_param\=>false,enable_fallthrough_quickfix_param\=>false}
+org.eclipse.cdt.codan.internal.checkers.CatchByReference=Warning
+org.eclipse.cdt.codan.internal.checkers.CatchByReference.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Catching by reference is recommended\\")",unknown\=>false,exceptions\=>()}
+org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem=Error
+org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Circular inheritance\\")"}
+org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization=Warning
+org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class members should be properly initialized\\")",skip\=>true}
+org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem=Error
+org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid 'decltype(auto)' specifier\\")"}
+org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Field cannot be resolved\\")"}
+org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Function cannot be resolved\\")"}
+org.eclipse.cdt.codan.internal.checkers.InvalidArguments=Error
+org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid arguments\\")"}
+org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem=Error
+org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid template argument\\")"}
+org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem=Error
+org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Label statement not found\\")"}
+org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem=Error
+org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Member declaration not found\\")"}
+org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Method cannot be resolved\\")"}
+org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker=-Info
+org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Name convention for function\\")",pattern\=>"^[a-z]",macro\=>true,exceptions\=>()}
+org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class has a virtual method and non-virtual destructor\\")"}
+org.eclipse.cdt.codan.internal.checkers.OverloadProblem=Error
+org.eclipse.cdt.codan.internal.checkers.OverloadProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid overload\\")"}
+org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem=Error
+org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redeclaration\\")"}
+org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redefinition\\")"}
+org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem=-Warning
+org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Return with parenthesis\\")"}
+org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem=-Warning
+org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Format String Vulnerability\\")"}
+org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Statement has no effect\\")",macro\=>true,exceptions\=>()}
+org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suggested parenthesis around expression\\")",paramNot\=>false}
+org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suspicious semicolon\\")",else\=>false,afterelse\=>false}
+org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Type cannot be resolved\\")"}
+org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused function declaration\\")",macro\=>true}
+org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused static function\\")",macro\=>true}
+org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused variable declaration in file scope\\")",macro\=>true,exceptions\=>("@(\#)","$Id")}
+org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol is not resolved\\")"}

.settings/org.eclipse.cdt.core.prefs

@@ -0,0 +1,13 @@
+eclipse.preferences.version=1
+environment/project/cdt.managedbuild.config.gnu.exe.debug.1751741082/append=true
+environment/project/cdt.managedbuild.config.gnu.exe.debug.1751741082/appendContributed=true
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/LLVM_HOME/delimiter=\:
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/LLVM_HOME/operation=append
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/LLVM_HOME/value=/usr/lib/llvm-6.0
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/append=true
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/appendContributed=true
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/LLVM_HOME/delimiter=\:
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/LLVM_HOME/operation=append
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/LLVM_HOME/value=/usr/lib/llvm-6.0
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/append=true
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/appendContributed=true

.settings/org.eclipse.cdt.managedbuilder.core.prefs

@@ -0,0 +1,37 @@
+eclipse.preferences.version=1
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/CPATH/delimiter=\:
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/CPATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/CPLUS_INCLUDE_PATH/delimiter=\:
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/CPLUS_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/C_INCLUDE_PATH/delimiter=\:
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/C_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/append=true
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/appendContributed=true
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/CPATH/delimiter=\:
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/CPATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/CPLUS_INCLUDE_PATH/delimiter=\:
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/CPLUS_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/C_INCLUDE_PATH/delimiter=\:
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/C_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/append=true
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/appendContributed=true
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/CPATH/delimiter=\:
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/CPATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/CPLUS_INCLUDE_PATH/delimiter=\:
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/CPLUS_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/C_INCLUDE_PATH/delimiter=\:
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/C_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/append=true
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/appendContributed=true
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.debug.1751741082/LIBRARY_PATH/delimiter=\:
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.debug.1751741082/LIBRARY_PATH/operation=remove
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.debug.1751741082/append=true
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.debug.1751741082/appendContributed=true
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/LIBRARY_PATH/delimiter=\:
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/LIBRARY_PATH/operation=remove
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/append=true
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/appendContributed=true
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171/LIBRARY_PATH/delimiter=\:
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171/LIBRARY_PATH/operation=remove
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171/append=true
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171/appendContributed=true

CMakeLists.txt

@@ -1,123 +1,114 @@
-cmake_minimum_required(VERSION 3.18)
+cmake_minimum_required(VERSION 3.12)
-list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/cmake)
-
 ###############################################################################
 #
 ###############################################################################
 project(dbt-rise-tgc VERSION 1.0.0)
 
 include(GNUInstallDirs)
-include(flink)
 
 find_package(elfio QUIET)
+find_package(Boost COMPONENTS coroutine)
 find_package(jsoncpp)
-find_package(Boost COMPONENTS coroutine REQUIRED)
+
+if(WITH_LLVM)
+    if(DEFINED ENV{LLVM_HOME})
+        find_path (LLVM_DIR LLVM-Config.cmake $ENV{LLVM_HOME}/lib/cmake/llvm)
+    endif(DEFINED ENV{LLVM_HOME})
+    find_package(LLVM REQUIRED CONFIG)
+    message(STATUS "Found LLVM ${LLVM_PACKAGE_VERSION}")
+    message(STATUS "Using LLVMConfig.cmake in: ${LLVM_DIR}")
+    llvm_map_components_to_libnames(llvm_libs support core mcjit x86codegen x86asmparser)
+endif()
+
+#Mac needed variables (adapt for your needs - http://www.cmake.org/Wiki/CMake_RPATH_handling#Mac_OS_X_and_the_RPATH)
+#set(CMAKE_MACOSX_RPATH ON)
+#set(CMAKE_SKIP_BUILD_RPATH FALSE)
+#set(CMAKE_BUILD_WITH_INSTALL_RPATH FALSE)
+#set(CMAKE_INSTALL_RPATH "${CMAKE_INSTALL_PREFIX}/lib")
+#set(CMAKE_INSTALL_RPATH_USE_LINK_PATH TRUE)
 
 add_subdirectory(softfloat)
 
 set(LIB_SOURCES 
     src/iss/plugin/instruction_count.cpp
-    src/iss/arch/tgc5c.cpp
+	src/iss/arch/tgc_c.cpp
-    src/vm/interp/vm_tgc5c.cpp
+	src/vm/interp/vm_tgc_c.cpp
 	src/vm/fp_functions.cpp
-    src/iss/debugger/csr_names.cpp
-    src/iss/semihosting/semihosting.cpp
 )
 
-if(WITH_TCC)
-    list(APPEND LIB_SOURCES
-        src/vm/tcc/vm_tgc5c.cpp
-    )
-endif()
-
-if(WITH_LLVM)
-    list(APPEND LIB_SOURCES
-        src/vm/llvm/vm_tgc5c.cpp
-        src/vm/llvm/fp_impl.cpp
-    )
-endif()
-
-if(WITH_ASMJIT)
-    list(APPEND LIB_SOURCES
-        src/vm/asmjit/vm_tgc5c.cpp
-    )
-endif()
-
 # library files
+if(TARGET ${CORE_NAME}_cpp)
+    list(APPEND LIB_SOURCES ${${CORE_NAME}_OUTPUT_FILES})
+else()
     FILE(GLOB GEN_ISS_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp)
     FILE(GLOB GEN_VM_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp)
-FILE(GLOB GEN_YAML_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/contrib/instr/*.yaml)
     list(APPEND LIB_SOURCES ${GEN_ISS_SOURCES} ${GEN_VM_SOURCES})
-
     foreach(FILEPATH ${GEN_ISS_SOURCES})
         get_filename_component(CORE ${FILEPATH} NAME_WE)
         string(TOUPPER ${CORE} CORE)
         list(APPEND LIB_DEFINES CORE_${CORE})
     endforeach()
+    message("Defines are ${LIB_DEFINES}")
+endif()
 
-message(STATUS "Core defines are ${LIB_DEFINES}")
+if(TARGET RapidJSON OR TARGET RapidJSON::RapidJSON)
+    list(APPEND LIB_SOURCES src/iss/plugin/cycle_estimate.cpp src/iss/plugin/pctrace.cpp)
+endif()
 
 if(WITH_LLVM)
-    FILE(GLOB LLVM_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/llvm/vm_*.cpp)
+	FILE(GLOB LLVM_GEN_SOURCES
+	    ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/llvm/vm_*.cpp
+	)
 	list(APPEND LIB_SOURCES ${LLVM_GEN_SOURCES})
 endif()
 
 if(WITH_TCC)
-    FILE(GLOB TCC_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/tcc/vm_*.cpp)
+	FILE(GLOB TCC_GEN_SOURCES
-    list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
+	    ${CMAKE_CURRENT_SOURCE_DIR}/src/vm/tcc/vm_*.cpp
-endif()
-
-if(WITH_ASMJIT)
-    FILE(GLOB TCC_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/asmjit/vm_*.cpp)
-    list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
-endif()
-
-if(TARGET yaml-cpp::yaml-cpp)
-    list(APPEND LIB_SOURCES
-        src/iss/plugin/cycle_estimate.cpp
-        src/iss/plugin/instruction_count.cpp
 	)
+	list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
 endif()
 
 # Define the library
-add_library(${PROJECT_NAME} SHARED ${LIB_SOURCES})
+add_library(${PROJECT_NAME} ${LIB_SOURCES})
+# list code gen dependencies
+if(TARGET ${CORE_NAME}_cpp)
+    add_dependencies(${PROJECT_NAME} ${CORE_NAME}_cpp)
+endif()
 
 if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
      target_compile_options(${PROJECT_NAME} PRIVATE -Wno-shift-count-overflow)
 elseif("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC")
     target_compile_options(${PROJECT_NAME} PRIVATE /wd4293)
 endif()
-
 target_include_directories(${PROJECT_NAME} PUBLIC src)
 target_include_directories(${PROJECT_NAME} PUBLIC src-gen)
-
+target_link_libraries(${PROJECT_NAME} PUBLIC softfloat scc-util Boost::coroutine)
-target_force_link_libraries(${PROJECT_NAME} PRIVATE dbt-rise-core)
+if(TARGET jsoncpp::jsoncpp)
-
+	target_link_libraries(${PROJECT_NAME} PUBLIC jsoncpp::jsoncpp)
-# only re-export the include paths
+else()
-get_target_property(DBT_CORE_INCL dbt-rise-core INTERFACE_INCLUDE_DIRECTORIES)
+	target_link_libraries(${PROJECT_NAME} PUBLIC jsoncpp)
-target_include_directories(${PROJECT_NAME} INTERFACE ${DBT_CORE_INCL})
+endif()
-get_target_property(DBT_CORE_DEFS dbt-rise-core INTERFACE_COMPILE_DEFINITIONS)
+if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU" AND BUILD_SHARED_LIBS)
-
+    target_link_libraries(${PROJECT_NAME} PUBLIC -Wl,--whole-archive dbt-rise-core -Wl,--no-whole-archive)
-if(NOT(DBT_CORE_DEFS STREQUAL DBT_CORE_DEFS-NOTFOUND))
+else()
-    target_compile_definitions(${PROJECT_NAME} INTERFACE ${DBT_CORE_DEFS})
+    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-core)
+endif()
+if(TARGET elfio::elfio)
+    target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio)
+else()
+    message(FATAL_ERROR "No elfio library found, maybe a find_package() call is missing")
+endif()
+if(TARGET lz4::lz4)
+    target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_LZ4)
+    target_link_libraries(${PROJECT_NAME} PUBLIC lz4::lz4)
+endif()
+if(TARGET RapidJSON::RapidJSON)
+    target_link_libraries(${PROJECT_NAME} PUBLIC RapidJSON::RapidJSON)
+elseif(TARGET RapidJSON)
+    target_link_libraries(${PROJECT_NAME} PUBLIC RapidJSON)
 endif()
 
-target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio softfloat scc-util Boost::coroutine)
-
-if(TARGET yaml-cpp::yaml-cpp)
-    target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_PLUGINS)
-    target_link_libraries(${PROJECT_NAME} PUBLIC yaml-cpp::yaml-cpp)
-endif()
-
-if(WITH_LLVM)
-    find_package(LLVM)
-    target_compile_definitions(${PROJECT_NAME} PUBLIC ${LLVM_DEFINITIONS})
-    target_include_directories(${PROJECT_NAME} PUBLIC ${LLVM_INCLUDE_DIRS})
-
-    if(BUILD_SHARED_LIBS)
-        target_link_libraries(${PROJECT_NAME} PUBLIC ${LLVM_LIBRARIES})
-    endif()
-endif()
 
 set_target_properties(${PROJECT_NAME} PROPERTIES
   VERSION ${PROJECT_VERSION}
@@ -137,17 +128,13 @@ install(DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss COMPONENT ${PROJECT_NAME}
         FILES_MATCHING # install only matched files
         PATTERN "*.h" # select header files
         )
-install(FILES ${GEN_YAML_SOURCES} DESTINATION share/tgc-vp)
-
 ###############################################################################
 #
 ###############################################################################
-set(CMAKE_INSTALL_RPATH $ORIGIN/../${CMAKE_INSTALL_LIBDIR})
 project(tgc-sim)
 find_package(Boost COMPONENTS program_options thread REQUIRED)
 
 add_executable(${PROJECT_NAME} src/main.cpp)
-
 if(TARGET ${CORE_NAME}_cpp)
     list(APPEND TGC_SOURCES ${${CORE_NAME}_OUTPUT_FILES})
 else()
@@ -166,23 +153,21 @@ foreach(F IN LISTS TGC_SOURCES)
     endif()
 endforeach()
 
-# if(WITH_LLVM)
+if(WITH_LLVM)
-# target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_LLVM)
+    target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_LLVM)
-# #target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
+    target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
-# endif()
+endif()
-# if(WITH_TCC)
+if(WITH_TCC)
-# target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_TCC)
+    target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_TCC)
-# endif()
+endif()
-target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc fmt::fmt)
+# Links the target exe against the libraries
-
+target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc)
 if(TARGET Boost::program_options)
     target_link_libraries(${PROJECT_NAME} PUBLIC Boost::program_options)
 else()
     target_link_libraries(${PROJECT_NAME} PUBLIC ${BOOST_program_options_LIBRARY})
 endif()
-
 target_link_libraries(${PROJECT_NAME} PUBLIC ${CMAKE_DL_LIBS})
-
 if (Tcmalloc_FOUND)
     target_link_libraries(${PROJECT_NAME} PUBLIC ${Tcmalloc_LIBRARIES})
 endif(Tcmalloc_FOUND)
@@ -196,43 +181,17 @@ install(TARGETS tgc-sim
   PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME}  # headers for mac (note the different component -> different package)
   INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}             # headers
 )
-
-if(BUILD_TESTING)
-    # ... CMake code to create tests ...
-    add_test(NAME tgc-sim-interp
-        COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend interp)
-
-    if(WITH_TCC)
-        add_test(NAME tgc-sim-tcc
-            COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend tcc)
-    endif()
-
-    if(WITH_LLVM)
-        add_test(NAME tgc-sim-llvm
-            COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend llvm)
-    endif()
-
-    if(WITH_ASMJIT)
-        add_test(NAME tgc-sim-asmjit
-            COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend asmjit)
-    endif()
-endif()
-
 ###############################################################################
 #
 ###############################################################################
 if(TARGET scc-sysc)
 	project(dbt-rise-tgc_sc VERSION 1.0.0)
-    set(LIB_SOURCES
+    add_library(${PROJECT_NAME} 
     	src/sysc/core_complex.cpp
     	src/sysc/register_tgc_c.cpp
     )
-    FILE(GLOB GEN_SC_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/sysc/register_*.cpp)
-    list(APPEND LIB_SOURCES ${GEN_SC_SOURCES})
-    add_library(${PROJECT_NAME} ${LIB_SOURCES})
     target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_SYSTEMC)
     target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
-
     foreach(F IN LISTS TGC_SOURCES)
         if (${F} MATCHES ".*/arch/([^/]*)\.cpp")
             string(REGEX REPLACE  ".*/([^/]*)\.cpp"  "\\1" CORE_NAME_LC ${F})
@@ -240,12 +199,11 @@ if(TARGET scc-sysc)
             target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
         endif()
     endforeach()
-
     target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc-sysc)
+    if(WITH_LLVM)
+        target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
+    endif()
     
-    # if(WITH_LLVM)
-    # target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
-    # endif()
 	set(LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/src/sysc/core_complex.h)
     set_target_properties(${PROJECT_NAME} PROPERTIES
       VERSION ${PROJECT_VERSION}
@@ -262,3 +220,4 @@ if(TARGET scc-sysc)
 	  INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}             # headers
 	)    
 endif()
+

TGC_C_instr.yaml

@@ -1,623 +1,536 @@
 
-RVI: 
+RV32I: 
-  LUI:
+  - LUI:
-    index: 0
     encoding: 0b00000000000000000000000000110111
     mask: 0b00000000000000000000000001111111
     size:   32
     branch:   false
     delay:   1
-  AUIPC:
+  - AUIPC:
-    index: 1
     encoding: 0b00000000000000000000000000010111
     mask: 0b00000000000000000000000001111111
     size:   32
     branch:   false
     delay:   1
-  JAL:
+  - JAL:
-    index: 2
     encoding: 0b00000000000000000000000001101111
     mask: 0b00000000000000000000000001111111
+    attributes: [[name:no_cont]]
     size:   32
     branch:   true
     delay:   1
-  JALR:
+  - JALR:
-    index: 3
     encoding: 0b00000000000000000000000001100111
     mask: 0b00000000000000000111000001111111
+    attributes: [[name:no_cont]]
     size:   32
     branch:   true
-    delay:   [1,1]
+    delay:   1
-  BEQ:
+  - BEQ:
-    index: 4
     encoding: 0b00000000000000000000000001100011
     mask: 0b00000000000000000111000001111111
+    attributes: [[name:no_cont], [name:cond]]
     size:   32
     branch:   true
     delay:   [1,1]
-  BNE:
+  - BNE:
-    index: 5
     encoding: 0b00000000000000000001000001100011
     mask: 0b00000000000000000111000001111111
+    attributes: [[name:no_cont], [name:cond]]
     size:   32
     branch:   true
     delay:   [1,1]
-  BLT:
+  - BLT:
-    index: 6
     encoding: 0b00000000000000000100000001100011
     mask: 0b00000000000000000111000001111111
+    attributes: [[name:no_cont], [name:cond]]
     size:   32
     branch:   true
     delay:   [1,1]
-  BGE:
+  - BGE:
-    index: 7
     encoding: 0b00000000000000000101000001100011
     mask: 0b00000000000000000111000001111111
+    attributes: [[name:no_cont], [name:cond]]
     size:   32
     branch:   true
     delay:   [1,1]
-  BLTU:
+  - BLTU:
-    index: 8
     encoding: 0b00000000000000000110000001100011
     mask: 0b00000000000000000111000001111111
+    attributes: [[name:no_cont], [name:cond]]
     size:   32
     branch:   true
     delay:   [1,1]
-  BGEU:
+  - BGEU:
-    index: 9
     encoding: 0b00000000000000000111000001100011
     mask: 0b00000000000000000111000001111111
+    attributes: [[name:no_cont], [name:cond]]
     size:   32
     branch:   true
     delay:   [1,1]
-  LB:
+  - LB:
-    index: 10
     encoding: 0b00000000000000000000000000000011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  LH:
+  - LH:
-    index: 11
     encoding: 0b00000000000000000001000000000011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  LW:
+  - LW:
-    index: 12
     encoding: 0b00000000000000000010000000000011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  LBU:
+  - LBU:
-    index: 13
     encoding: 0b00000000000000000100000000000011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  LHU:
+  - LHU:
-    index: 14
     encoding: 0b00000000000000000101000000000011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  SB:
+  - SB:
-    index: 15
     encoding: 0b00000000000000000000000000100011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  SH:
+  - SH:
-    index: 16
     encoding: 0b00000000000000000001000000100011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  SW:
+  - SW:
-    index: 17
     encoding: 0b00000000000000000010000000100011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  ADDI:
+  - ADDI:
-    index: 18
     encoding: 0b00000000000000000000000000010011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  SLTI:
+  - SLTI:
-    index: 19
     encoding: 0b00000000000000000010000000010011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  SLTIU:
+  - SLTIU:
-    index: 20
     encoding: 0b00000000000000000011000000010011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  XORI:
+  - XORI:
-    index: 21
     encoding: 0b00000000000000000100000000010011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  ORI:
+  - ORI:
-    index: 22
     encoding: 0b00000000000000000110000000010011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  ANDI:
+  - ANDI:
-    index: 23
     encoding: 0b00000000000000000111000000010011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  SLLI:
+  - SLLI:
-    index: 24
     encoding: 0b00000000000000000001000000010011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  SRLI:
+  - SRLI:
-    index: 25
     encoding: 0b00000000000000000101000000010011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  SRAI:
+  - SRAI:
-    index: 26
     encoding: 0b01000000000000000101000000010011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  ADD:
+  - ADD:
-    index: 27
     encoding: 0b00000000000000000000000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  SUB:
+  - SUB:
-    index: 28
     encoding: 0b01000000000000000000000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  SLL:
+  - SLL:
-    index: 29
     encoding: 0b00000000000000000001000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  SLT:
+  - SLT:
-    index: 30
     encoding: 0b00000000000000000010000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  SLTU:
+  - SLTU:
-    index: 31
     encoding: 0b00000000000000000011000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  XOR:
+  - XOR:
-    index: 32
     encoding: 0b00000000000000000100000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  SRL:
+  - SRL:
-    index: 33
     encoding: 0b00000000000000000101000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  SRA:
+  - SRA:
-    index: 34
     encoding: 0b01000000000000000101000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  OR:
+  - OR:
-    index: 35
     encoding: 0b00000000000000000110000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  AND:
+  - AND:
-    index: 36
     encoding: 0b00000000000000000111000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  FENCE:
+  - FENCE:
-    index: 37
     encoding: 0b00000000000000000000000000001111
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  ECALL:
+  - ECALL:
-    index: 38
     encoding: 0b00000000000000000000000001110011
     mask: 0b11111111111111111111111111111111
     attributes: [[name:no_cont]]
     size:   32
     branch:   false
     delay:   1
-  EBREAK:
+  - EBREAK:
-    index: 39
     encoding: 0b00000000000100000000000001110011
     mask: 0b11111111111111111111111111111111
     attributes: [[name:no_cont]]
     size:   32
     branch:   false
     delay:   1
-  MRET:
+  - MRET:
-    index: 40
     encoding: 0b00110000001000000000000001110011
     mask: 0b11111111111111111111111111111111
     attributes: [[name:no_cont]]
     size:   32
     branch:   false
     delay:   1
-  WFI:
+  - WFI:
-    index: 41
     encoding: 0b00010000010100000000000001110011
     mask: 0b11111111111111111111111111111111
     size:   32
     branch:   false
     delay:   1
 Zicsr: 
-  CSRRW:
+  - CSRRW:
-    index: 42
     encoding: 0b00000000000000000001000001110011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  CSRRS:
+  - CSRRS:
-    index: 43
     encoding: 0b00000000000000000010000001110011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  CSRRC:
+  - CSRRC:
-    index: 44
     encoding: 0b00000000000000000011000001110011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  CSRRWI:
+  - CSRRWI:
-    index: 45
     encoding: 0b00000000000000000101000001110011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  CSRRSI:
+  - CSRRSI:
-    index: 46
     encoding: 0b00000000000000000110000001110011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  CSRRCI:
+  - CSRRCI:
-    index: 47
     encoding: 0b00000000000000000111000001110011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
 Zifencei: 
-  FENCE_I:
+  - FENCE_I:
-    index: 48
     encoding: 0b00000000000000000001000000001111
     mask: 0b00000000000000000111000001111111
     attributes: [[name:flush]]
     size:   32
     branch:   false
     delay:   1
-RVM: 
+RV32M: 
-  MUL:
+  - MUL:
-    index: 49
     encoding: 0b00000010000000000000000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  MULH:
+  - MULH:
-    index: 50
     encoding: 0b00000010000000000001000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  MULHSU:
+  - MULHSU:
-    index: 51
     encoding: 0b00000010000000000010000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  MULHU:
+  - MULHU:
-    index: 52
     encoding: 0b00000010000000000011000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  DIV:
+  - DIV:
-    index: 53
     encoding: 0b00000010000000000100000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  DIVU:
+  - DIVU:
-    index: 54
     encoding: 0b00000010000000000101000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  REM:
+  - REM:
-    index: 55
     encoding: 0b00000010000000000110000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
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cmake/flink.cmake

@@ -1,35 +0,0 @@
-# according to https://github.com/horance-liu/flink.cmake/tree/master
-# SPDX-License-Identifier: Apache-2.0
-
-include(CMakeParseArguments)
-
-function(target_do_force_link_libraries target visibility lib)
-  if(MSVC)
-    target_link_libraries(${target} ${visibility} "/WHOLEARCHIVE:${lib}")
-  elseif(APPLE)
-    target_link_libraries(${target} ${visibility} -Wl,-force_load ${lib})
-  else()
-    target_link_libraries(${target} ${visibility} -Wl,--whole-archive ${lib} -Wl,--no-whole-archive)
-  endif()
-endfunction()
-
-function(target_force_link_libraries target)
-  cmake_parse_arguments(FLINK
-    ""
-    ""
-    "PUBLIC;INTERFACE;PRIVATE"
-    ${ARGN}
-  )
-  
-  foreach(lib IN LISTS FLINK_PUBLIC)
-    target_do_force_link_libraries(${target} PUBLIC ${lib})
-  endforeach()
-
-  foreach(lib IN LISTS FLINK_INTERFACE)
-    target_do_force_link_libraries(${target} INTERFACE ${lib})
-  endforeach()
-  
-  foreach(lib IN LISTS FLINK_PRIVATE)
-    target_do_force_link_libraries(${target} PRIVATE ${lib})
-  endforeach()
-endfunction()

contrib/README.md

@@ -19,7 +19,7 @@ setenv CXX $COWAREHOME/SLS/linux/common/bin/g++
 cmake -S . -B build/PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON \
     -DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=${TGFS_INSTALL_ROOT}
 cmake --build build/PA --target install -j16
-cd dbt-rise-tgc/contrib/pa
+cd dbt-rise-tgc/contrib
 # import the TGC core itself
 pct tgc_import_tb.tcl
 ```
@@ -37,7 +37,7 @@ export CXX=$COWAREHOME/SLS/linux/common/bin/g++
 cmake -S . -B build/PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON \
     -DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=${TGFS_INSTALL_ROOT}
 cmake --build build/PA --target install -j16
-cd dbt-rise-tgc/contrib/pa
+cd dbt-rise-tgc/contrib
 # import the TGC core itself
 pct tgc_import_tb.tcl
 ```

contrib/instr/.gitignore

@@ -1 +0,0 @@
-/*.yaml

contrib/instr/TGC5C_slow.yaml

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gen_input/TGC_C.core_desc

@@ -1,8 +1,8 @@
-import "ISA/RVI.core_desc"
+import "ISA/RV32I.core_desc"
 import "ISA/RVM.core_desc"
 import "ISA/RVC.core_desc"
 
-Core TGC5C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
+Core TGC_C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
     architectural_state {
         XLEN=32;
         // definitions for the architecture wrapper

gen_input/templates/CORENAME.cpp.gtl

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2024 MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2020 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -37,7 +37,6 @@ def getRegisterSizes(){
     return regs
 }
 %>
-// clang-format off
 #include "${coreDef.name.toLowerCase()}.h"
 #include "util/ities.h"
 #include <util/logging.h>
@@ -47,10 +46,10 @@ def getRegisterSizes(){
 
 using namespace iss::arch;
 
-constexpr std::array<const char*, ${registers.size()}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
+constexpr std::array<const char*, ${registers.size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
-constexpr std::array<const char*, ${registers.size()}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
+constexpr std::array<const char*, ${registers.size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
-constexpr std::array<const uint32_t, ${getRegisterSizes().size()}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
+constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
-constexpr std::array<const uint32_t, ${getRegisterSizes().size()}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
+constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
 
 ${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}()  = default;
 
@@ -71,7 +70,7 @@ uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
 	return reinterpret_cast<uint8_t*>(&reg);
 }
 
-${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &addr) {
+${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
-    return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
+    return phys_addr_t(pc); // change logical address to physical address
 }
-// clang-format on
+

gen_input/templates/CORENAME.h.gtl

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2024 MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2021 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -55,12 +55,12 @@ def byteSize(int size){
     return 128;
 }
 def getCString(def val){
-    return val.toString()+'ULL'
+    return val.toString()
 }
 %>
 #ifndef _${coreDef.name.toUpperCase()}_H_
 #define _${coreDef.name.toUpperCase()}_H_
-// clang-format off
+
 #include <array>
 #include <iss/arch/traits.h>
 #include <iss/arch_if.h>
@@ -75,11 +75,11 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
 
     constexpr static char const* const core_type = "${coreDef.name}";
     
-    static constexpr std::array<const char*, ${registers.size()}> reg_names{
+    static constexpr std::array<const char*, ${registers.size}> reg_names{
-        {"${registers.collect{it.name.toLowerCase()}.join('", "')}"}};
+        {"${registers.collect{it.name}.join('", "')}"}};
  
-    static constexpr std::array<const char*, ${registers.size()}> reg_aliases{
+    static constexpr std::array<const char*, ${registers.size}> reg_aliases{
-        {"${registers.collect{it.alias.toLowerCase()}.join('", "')}"}};
+        {"${registers.collect{it.alias}.join('", "')}"}};
 
     enum constants {${constants.collect{c -> c.name+"="+getCString(c.value)}.join(', ')}};
 
@@ -99,17 +99,17 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
 
     using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
 
-    static constexpr std::array<const uint32_t, ${getRegisterSizes().size()}> reg_bit_widths{
+    static constexpr std::array<const uint32_t, ${getRegisterSizes().size}> reg_bit_widths{
         {${getRegisterSizes().join(',')}}};
 
-    static constexpr std::array<const uint32_t, ${getRegisterOffsets().size()}> reg_byte_offsets{
+    static constexpr std::array<const uint32_t, ${getRegisterOffsets().size}> reg_byte_offsets{
         {${getRegisterOffsets().join(',')}}};
 
     static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
 
     enum sreg_flag_e { FLAGS };
 
-    enum mem_type_e { ${spaces.collect{it.name}.join(', ')}, IMEM = MEM };
+    enum mem_type_e { ${spaces.collect{it.name}.join(', ')} };
     
     enum class opcode_e {<%instructions.eachWithIndex{instr, index -> %>
         ${instr.instruction.name} = ${index},<%}%>
@@ -137,6 +137,14 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
 
     inline uint64_t stop_code() { return interrupt_sim; }
 
+    inline phys_addr_t v2p(const iss::addr_t& addr){
+        if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
+                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
+            return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
+        } else
+            return virt2phys(addr);
+    }
+
     virtual phys_addr_t virt2phys(const iss::addr_t& addr);
 
     virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
@@ -174,4 +182,3 @@ if(fcsr != null) {%>
 }
 }            
 #endif /* _${coreDef.name.toUpperCase()}_H_ */
-// clang-format on

gen_input/templates/CORENAME_decoder.cpp.gtl

@@ -0,0 +1,86 @@
+#include "${coreDef.name.toLowerCase()}.h"
+#include <vector>
+#include <array>
+#include <cstdlib>
+#include <algorithm>
+
+namespace iss {
+namespace arch {
+namespace {
+// according to
+// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
+#ifdef __GCC__
+constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); }
+#elif __cplusplus < 201402L
+constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); }
+constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; }
+#else
+constexpr size_t bit_count(uint32_t u) {
+    size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111);
+    return ((uCount + (uCount >> 3)) & 030707070707) % 63;
+}
+#endif
+
+using opcode_e = traits<${coreDef.name.toLowerCase()}>::opcode_e;
+
+/****************************************************************************
+ * start opcode definitions
+ ****************************************************************************/
+struct instruction_desriptor {
+    size_t length;
+    uint32_t value;
+    uint32_t mask;
+    opcode_e op;
+};
+
+const std::array<instruction_desriptor, ${instructions.size}> instr_descr = {{
+     /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
+    {${instr.length}, ${instr.encoding}, ${instr.mask}, opcode_e::${instr.instruction.name}},<%}%>
+}};
+
+}
+
+template<>
+struct instruction_decoder<${coreDef.name.toLowerCase()}> {
+    using opcode_e = traits<${coreDef.name.toLowerCase()}>::opcode_e;
+    using code_word_t=traits<${coreDef.name.toLowerCase()}>::code_word_t;
+
+    struct instruction_pattern {
+        uint32_t value;
+        uint32_t mask;
+        opcode_e id;
+    };
+
+    std::array<std::vector<instruction_pattern>, 4> qlut;
+
+    template<typename T>
+    unsigned decode_instruction(T);
+
+    instruction_decoder() {
+        for (auto instr : instr_descr) {
+            auto quadrant = instr.value & 0x3;
+            qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
+        }
+        for(auto& lut: qlut){
+            std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
+                return bit_count(a.mask) < bit_count(b.mask);
+            });
+        }
+    }
+};
+
+template<>
+unsigned instruction_decoder<${coreDef.name.toLowerCase()}>::decode_instruction<traits<${coreDef.name.toLowerCase()}>::code_word_t>(traits<${coreDef.name.toLowerCase()}>::code_word_t instr){
+    auto res = std::find_if(std::begin(qlut[instr&0x3]), std::end(qlut[instr&0x3]), [instr](instruction_pattern const& e){
+        return !((instr&e.mask) ^ e.value );
+    });
+    return static_cast<unsigned>(res!=std::end(qlut[instr&0x3])? res->id : opcode_e::MAX_OPCODE);
+}
+
+
+std::unique_ptr<instruction_decoder<${coreDef.name.toLowerCase()}>> traits<${coreDef.name.toLowerCase()}>::get_decoder(){
+    return std::make_unique<instruction_decoder<${coreDef.name.toLowerCase()}>>();
+}
+
+}
+}

gen_input/templates/CORENAME_instr.yaml.gtl

@@ -8,10 +8,9 @@
         instrGroups[groupName]+=it;
     }
     instrGroups
-}%><%int index = 0; getInstructionGroups().each{name, instrList -> %>
+}%><%getInstructionGroups().each{name, instrList -> %>
-${name}: <% instrList.each { %>
+${name}: <% instrList.findAll{!it.instruction.name.startsWith("__")}.each { %>
-  ${it.instruction.name}:
+  - ${it.instruction.name}:
-    index: ${index++}
     encoding: ${it.encoding}
     mask: ${it.mask}<%if(it.attributes.size) {%>
     attributes: ${it.attributes}<%}%>

gen_input/templates/CORENAME_sysc.cpp.gtl

@@ -1,131 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2024 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-// clang-format off
-#include <sysc/iss_factory.h>
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_mu_p.h>
-#include <sysc/sc_core_adapter.h>
-#include <sysc/core_complex.h>
-#include <array>
-<%
-def array_count = coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e"? 3 : 2;
-%>
-namespace iss {
-namespace interp {
-using namespace sysc;
-volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        }),
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        })<%}%>
-};
-}
-#if defined(WITH_LLVM)
-namespace llvm {
-using namespace sysc;
-volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        }),
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        })<%}%>
-};
-}
-#endif
-#if defined(WITH_TCC)
-namespace tcc {
-using namespace sysc;
-volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        }),
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        })<%}%>
-};
-}
-#endif
-#if defined(WITH_ASMJIT)
-namespace asmjit {
-using namespace sysc;
-volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        }),
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        })<%}%>
-};
-}
-#endif
-}
-// clang-format on

gen_input/templates/asmjit/CORENAME.cpp.gtl

@@ -1,369 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017-2024 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-// clang-format off
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <iss/debugger/gdb_session.h>
-#include <iss/debugger/server.h>
-#include <iss/iss.h>
-#include <iss/asmjit/vm_base.h>
-#include <asmjit/asmjit.h>
-#include <util/logging.h>
-#include <iss/instruction_decoder.h>
-<%def fcsr = registers.find {it.name=='FCSR'}
-if(fcsr != null) {%>
-#include <vm/fp_functions.h><%}%>
-#ifndef FMT_HEADER_ONLY
-#define FMT_HEADER_ONLY
-#endif
-#include <fmt/format.h>
-
-#include <array>
-#include <iss/debugger/riscv_target_adapter.h>
-
-namespace iss {
-namespace asmjit {
-
-
-namespace ${coreDef.name.toLowerCase()} {
-using namespace ::asmjit;
-using namespace iss::arch;
-using namespace iss::debugger;
-
-template <typename ARCH> class vm_impl : public iss::asmjit::vm_base<ARCH> {
-public:
-    using traits = arch::traits<ARCH>;
-    using super = typename iss::asmjit::vm_base<ARCH>;
-    using virt_addr_t = typename super::virt_addr_t;
-    using phys_addr_t = typename super::phys_addr_t;
-    using code_word_t = typename super::code_word_t;
-    using mem_type_e = typename super::mem_type_e;
-    using addr_t = typename super::addr_t;
-
-    vm_impl();
-
-    vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
-
-    void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
-
-    target_adapter_if *accquire_target_adapter(server_if *srv) override {
-        debugger_if::dbg_enabled = true;
-        if (vm_base<ARCH>::tgt_adapter == nullptr)
-            vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
-        return vm_base<ARCH>::tgt_adapter;
-    }
-
-protected:
-    using super::get_ptr_for;
-    using super::get_reg_for;
-    using super::get_reg_for_Gp;
-    using super::load_reg_from_mem;
-    using super::load_reg_from_mem_Gp;
-    using super::write_reg_to_mem;
-    using super::gen_read_mem;
-    using super::gen_write_mem;
-    using super::gen_leave;
-    using super::gen_sync;
-   
-    using this_class = vm_impl<ARCH>;
-    using compile_func = continuation_e (this_class::*)(virt_addr_t&, code_word_t, jit_holder&);
-
-    continuation_e gen_single_inst_behavior(virt_addr_t&, unsigned int &, jit_holder&) override;
-    enum globals_e {TVAL = 0, GLOBALS_SIZE};
-    void gen_block_prologue(jit_holder& jh) override;
-    void gen_block_epilogue(jit_holder& jh) override;
-    inline const char *name(size_t index){return traits::reg_aliases.at(index);}
-<%if(fcsr != null) {%>
-    inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}   
-<%}%>
-    void gen_instr_prologue(jit_holder& jh);
-    void gen_instr_epilogue(jit_holder& jh);
-    inline void gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause);
-    template <typename T, typename = typename std::enable_if<std::is_integral<T>::value>::type> void gen_set_tval(jit_holder& jh, T new_tval) ;
-    void gen_set_tval(jit_holder& jh, x86_reg_t _new_tval) ;
-
-    template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
-    inline S sext(U from) {
-        auto mask = (1ULL<<W) - 1;
-        auto sign_mask = 1ULL<<(W-1);
-        return (from & mask) | ((from & sign_mask) ? ~mask : 0);
-    }
-<%functions.each{ it.eachLine { %>
-    ${it}<%}%>
-<%}%>
-private:
-    /****************************************************************************
-     * start opcode definitions
-     ****************************************************************************/
-    struct instruction_descriptor {
-        uint32_t length;
-        uint32_t value;
-        uint32_t mask;
-        compile_func op;
-    };
-
-    const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
-         /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
-        /* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
-        {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
-    }};
-
-    //needs to be declared after instr_descr
-    decoder instr_decoder;
-
-    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
-    /* instruction ${idx}: ${instr.name} */
-    continuation_e __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, jit_holder& jh){
-        uint64_t PC = pc.val;
-        <%instr.fields.eachLine{%>${it}
-        <%}%>if(this->disass_enabled){
-            /* generate disass */
-            <%instr.disass.eachLine{%>
-            ${it}<%}%>
-            InvokeNode* call_print_disass;
-            char* mnemonic_ptr = strdup(mnemonic.c_str());
-            jh.disass_collection.push_back(mnemonic_ptr);
-            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build<void, void *, uint64_t, char *>());
-            call_print_disass->setArg(0, jh.arch_if_ptr);
-            call_print_disass->setArg(1, pc.val);
-            call_print_disass->setArg(2, mnemonic_ptr);
-
-        }
-        x86::Compiler& cc = jh.cc;
-        cc.comment(fmt::format("${instr.name}_{:#x}:",pc.val).c_str());
-        gen_sync(jh, PRE_SYNC, ${idx});
-        mov(cc, jh.pc, pc.val);
-        gen_set_tval(jh, instr);
-        pc = pc+${instr.length/8};
-        mov(cc, jh.next_pc, pc.val);
-
-        gen_instr_prologue(jh);
-        cc.comment("//behavior:");
-        /*generate behavior*/
-        <%instr.behavior.eachLine{%>${it}
-        <%}%>
-        gen_sync(jh, POST_SYNC, ${idx});
-        gen_instr_epilogue(jh);
-    	return returnValue;        
-    }
-    <%}%>
-    /****************************************************************************
-     * end opcode definitions
-     ****************************************************************************/
-    continuation_e illegal_instruction(virt_addr_t &pc, code_word_t instr, jit_holder& jh ) {
-        x86::Compiler& cc = jh.cc;
-        if(this->disass_enabled){          
-            auto mnemonic = std::string("illegal_instruction");
-            InvokeNode* call_print_disass;
-            char* mnemonic_ptr = strdup(mnemonic.c_str());
-            jh.disass_collection.push_back(mnemonic_ptr);
-            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build<void, void *, uint64_t, char *>());
-            call_print_disass->setArg(0, jh.arch_if_ptr);
-            call_print_disass->setArg(1, pc.val);
-            call_print_disass->setArg(2, mnemonic_ptr);
-        }
-        cc.comment(fmt::format("illegal_instruction{:#x}:",pc.val).c_str());
-        gen_sync(jh, PRE_SYNC, instr_descr.size());
-        mov(cc, jh.pc, pc.val);
-        gen_set_tval(jh, instr);
-        pc = pc + ((instr & 3) == 3 ? 4 : 2);
-        mov(cc, jh.next_pc, pc.val);
-        gen_instr_prologue(jh);
-        cc.comment("//behavior:");
-        gen_raise(jh, 0, 2);
-        gen_sync(jh, POST_SYNC, instr_descr.size());
-        gen_instr_epilogue(jh);
-        return ILLEGAL_INSTR;
-    }
-};
-
-template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
-
-template <typename ARCH>
-vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
-: vm_base<ARCH>(core, core_id, cluster_id)
-, instr_decoder([this]() {
-        std::vector<generic_instruction_descriptor> g_instr_descr;
-        g_instr_descr.reserve(instr_descr.size());
-        for (uint32_t i = 0; i < instr_descr.size(); ++i) {
-            generic_instruction_descriptor new_instr_descr {instr_descr[i].value, instr_descr[i].mask, i};
-            g_instr_descr.push_back(new_instr_descr);
-        }
-        return std::move(g_instr_descr);
-    }()) {}
-
-template <typename ARCH>
-continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, jit_holder& jh) {
-    enum {TRAP_ID=1<<16};
-    code_word_t instr = 0;
-    phys_addr_t paddr(pc);
-    auto *const data = (uint8_t *)&instr;
-    if(this->core.has_mmu())
-        paddr = this->core.virt2phys(pc);
-    auto res = this->core.read(paddr, 4, data);
-    if (res != iss::Ok)
-        return ILLEGAL_FETCH;
-    if (instr == 0x0000006f || (instr&0xffff)==0xa001)
-        return JUMP_TO_SELF;
-    ++inst_cnt;
-    uint32_t inst_index = instr_decoder.decode_instr(instr);
-    compile_func f = nullptr;
-    if(inst_index < instr_descr.size())
-        f = instr_descr[inst_index].op;
-    if (f == nullptr) 
-        f = &this_class::illegal_instruction;
-    return (this->*f)(pc, instr, jh);
-}
-template <typename ARCH>
-void vm_impl<ARCH>::gen_instr_prologue(jit_holder& jh) {
-    auto& cc = jh.cc;
-
-    cc.comment("//gen_instr_prologue");
-
-    x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE);
-    mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
-    mov(cc, get_ptr_for(jh, traits::PENDING_TRAP), current_trap_state);
-
-}
-template <typename ARCH>
-void vm_impl<ARCH>::gen_instr_epilogue(jit_holder& jh) {
-    auto& cc = jh.cc;
-
-    cc.comment("//gen_instr_epilogue");
-    x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE);
-    mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
-    cmp(cc, current_trap_state, 0);
-    cc.jne(jh.trap_entry);
-    cc.inc(get_ptr_for(jh, traits::ICOUNT));
-}
-template <typename ARCH>
-void vm_impl<ARCH>::gen_block_prologue(jit_holder& jh){
-    jh.pc = load_reg_from_mem_Gp(jh, traits::PC);
-    jh.next_pc = load_reg_from_mem_Gp(jh, traits::NEXT_PC);
-    jh.globals.resize(GLOBALS_SIZE);
-    jh.globals[TVAL] = get_reg_Gp(jh.cc, 64, false);
-}
-template <typename ARCH>
-void vm_impl<ARCH>::gen_block_epilogue(jit_holder& jh){
-    x86::Compiler& cc = jh.cc;
-    cc.comment("//gen_block_epilogue");
-    cc.ret(jh.next_pc);
-
-    cc.bind(jh.trap_entry);
-    this->write_back(jh);
-
-    x86::Gp current_trap_state = get_reg_for_Gp(cc, traits::TRAP_STATE);
-    mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
-
-    x86::Gp current_pc = get_reg_for_Gp(cc, traits::PC);
-    mov(cc, current_pc, get_ptr_for(jh, traits::PC));
-
-    cc.comment("//enter trap call;");
-    InvokeNode* call_enter_trap;
-    cc.invoke(&call_enter_trap, &enter_trap, FuncSignature::build<uint64_t, void*, uint64_t, uint64_t, uint64_t>());
-    call_enter_trap->setArg(0, jh.arch_if_ptr);
-    call_enter_trap->setArg(1, current_trap_state);
-    call_enter_trap->setArg(2, current_pc);
-    call_enter_trap->setArg(3, jh.globals[TVAL]);
-
-    x86_reg_t current_next_pc = get_reg_for(cc, traits::NEXT_PC);
-    mov(cc, current_next_pc, get_ptr_for(jh, traits::NEXT_PC));
-    mov(cc, jh.next_pc, current_next_pc);
-
-    mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(UNKNOWN_JUMP));
-    cc.ret(jh.next_pc);
-}
-template <typename ARCH>
-inline void vm_impl<ARCH>::gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause) {
-    auto& cc = jh.cc;
-    cc.comment("//gen_raise");
-    auto tmp1 = get_reg_for(cc, traits::TRAP_STATE);
-    mov(cc, tmp1, 0x80ULL << 24 | (cause << 16) | trap_id);
-    mov(cc, get_ptr_for(jh, traits::TRAP_STATE), tmp1);
-}
-template <typename ARCH>
-template <typename T, typename>
-void vm_impl<ARCH>::gen_set_tval(jit_holder& jh, T new_tval) {
-        mov(jh.cc, jh.globals[TVAL], new_tval);
-    }
-template <typename ARCH>
-void vm_impl<ARCH>::gen_set_tval(jit_holder& jh, x86_reg_t _new_tval) {
-    if(nonstd::holds_alternative<x86::Gp>(_new_tval)) {
-        x86::Gp new_tval = nonstd::get<x86::Gp>(_new_tval);
-        if(new_tval.size() < 8)
-            new_tval = gen_ext_Gp(jh.cc, new_tval, 64, false);
-        mov(jh.cc, jh.globals[TVAL], new_tval);
-    } else {
-        throw std::runtime_error("Variant not supported in gen_set_tval");
-    }
-}
-
-} // namespace tgc5c
-
-template <>
-std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
-    auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
-    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
-    return std::unique_ptr<vm_if>(ret);
-}
-} // namespace asmjit
-} // namespace iss
-
-#include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_mu_p.h>
-#include <iss/factory.h>
-namespace iss {
-namespace {
-volatile std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|asmjit", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
-		    auto vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
-		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            if(init_data){
-                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
-                cpu->set_semihosting_callback(*cb);
-            }
-            return {cpu_ptr{cpu}, vm_ptr{vm}};
-        }),
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|asmjit", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
-		    auto vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
-		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            if(init_data){
-                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
-                cpu->set_semihosting_callback(*cb);
-            }
-            return {cpu_ptr{cpu}, vm_ptr{vm}};
-        })
-};
-}
-}
-// clang-format on

gen_input/templates/interp/CORENAME.cpp.gtl

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017-2024 MINRES Technologies GmbH
+ * Copyright (C) 2021 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -34,22 +34,15 @@ def nativeTypeSize(int size){
     if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
 }
 %>
-// clang-format off
-#include <cstdint>
 #include <iss/arch/${coreDef.name.toLowerCase()}.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
 #include <iss/iss.h>
 #include <iss/interp/vm_base.h>
-#include <vm/fp_functions.h>
 #include <util/logging.h>
+#include <sstream>
 #include <boost/coroutine2/all.hpp>
 #include <functional>
-#include <exception>
-#include <vector>
-#include <sstream>
-#include <iss/instruction_decoder.h>
-
 
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
@@ -66,10 +59,6 @@ using namespace iss::arch;
 using namespace iss::debugger;
 using namespace std::placeholders;
 
-struct memory_access_exception : public std::exception{
-    memory_access_exception(){}
-};
-
 template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
 public:
     using traits = arch::traits<ARCH>;
@@ -100,20 +89,37 @@ protected:
     using compile_ret_t = virt_addr_t;
     using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
 
-    inline const char *name(size_t index){return traits::reg_aliases.at(index);}
+    inline const char *name(size_t index){return index<traits::reg_aliases.size()?traits::reg_aliases[index]:"illegal";}
-<%
-def fcsr = registers.find {it.name=='FCSR'}
-if(fcsr != null) {%>
-    inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}     
-<%}%>
 
+    typename arch::traits<ARCH>::opcode_e decode_inst_id(code_word_t instr);
     virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;
 
     // some compile time constants
+    // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
+    enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
+    enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
+    enum {
+        LUT_SIZE = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK32)),
+        LUT_SIZE_C = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK16))
+    };
+
+    std::array<compile_func, LUT_SIZE> lut;
+
+    std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
+    std::array<compile_func, LUT_SIZE> lut_11;
+
+    struct instruction_pattern {
+        uint32_t value;
+        uint32_t mask;
+        typename arch::traits<ARCH>::opcode_e id;
+    };
+
+    std::array<std::vector<instruction_pattern>, 4> qlut;
 
     inline void raise(uint16_t trap_id, uint16_t cause){
         auto trap_val =  0x80ULL << 24 | (cause << 16) | trap_id;
         this->core.reg.trap_state = trap_val;
+        this->template get_reg<uint${addrDataWidth}_t>(traits::NEXT_PC) = std::numeric_limits<uint${addrDataWidth}_t>::max();
     }
 
     inline void leave(unsigned lvl){
@@ -124,13 +130,6 @@ if(fcsr != null) {%>
         this->core.wait_until(type);
     }
 
-    inline void set_tval(uint64_t new_tval){
-        tval = new_tval;
-    }
-
-    uint64_t fetch_count{0};
-    uint64_t tval{0};
-
     using yield_t = boost::coroutines2::coroutine<void>::push_type;
     using coro_t = boost::coroutines2::coroutine<void>::pull_type;
     std::vector<coro_t> spawn_blocks;
@@ -159,38 +158,28 @@ private:
     /****************************************************************************
      * start opcode definitions
      ****************************************************************************/
-    struct instruction_descriptor {
+    struct InstructionDesriptor {
-        uint32_t length;
+        size_t length;
         uint32_t value;
         uint32_t mask;
         typename arch::traits<ARCH>::opcode_e op;
     };
 
-    const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
+    const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
          /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
         {${instr.length}, ${instr.encoding}, ${instr.mask}, arch::traits<ARCH>::opcode_e::${instr.instruction.name}},<%}%>
     }};
 
-    //needs to be declared after instr_descr
+    //static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK;
-    decoder instr_decoder;
-
     iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
-        if(this->core.has_mmu()) {
+        auto phys_pc = this->core.v2p(pc);
-            auto phys_pc = this->core.virt2phys(pc);
         //if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
         //    if (this->core.read(phys_pc, 2, data) != iss::Ok) return iss::Err;
         //    if ((data[0] & 0x3) == 0x3) // this is a 32bit instruction
-//                    if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok)
+        //        if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok) return iss::Err;
-//                        return iss::Err;
         //} else {
-                if (this->core.read(phys_pc, 4, data) != iss::Ok)
+            if (this->core.read(phys_pc, 4, data) != iss::Ok)  return iss::Err;
-                    return iss::Err;
         //}
-        } else {
-            if (this->core.read(phys_addr_t(pc.access, pc.space, pc.val), 4, data) != iss::Ok)
-                return iss::Err;
-
-        }
         return iss::Ok;
     }
 };
@@ -218,23 +207,21 @@ constexpr size_t bit_count(uint32_t u) {
 
 template <typename ARCH>
 vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
-: vm_base<ARCH>(core, core_id, cluster_id)
+: vm_base<ARCH>(core, core_id, cluster_id) {
-, instr_decoder([this]() {
+    unsigned id=0;
-        std::vector<generic_instruction_descriptor> g_instr_descr;
+    for (auto instr : instr_descr) {
-        g_instr_descr.reserve(instr_descr.size());
+        auto quadrant = instr.value & 0x3;
-        for (uint32_t i = 0; i < instr_descr.size(); ++i) {
+        qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
-            generic_instruction_descriptor new_instr_descr {instr_descr[i].value, instr_descr[i].mask, i};
+    }
-            g_instr_descr.push_back(new_instr_descr);
+    for(auto& lut: qlut){
+        std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
+            return bit_count(a.mask) > bit_count(b.mask);
+        });
     }
-        return std::move(g_instr_descr);
-    }()) {}
-
-inline bool is_icount_limit_enabled(finish_cond_e cond){
-    return (cond & finish_cond_e::ICOUNT_LIMIT) == finish_cond_e::ICOUNT_LIMIT;
 }
 
-inline bool is_fcount_limit_enabled(finish_cond_e cond){
+inline bool is_count_limit_enabled(finish_cond_e cond){
-    return (cond & finish_cond_e::FCOUNT_LIMIT) == finish_cond_e::FCOUNT_LIMIT;
+    return (cond & finish_cond_e::COUNT_LIMIT) == finish_cond_e::COUNT_LIMIT;
 }
 
 inline bool is_jump_to_self_enabled(finish_cond_e cond){
@@ -242,7 +229,15 @@ inline bool is_jump_to_self_enabled(finish_cond_e cond){
 }
 
 template <typename ARCH>
-typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t count_limit){
+typename arch::traits<ARCH>::opcode_e vm_impl<ARCH>::decode_inst_id(code_word_t instr){
+    for(auto& e: qlut[instr&0x3]){
+        if(!((instr&e.mask) ^ e.value )) return e.id;
+    }
+    return arch::traits<ARCH>::opcode_e::MAX_OPCODE;
+}
+
+template <typename ARCH>
+typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
     auto pc=start;
     auto* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
     auto* NEXT_PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
@@ -255,35 +250,23 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
     auto *const data = reinterpret_cast<uint8_t*>(&instr);
 
     while(!this->core.should_stop() &&
-            !(is_icount_limit_enabled(cond) && icount >= count_limit) &&
+            !(is_count_limit_enabled(cond) && icount >= icount_limit)){
-            !(is_fcount_limit_enabled(cond) && fetch_count >= count_limit)){
-        if(this->debugging_enabled())
-            this->tgt_adapter->check_continue(*PC);
-        pc.val=*PC;
         if(fetch_ins(pc, data)!=iss::Ok){
-            if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());
+            this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
-            process_spawn_blocks();
+            pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);
-            if(this->sync_exec && POST_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());
-            pc.val = super::core.enter_trap(arch::traits<ARCH>::RV_CAUSE_FETCH_ACCESS<<16, pc.val, 0);
         } else {
             if (is_jump_to_self_enabled(cond) &&
                     (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
-            uint32_t inst_index = instr_decoder.decode_instr(instr);
+            auto inst_id = decode_inst_id(instr);
-            opcode_e inst_id = arch::traits<ARCH>::opcode_e::MAX_OPCODE;;
-            if(inst_index <instr_descr.size())
-                inst_id = instr_descr[inst_index].op;
-
             // pre execution stuff
              this->core.reg.last_branch = 0;
             if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
-            try{
             switch(inst_id){<%instructions.eachWithIndex{instr, idx -> %>
             case arch::traits<ARCH>::opcode_e::${instr.name}: {
                 <%instr.fields.eachLine{%>${it}
                 <%}%>if(this->disass_enabled){
                     /* generate console output when executing the command */<%instr.disass.eachLine{%>
                     ${it}<%}%>
-                        this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers<%instr.usedVariables.each{ k,v->
                 if(v.isArray) {%>
@@ -293,14 +276,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 *NEXT_PC = *PC + ${instr.length/8};
                 // execute instruction<%instr.behavior.eachLine{%>
                 ${it}<%}%>
-                    break;
+                TRAP_${instr.name}:break;
             }// @suppress("No break at end of case")<%}%>
             default: {
                 *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
                 raise(0,  2);
             }
             }
-            }catch(memory_access_exception& e){}
             // post execution stuff
             process_spawn_blocks();
             if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
@@ -308,23 +290,21 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
             //    this->core.reg.trap_state =  this->core.reg.pending_trap;
             // trap check
             if(trap_state!=0){
-                //In case of Instruction address misaligned (cause = 0 and trapid = 0) need the targeted addr (in tval)
+                super::core.enter_trap(trap_state, pc.val, instr);
-                auto mcause = (trap_state>>16) & 0xff; 
-                super::core.enter_trap(trap_state, pc.val, mcause ? instr:tval);
             } else {
                 icount++;
                 instret++;
             }
-            *PC = *NEXT_PC;
+            cycle++;
+            pc.val=*NEXT_PC;
+            this->core.reg.PC = this->core.reg.NEXT_PC;
             this->core.reg.trap_state =  this->core.reg.pending_trap;
         }
-        fetch_count++;
-        cycle++;
     }
     return pc;
 }
 
-} // namespace ${coreDef.name.toLowerCase()}
+}
 
 template <>
 std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
@@ -335,33 +315,29 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
 } // namespace interp
 } // namespace iss
 
+#include <iss/factory.h>
 #include <iss/arch/riscv_hart_m_p.h>
 #include <iss/arch/riscv_hart_mu_p.h>
-#include <iss/factory.h>
 namespace iss {
 namespace {
-volatile std::array<bool, 2> dummy = {
+std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
             auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
 		    auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
 		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            if(init_data){
-                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
-                cpu->set_semihosting_callback(*cb);
-            }
             return {cpu_ptr{cpu}, vm_ptr{vm}};
         }),
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
             auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
 		    auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
 		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            if(init_data){
-                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
-                cpu->set_semihosting_callback(*cb);
-            }
             return {cpu_ptr{cpu}, vm_ptr{vm}};
         })
 };
 }
 }
-// clang-format on
+extern "C" {
+	bool* get_${coreDef.name.toLowerCase()}_interp_creators() {
+		return iss::dummy.data();
+	}
+}

gen_input/templates/llvm/CORENAME.cpp.gtl

@@ -1,384 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017-2024 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-// clang-format off
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <iss/debugger/gdb_session.h>
-#include <iss/debugger/server.h>
-#include <iss/iss.h>
-#include <iss/llvm/vm_base.h>
-#include <util/logging.h>
-#include <iss/instruction_decoder.h>
-<%def fcsr = registers.find {it.name=='FCSR'}
-if(fcsr != null) {%>
-#include <vm/fp_functions.h><%}%>
-#ifndef FMT_HEADER_ONLY
-#define FMT_HEADER_ONLY
-#endif
-#include <fmt/format.h>
-
-#include <array>
-#include <iss/debugger/riscv_target_adapter.h>
-
-namespace iss {
-namespace llvm {
-namespace fp_impl {
-void add_fp_functions_2_module(::llvm::Module *, unsigned, unsigned);
-}
-
-namespace ${coreDef.name.toLowerCase()} {
-using namespace ::llvm;
-using namespace iss::arch;
-using namespace iss::debugger;
-
-template <typename ARCH> class vm_impl : public iss::llvm::vm_base<ARCH> {
-public:
-    using traits = arch::traits<ARCH>;
-    using super = typename iss::llvm::vm_base<ARCH>;
-    using virt_addr_t = typename super::virt_addr_t;
-    using phys_addr_t = typename super::phys_addr_t;
-    using code_word_t = typename super::code_word_t;
-    using addr_t = typename super::addr_t;
-
-    vm_impl();
-
-    vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
-
-    void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
-
-    target_adapter_if *accquire_target_adapter(server_if *srv) override {
-        debugger_if::dbg_enabled = true;
-        if (vm_base<ARCH>::tgt_adapter == nullptr)
-            vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
-        return vm_base<ARCH>::tgt_adapter;
-    }
-
-protected:
-    using vm_base<ARCH>::get_reg_ptr;
-
-    inline const char *name(size_t index){return traits::reg_aliases.at(index);}
-<%if(fcsr != null) {%>
-    inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}   
-<%}%>
-    template <typename T> inline ConstantInt *size(T type) {
-        return ConstantInt::get(getContext(), APInt(32, type->getType()->getScalarSizeInBits()));
-    }
-
-    void setup_module(Module* m) override {
-        super::setup_module(m);
-        iss::llvm::fp_impl::add_fp_functions_2_module(m, traits::FP_REGS_SIZE, traits::XLEN);
-    }
-
-    inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) {
-        return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
-    }
-
-    std::tuple<continuation_e, BasicBlock *> gen_single_inst_behavior(virt_addr_t &, unsigned int &, BasicBlock *) override;
-
-    void gen_leave_behavior(BasicBlock *leave_blk) override;
-    void gen_raise_trap(uint16_t trap_id, uint16_t cause);
-    void gen_leave_trap(unsigned lvl);
-    void gen_wait(unsigned type);
-    void set_tval(uint64_t new_tval);
-    void set_tval(Value* new_tval);
-    void gen_trap_behavior(BasicBlock *) override;
-    void gen_instr_prologue();
-    void gen_instr_epilogue(BasicBlock *bb);
-
-    inline Value *gen_reg_load(unsigned i, unsigned level = 0) {
-        return this->builder.CreateLoad(this->get_typeptr(i), get_reg_ptr(i), false);
-    }
-
-    inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
-        Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits::XLEN, pc.val),
-                                                           this->get_type(traits::XLEN));
-        this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
-    }
-
-    // some compile time constants
-
-    using this_class = vm_impl<ARCH>;
-    using compile_func = std::tuple<continuation_e, BasicBlock *> (this_class::*)(virt_addr_t &pc,
-                                                                                  code_word_t instr,
-                                                                                  BasicBlock *bb);
-    template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
-    inline S sext(U from) {
-        auto mask = (1ULL<<W) - 1;
-        auto sign_mask = 1ULL<<(W-1);
-        return (from & mask) | ((from & sign_mask) ? ~mask : 0);
-    }
-<%functions.each{ it.eachLine { %>
-    ${it}<%}%>
-<%}%>
-private:
-    /****************************************************************************
-     * start opcode definitions
-     ****************************************************************************/
-    struct instruction_descriptor {
-        uint32_t length;
-        uint32_t value;
-        uint32_t mask;
-        compile_func op;
-    };
-
-    const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
-         /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
-        /* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
-        {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
-    }};
-
-    //needs to be declared after instr_descr
-    decoder instr_decoder;
-
-    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
-    /* instruction ${idx}: ${instr.name} */
-    std::tuple<continuation_e, BasicBlock*> __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        uint64_t PC = pc.val;
-        <%instr.fields.eachLine{%>${it}
-        <%}%>if(this->disass_enabled){
-            /* generate console output when executing the command */<%instr.disass.eachLine{%>
-            ${it}<%}%>
-            std::vector<Value*> args {
-                this->core_ptr,
-                this->gen_const(64, pc.val),
-                this->builder.CreateGlobalStringPtr(mnemonic),
-            };
-            this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
-        }
-        bb->setName(fmt::format("${instr.name}_0x{:X}",pc.val));
-        this->gen_sync(PRE_SYNC,${idx});
-        
-        this->gen_set_pc(pc, traits::PC);
-        this->set_tval(instr);
-        pc=pc+ ${instr.length/8};
-        this->gen_set_pc(pc, traits::NEXT_PC);
-        
-        this->gen_instr_prologue();
-        /*generate behavior*/
-        <%instr.behavior.eachLine{%>${it}
-        <%}%>
-        this->gen_sync(POST_SYNC, ${idx});
-        this->gen_instr_epilogue(bb);
-        this->builder.CreateBr(bb);
-    	return returnValue;        
-    }
-    <%}%>
-    /****************************************************************************
-     * end opcode definitions
-     ****************************************************************************/
-    std::tuple<continuation_e, BasicBlock *> illegal_instruction(virt_addr_t &pc, code_word_t instr, BasicBlock *bb) {
-        if(this->disass_enabled){
-            auto mnemonic = std::string("illegal_instruction");
-            std::vector<Value*> args {
-                this->core_ptr,
-                this->gen_const(64, pc.val),
-                this->builder.CreateGlobalStringPtr(mnemonic),
-            };
-            this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
-        }
-        this->gen_sync(iss::PRE_SYNC, instr_descr.size());
-        this->builder.CreateStore(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), true),
-                                   get_reg_ptr(traits::PC), true);
-        this->builder.CreateStore(
-            this->builder.CreateAdd(this->builder.CreateLoad(this->get_typeptr(traits::ICOUNT), get_reg_ptr(traits::ICOUNT), true),
-                                     this->gen_const(64U, 1)),
-            get_reg_ptr(traits::ICOUNT), true);
-        pc = pc + ((instr & 3) == 3 ? 4 : 2);
-        this->set_tval(instr);
-        this->gen_raise_trap(0, 2);     // illegal instruction trap
-		this->gen_sync(iss::POST_SYNC, instr_descr.size());
-        bb = this->leave_blk;
-        this->gen_instr_epilogue(bb);
-        this->builder.CreateBr(bb);
-        return std::make_tuple(ILLEGAL_INSTR, nullptr);
-    }    
-};
-
-template <typename CODE_WORD> void debug_fn(CODE_WORD instr) {
-    volatile CODE_WORD x = instr;
-    instr = 2 * x;
-}
-
-template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
-
-template <typename ARCH>
-vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
-: vm_base<ARCH>(core, core_id, cluster_id)
-, instr_decoder([this]() {
-        std::vector<generic_instruction_descriptor> g_instr_descr;
-        g_instr_descr.reserve(instr_descr.size());
-        for (uint32_t i = 0; i < instr_descr.size(); ++i) {
-            generic_instruction_descriptor new_instr_descr {instr_descr[i].value, instr_descr[i].mask, i};
-            g_instr_descr.push_back(new_instr_descr);
-        }
-        return std::move(g_instr_descr);
-    }()) {}
-
-template <typename ARCH>
-std::tuple<continuation_e, BasicBlock *>
-vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, BasicBlock *this_block) {
-    // we fetch at max 4 byte, alignment is 2
-    enum {TRAP_ID=1<<16};
-    code_word_t instr = 0;
-    // const typename traits::addr_t upper_bits = ~traits::PGMASK;
-    phys_addr_t paddr(pc);
-    auto *const data = (uint8_t *)&instr;
-    if(this->core.has_mmu())
-        paddr = this->core.virt2phys(pc);
-    auto res = this->core.read(paddr, 4, data);
-    if (res != iss::Ok) 
-        return std::make_tuple(ILLEGAL_FETCH, nullptr);
-    if (instr == 0x0000006f || (instr&0xffff)==0xa001)
-        return std::make_tuple(JUMP_TO_SELF, nullptr);
-    ++inst_cnt;
-    uint32_t inst_index = instr_decoder.decode_instr(instr);
-    compile_func f = nullptr;
-    if(inst_index < instr_descr.size())
-        f = instr_descr[inst_index].op;
-    if (f == nullptr) {
-        f = &this_class::illegal_instruction;
-    }
-    return (this->*f)(pc, instr, this_block);
-}
-
-template <typename ARCH>
-void vm_impl<ARCH>::gen_leave_behavior(BasicBlock *leave_blk) {
-    this->builder.SetInsertPoint(leave_blk);
-    this->builder.CreateRet(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC),get_reg_ptr(traits::NEXT_PC), false));
-}
-
-template <typename ARCH>
-void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
-    auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
-    this->builder.CreateStore(TRAP_val, get_reg_ptr(traits::TRAP_STATE), true);
-}
-
-template <typename ARCH>
-void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
-    std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)) };
-    this->builder.CreateCall(this->mod->getFunction("leave_trap"), args);
-    this->builder.CreateStore(this->gen_const(32U, static_cast<int>(UNKNOWN_JUMP)), get_reg_ptr(traits::LAST_BRANCH), false);
-}
-
-template <typename ARCH>
-void vm_impl<ARCH>::gen_wait(unsigned type) {
-    std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, type)) };
-    this->builder.CreateCall(this->mod->getFunction("wait"), args);
-}
-
-template <typename ARCH>
-inline void vm_impl<ARCH>::set_tval(uint64_t tval) {
-    auto tmp_tval = this->gen_const(64, tval);
-    this->set_tval(tmp_tval);
-}
-template <typename ARCH>
-inline void vm_impl<ARCH>::set_tval(Value* new_tval) {
-    this->builder.CreateStore(this->gen_ext(new_tval, 64, false), this->tval);
-}
-template <typename ARCH> 
-void vm_impl<ARCH>::gen_trap_behavior(BasicBlock *trap_blk) {
-    this->builder.SetInsertPoint(trap_blk);
-    auto *trap_state_val = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true);
-    auto *cur_pc_val = this->builder.CreateLoad(this->get_typeptr(traits::PC), get_reg_ptr(traits::PC), true);
-    std::vector<Value *> args{this->core_ptr,
-                                this->adj_to64(trap_state_val),
-                                this->adj_to64(cur_pc_val),
-                              this->adj_to64(this->builder.CreateLoad(this->get_type(64),this->tval))};
-    this->builder.CreateCall(this->mod->getFunction("enter_trap"), args);
-    this->builder.CreateStore(this->gen_const(32U, static_cast<int>(UNKNOWN_JUMP)), get_reg_ptr(traits::LAST_BRANCH), false);
-
-    auto *trap_addr_val = this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), false);
-    this->builder.CreateRet(trap_addr_val);
-}
-template <typename ARCH>
-void vm_impl<ARCH>::gen_instr_prologue() {
-    auto* trap_val =
-        this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::PENDING_TRAP), get_reg_ptr(arch::traits<ARCH>::PENDING_TRAP));
-    this->builder.CreateStore(trap_val, get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), false);
-}
-            
-
-template <typename ARCH>
-void vm_impl<ARCH>::gen_instr_epilogue(BasicBlock *bb) {
-    auto* target_bb = BasicBlock::Create(this->mod->getContext(), "", this->func, bb);
-    auto *v = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true);
-    this->gen_cond_branch(this->builder.CreateICmp(
-                              ICmpInst::ICMP_EQ, v,
-                              ConstantInt::get(getContext(), APInt(v->getType()->getIntegerBitWidth(), 0))),
-                          target_bb, this->trap_blk, 1);
-    this->builder.SetInsertPoint(target_bb);
-    // update icount
-    auto* icount_val = this->builder.CreateAdd(
-        this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::ICOUNT), get_reg_ptr(arch::traits<ARCH>::ICOUNT)), this->gen_const(64U, 1));
-    this->builder.CreateStore(icount_val, get_reg_ptr(arch::traits<ARCH>::ICOUNT), false);
-}
-
-} // namespace ${coreDef.name.toLowerCase()}
-
-template <>
-std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
-    auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
-    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
-    return std::unique_ptr<vm_if>(ret);
-}
-} // namespace llvm
-} // namespace iss
-
-#include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_mu_p.h>
-#include <iss/factory.h>
-namespace iss {
-namespace {
-volatile std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|llvm", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
-		    auto vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
-		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            if(init_data){
-                auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*)>*>(init_data);
-                cpu->set_semihosting_callback(*cb);
-            }
-            return {cpu_ptr{cpu}, vm_ptr{vm}};
-        }),
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|llvm", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
-		    auto vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
-		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            if(init_data){
-                auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*)>*>(init_data);
-                cpu->set_semihosting_callback(*cb);
-            }
-            return {cpu_ptr{cpu}, vm_ptr{vm}};
-        })
-};
-}
-}
-// clang-format on

gen_input/templates/llvm/CORENAME_cyles.txt.gtl

@@ -0,0 +1,9 @@
+{ 
+	"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
+		{
+			"name"  : "${instr.name}",
+			"size"  : ${instr.length},
+			"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
+		}<%}%>
+	]
+}

gen_input/templates/llvm/incl-CORENAME.h.gtl

@@ -0,0 +1,223 @@
+/*******************************************************************************
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+<% 
+import com.minres.coredsl.coreDsl.Register
+import com.minres.coredsl.coreDsl.RegisterFile
+import com.minres.coredsl.coreDsl.RegisterAlias
+def getTypeSize(size){
+	if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
+}
+def getOriginalName(reg){
+    if( reg.original instanceof RegisterFile) {
+    	if( reg.index != null ) {
+        	return reg.original.name+generator.generateHostCode(reg.index)
+        } else {
+        	return reg.original.name
+        }
+    } else if(reg.original instanceof Register){
+        return reg.original.name
+    }
+}
+def getRegisterNames(){
+	def regNames = []
+ 	allRegs.each { reg -> 
+		if( reg instanceof RegisterFile) {
+			(reg.range.right..reg.range.left).each{
+    			regNames+=reg.name.toLowerCase()+it
+            }
+        } else if(reg instanceof Register){
+    		regNames+=reg.name.toLowerCase()
+        }
+    }
+    return regNames
+}
+def getRegisterAliasNames(){
+	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
+ 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
+		if( reg instanceof RegisterFile) {
+			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
+        } else if(reg instanceof Register){
+    		regMap[reg.name]?:reg.name.toLowerCase()
+        }
+ 	}.flatten()
+}
+%>
+#ifndef _${coreDef.name.toUpperCase()}_H_
+#define _${coreDef.name.toUpperCase()}_H_
+
+#include <array>
+#include <iss/arch/traits.h>
+#include <iss/arch_if.h>
+#include <iss/vm_if.h>
+
+namespace iss {
+namespace arch {
+
+struct ${coreDef.name.toLowerCase()};
+
+template <> struct traits<${coreDef.name.toLowerCase()}> {
+
+	constexpr static char const* const core_type = "${coreDef.name}";
+    
+  	static constexpr std::array<const char*, ${getRegisterNames().size}> reg_names{
+ 		{"${getRegisterNames().join("\", \"")}"}};
+ 
+  	static constexpr std::array<const char*, ${getRegisterAliasNames().size}> reg_aliases{
+ 		{"${getRegisterAliasNames().join("\", \"")}"}};
+
+    enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
+
+    constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
+
+    enum reg_e {<%
+     	allRegs.each { reg -> 
+    		if( reg instanceof RegisterFile) {
+    			(reg.range.right..reg.range.left).each{%>
+        ${reg.name}${it},<%
+                }
+            } else if(reg instanceof Register){ %>
+        ${reg.name},<%  
+            }
+        }%>
+        NUM_REGS,
+        NEXT_${pc.name}=NUM_REGS,
+        TRAP_STATE,
+        PENDING_TRAP,
+        MACHINE_STATE,
+        LAST_BRANCH,
+        ICOUNT<% 
+     	allRegs.each { reg -> 
+    		if(reg instanceof RegisterAlias){ def aliasname=getOriginalName(reg)%>,
+        ${reg.name} = ${aliasname}<%
+            }
+        }%>
+    };
+
+    using reg_t = uint${regDataWidth}_t;
+
+    using addr_t = uint${addrDataWidth}_t;
+
+    using code_word_t = uint${addrDataWidth}_t; //TODO: check removal
+
+    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
+
+    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
+
+ 	static constexpr std::array<const uint32_t, ${regSizes.size}> reg_bit_widths{
+ 		{${regSizes.join(",")}}};
+
+    static constexpr std::array<const uint32_t, ${regOffsets.size}> reg_byte_offsets{
+    	{${regOffsets.join(",")}}};
+
+    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
+
+    enum sreg_flag_e { FLAGS };
+
+    enum mem_type_e { ${allSpaces.collect{s -> s.name}.join(', ')} };
+};
+
+struct ${coreDef.name.toLowerCase()}: public arch_if {
+
+    using virt_addr_t = typename traits<${coreDef.name.toLowerCase()}>::virt_addr_t;
+    using phys_addr_t = typename traits<${coreDef.name.toLowerCase()}>::phys_addr_t;
+    using reg_t =  typename traits<${coreDef.name.toLowerCase()}>::reg_t;
+    using addr_t = typename traits<${coreDef.name.toLowerCase()}>::addr_t;
+
+    ${coreDef.name.toLowerCase()}();
+    ~${coreDef.name.toLowerCase()}();
+
+    void reset(uint64_t address=0) override;
+
+    uint8_t* get_regs_base_ptr() override;
+    /// deprecated
+    void get_reg(short idx, std::vector<uint8_t>& value) override {}
+    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
+    /// deprecated
+    bool get_flag(int flag) override {return false;}
+    void set_flag(int, bool value) override {};
+    /// deprecated
+    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
+
+    inline uint64_t get_icount() { return reg.icount; }
+
+    inline bool should_stop() { return interrupt_sim; }
+
+    inline uint64_t stop_code() { return interrupt_sim; }
+
+    inline phys_addr_t v2p(const iss::addr_t& addr){
+        if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
+                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
+            return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
+        } else
+            return virt2phys(addr);
+    }
+
+    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
+
+    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
+
+    inline uint32_t get_last_branch() { return reg.last_branch; }
+
+protected:
+    struct ${coreDef.name}_regs {<%
+     	allRegs.each { reg -> 
+    		if( reg instanceof RegisterFile) {
+    			(reg.range.right..reg.range.left).each{%>
+        uint${generator.getSize(reg)}_t ${reg.name}${it} = 0;<%
+                }
+            } else if(reg instanceof Register){ %>
+        uint${generator.getSize(reg)}_t ${reg.name} = 0;<%
+            }
+        }%>
+        uint${generator.getSize(pc)}_t NEXT_${pc.name} = 0;
+        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
+        uint64_t icount = 0;
+    } reg;
+
+    std::array<address_type, 4> addr_mode;
+    
+    uint64_t interrupt_sim=0;
+<%
+def fcsr = allRegs.find {it.name=='FCSR'}
+if(fcsr != null) {%>
+	uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
+	void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}		
+<%} else { %>
+	uint32_t get_fcsr(){return 0;}
+	void set_fcsr(uint32_t val){}
+<%}%>
+};
+
+}
+}            
+#endif /* _${coreDef.name.toUpperCase()}_H_ */

gen_input/templates/llvm/src-CORENAME.cpp.gtl

@@ -0,0 +1,107 @@
+/*******************************************************************************
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+ <% 
+import com.minres.coredsl.coreDsl.Register
+import com.minres.coredsl.coreDsl.RegisterFile
+import com.minres.coredsl.coreDsl.RegisterAlias
+def getOriginalName(reg){
+    if( reg.original instanceof RegisterFile) {
+    	if( reg.index != null ) {
+        	return reg.original.name+generator.generateHostCode(reg.index)
+        } else {
+        	return reg.original.name
+        }
+    } else if(reg.original instanceof Register){
+        return reg.original.name
+    }
+}
+def getRegisterNames(){
+	def regNames = []
+ 	allRegs.each { reg -> 
+		if( reg instanceof RegisterFile) {
+			(reg.range.right..reg.range.left).each{
+    			regNames+=reg.name.toLowerCase()+it
+            }
+        } else if(reg instanceof Register){
+    		regNames+=reg.name.toLowerCase()
+        }
+    }
+    return regNames
+}
+def getRegisterAliasNames(){
+	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
+ 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
+		if( reg instanceof RegisterFile) {
+			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
+        } else if(reg instanceof Register){
+    		regMap[reg.name]?:reg.name.toLowerCase()
+        }
+ 	}.flatten()
+}
+%>
+#include "util/ities.h"
+#include <util/logging.h>
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <cstdio>
+#include <cstring>
+#include <fstream>
+
+using namespace iss::arch;
+
+constexpr std::array<const char*, ${getRegisterNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
+constexpr std::array<const char*, ${getRegisterAliasNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
+constexpr std::array<const uint32_t, ${regSizes.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
+constexpr std::array<const uint32_t, ${regOffsets.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
+
+${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
+    reg.icount = 0;
+}
+
+${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
+
+void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
+    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
+    reg.PC=address;
+    reg.NEXT_PC=reg.PC;
+    reg.trap_state=0;
+    reg.machine_state=0x3;
+    reg.icount=0;
+}
+
+uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
+	return reinterpret_cast<uint8_t*>(&reg);
+}
+
+${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
+    return phys_addr_t(pc); // change logical address to physical address
+}
+

gen_input/templates/llvm/vm-vm_CORENAME.cpp.gtl

@@ -0,0 +1,325 @@
+/*******************************************************************************
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+#include <iss/debugger/gdb_session.h>
+#include <iss/debugger/server.h>
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <iss/arch/riscv_hart_m_p.h>
+#include <iss/iss.h>
+#include <iss/llvm/vm_base.h>
+#include <util/logging.h>
+
+#ifndef FMT_HEADER_ONLY
+#define FMT_HEADER_ONLY
+#endif
+#include <fmt/format.h>
+
+#include <array>
+#include <iss/debugger/riscv_target_adapter.h>
+
+namespace iss {
+namespace llvm {
+namespace fp_impl {
+void add_fp_functions_2_module(::llvm::Module *, unsigned, unsigned);
+}
+
+namespace ${coreDef.name.toLowerCase()} {
+using namespace ::llvm;
+using namespace iss::arch;
+using namespace iss::debugger;
+
+template <typename ARCH> class vm_impl : public iss::llvm::vm_base<ARCH> {
+public:
+    using super = typename iss::llvm::vm_base<ARCH>;
+    using virt_addr_t = typename super::virt_addr_t;
+    using phys_addr_t = typename super::phys_addr_t;
+    using code_word_t = typename super::code_word_t;
+    using addr_t = typename super::addr_t;
+
+    vm_impl();
+
+    vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
+
+    void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
+
+    target_adapter_if *accquire_target_adapter(server_if *srv) override {
+        debugger_if::dbg_enabled = true;
+        if (vm_base<ARCH>::tgt_adapter == nullptr)
+            vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
+        return vm_base<ARCH>::tgt_adapter;
+    }
+
+protected:
+    using vm_base<ARCH>::get_reg_ptr;
+
+    inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
+
+    template <typename T> inline ConstantInt *size(T type) {
+        return ConstantInt::get(getContext(), APInt(32, type->getType()->getScalarSizeInBits()));
+    }
+
+    void setup_module(Module* m) override {
+        super::setup_module(m);
+        iss::llvm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE, traits<ARCH>::XLEN);
+    }
+
+    inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) {
+        return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
+    }
+
+    std::tuple<continuation_e, BasicBlock *> gen_single_inst_behavior(virt_addr_t &, unsigned int &, BasicBlock *) override;
+
+    void gen_leave_behavior(BasicBlock *leave_blk) override;
+
+    void gen_raise_trap(uint16_t trap_id, uint16_t cause);
+
+    void gen_leave_trap(unsigned lvl);
+
+    void gen_wait(unsigned type);
+
+    void gen_trap_behavior(BasicBlock *) override;
+
+    void gen_trap_check(BasicBlock *bb);
+
+    inline Value *gen_reg_load(unsigned i, unsigned level = 0) {
+        return this->builder.CreateLoad(get_reg_ptr(i), false);
+    }
+
+    inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
+        Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits<ARCH>::XLEN, pc.val),
+                                                           this->get_type(traits<ARCH>::XLEN));
+        this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
+    }
+
+    // some compile time constants
+    // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
+    enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
+    enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
+    enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
+
+    using this_class = vm_impl<ARCH>;
+    using compile_func = std::tuple<continuation_e, BasicBlock *> (this_class::*)(virt_addr_t &pc,
+                                                                                  code_word_t instr,
+                                                                                  BasicBlock *bb);
+    std::array<compile_func, LUT_SIZE> lut;
+
+    std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
+    std::array<compile_func, LUT_SIZE> lut_11;
+
+	std::array<compile_func *, 4> qlut;
+
+	std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
+
+    void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
+                         compile_func f) {
+        if (pos < 0) {
+            lut[idx] = f;
+        } else {
+            auto bitmask = 1UL << pos;
+            if ((mask & bitmask) == 0) {
+                expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
+            } else {
+                if ((valid & bitmask) == 0) {
+                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
+                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
+                } else {
+                    auto new_val = idx << 1;
+                    if ((value & bitmask) != 0) new_val++;
+                    expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
+                }
+            }
+        }
+    }
+
+    inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
+
+    uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
+        if (pos >= 0) {
+            auto bitmask = 1UL << pos;
+            if ((mask & bitmask) == 0) {
+                lut_val = extract_fields(pos - 1, val, mask, lut_val);
+            } else {
+                auto new_val = lut_val << 1;
+                if ((val & bitmask) != 0) new_val++;
+                lut_val = extract_fields(pos - 1, val, mask, new_val);
+            }
+        }
+        return lut_val;
+    }
+
+private:
+    /****************************************************************************
+     * start opcode definitions
+     ****************************************************************************/
+    struct InstructionDesriptor {
+        size_t length;
+        uint32_t value;
+        uint32_t mask;
+        compile_func op;
+    };
+
+    const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
+         /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
+        /* instruction ${instr.instruction.name} */
+        {${instr.length}, ${instr.value}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
+    }};
+ 
+    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
+    /* instruction ${idx}: ${instr.name} */
+    std::tuple<continuation_e, BasicBlock*> __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){<%instr.code.eachLine{%>
+    	${it}<%}%>
+    }
+    <%}%>
+    /****************************************************************************
+     * end opcode definitions
+     ****************************************************************************/
+    std::tuple<continuation_e, BasicBlock *> illegal_intruction(virt_addr_t &pc, code_word_t instr, BasicBlock *bb) {
+		this->gen_sync(iss::PRE_SYNC, instr_descr.size());
+        this->builder.CreateStore(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), true),
+                                   get_reg_ptr(traits<ARCH>::PC), true);
+        this->builder.CreateStore(
+            this->builder.CreateAdd(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::ICOUNT), true),
+                                     this->gen_const(64U, 1)),
+            get_reg_ptr(traits<ARCH>::ICOUNT), true);
+        pc = pc + ((instr & 3) == 3 ? 4 : 2);
+        this->gen_raise_trap(0, 2);     // illegal instruction trap
+		this->gen_sync(iss::POST_SYNC, instr_descr.size());
+        this->gen_trap_check(this->leave_blk);
+        return std::make_tuple(BRANCH, nullptr);
+    }
+};
+
+template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
+    volatile CODE_WORD x = insn;
+    insn = 2 * x;
+}
+
+template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
+
+template <typename ARCH>
+vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
+: vm_base<ARCH>(core, core_id, cluster_id) {
+    qlut[0] = lut_00.data();
+    qlut[1] = lut_01.data();
+    qlut[2] = lut_10.data();
+    qlut[3] = lut_11.data();
+    for (auto instr : instr_descr) {
+        auto quantrant = instr.value & 0x3;
+        expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
+    }
+}
+
+template <typename ARCH>
+std::tuple<continuation_e, BasicBlock *>
+vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, BasicBlock *this_block) {
+    // we fetch at max 4 byte, alignment is 2
+    enum {TRAP_ID=1<<16};
+    code_word_t insn = 0;
+    const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
+    phys_addr_t paddr(pc);
+    auto *const data = (uint8_t *)&insn;
+    paddr = this->core.v2p(pc);
+    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
+        auto res = this->core.read(paddr, 2, data);
+        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+        if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
+            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
+        }
+    } else {
+        auto res = this->core.read(paddr, 4, data);
+        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+    }
+    if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+    // curr pc on stack
+    ++inst_cnt;
+    auto lut_val = extract_fields(insn);
+    auto f = qlut[insn & 0x3][lut_val];
+    if (f == nullptr) {
+        f = &this_class::illegal_intruction;
+    }
+    return (this->*f)(pc, insn, this_block);
+}
+
+template <typename ARCH> void vm_impl<ARCH>::gen_leave_behavior(BasicBlock *leave_blk) {
+    this->builder.SetInsertPoint(leave_blk);
+    this->builder.CreateRet(this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::NEXT_PC), false));
+}
+
+template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
+    auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
+    this->builder.CreateStore(TRAP_val, get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
+    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
+}
+
+template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
+    std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)) };
+    this->builder.CreateCall(this->mod->getFunction("leave_trap"), args);
+    auto *PC_val = this->gen_read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN / 8);
+    this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
+    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
+}
+
+template <typename ARCH> void vm_impl<ARCH>::gen_wait(unsigned type) {
+    std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, type)) };
+    this->builder.CreateCall(this->mod->getFunction("wait"), args);
+}
+
+template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(BasicBlock *trap_blk) {
+    this->builder.SetInsertPoint(trap_blk);
+    auto *trap_state_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
+    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
+                              get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
+    std::vector<Value *> args{this->core_ptr, this->adj_to64(trap_state_val),
+                              this->adj_to64(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::PC), false))};
+    this->builder.CreateCall(this->mod->getFunction("enter_trap"), args);
+    auto *trap_addr_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), false);
+    this->builder.CreateRet(trap_addr_val);
+}
+
+template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(BasicBlock *bb) {
+    auto *v = this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), true);
+    this->gen_cond_branch(this->builder.CreateICmp(
+                              ICmpInst::ICMP_EQ, v,
+                              ConstantInt::get(getContext(), APInt(v->getType()->getIntegerBitWidth(), 0))),
+                          bb, this->trap_blk, 1);
+}
+
+} // namespace ${coreDef.name.toLowerCase()}
+
+template <>
+std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
+    auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
+    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
+    return std::unique_ptr<vm_if>(ret);
+}
+} // namespace llvm
+} // namespace iss

gen_input/templates/tcc/CORENAME.cpp.gtl

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2020-2024 MINRES Technologies GmbH
+ * Copyright (C) 2020 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -29,7 +29,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
-// clang-format off
+
 #include <iss/arch/${coreDef.name.toLowerCase()}.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
@@ -37,10 +37,7 @@
 #include <iss/tcc/vm_base.h>
 #include <util/logging.h>
 #include <sstream>
-#include <iss/instruction_decoder.h>
+
-<%def fcsr = registers.find {it.name=='FCSR'}
-if(fcsr != null) {%>
-#include <vm/fp_functions.h><%}%>
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
 #endif
@@ -87,12 +84,7 @@ protected:
     using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, tu_builder&);
 
     inline const char *name(size_t index){return traits::reg_aliases.at(index);}
-<%
-if(fcsr != null) {%>
-    inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}   
 
-    void add_prologue(tu_builder& tu) override;
-<%}%>
     void setup_module(std::string m) override {
         super::setup_module(m);
     }
@@ -105,9 +97,7 @@ if(fcsr != null) {%>
 
     void gen_leave_trap(tu_builder& tu, unsigned lvl);
 
-    inline void gen_set_tval(tu_builder& tu, uint64_t new_tval);
+    void gen_wait(tu_builder& tu, unsigned type);
-
-    inline void gen_set_tval(tu_builder& tu, value new_tval);
 
     inline void gen_trap_check(tu_builder& tu) {
         tu("if(*trap_state!=0) goto trap_entry;");
@@ -130,7 +120,57 @@ if(fcsr != null) {%>
         }
     }
 
+    // some compile time constants
+    // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
+    enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
+    enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
+    enum { LUT_SIZE = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK32)), LUT_SIZE_C = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK16)) };
 
+    std::array<compile_func, LUT_SIZE> lut;
+
+    std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
+    std::array<compile_func, LUT_SIZE> lut_11;
+
+    std::array<compile_func *, 4> qlut;
+
+    std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
+
+    void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
+                         compile_func f) {
+        if (pos < 0) {
+            lut[idx] = f;
+        } else {
+            auto bitmask = 1UL << pos;
+            if ((mask & bitmask) == 0) {
+                expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
+            } else {
+                if ((valid & bitmask) == 0) {
+                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
+                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
+                } else {
+                    auto new_val = idx << 1;
+                    if ((value & bitmask) != 0) new_val++;
+                    expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
+                }
+            }
+        }
+    }
+
+    inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
+
+    uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
+        if (pos >= 0) {
+            auto bitmask = 1UL << pos;
+            if ((mask & bitmask) == 0) {
+                lut_val = extract_fields(pos - 1, val, mask, lut_val);
+            } else {
+                auto new_val = lut_val << 1;
+                if ((val & bitmask) != 0) new_val++;
+                lut_val = extract_fields(pos - 1, val, mask, new_val);
+            }
+        }
+        return lut_val;
+    }
     template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
     inline S sext(U from) {
         auto mask = (1ULL<<W) - 1;
@@ -138,48 +178,38 @@ if(fcsr != null) {%>
         return (from & mask) | ((from & sign_mask) ? ~mask : 0);
     }    
 
-<%functions.each{ it.eachLine { %>
-    ${it}<%}%>
-<%}%>
 private:
     /****************************************************************************
      * start opcode definitions
      ****************************************************************************/
-    struct instruction_descriptor {
+    struct InstructionDesriptor {
-        uint32_t length;
+        size_t length;
         uint32_t value;
         uint32_t mask;
         compile_func op;
     };
 
-    const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
+    const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
          /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
         /* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
         {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
     }};
  
-    //needs to be declared after instr_descr
-    decoder instr_decoder;
-
     /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
     /* instruction ${idx}: ${instr.name} */
     compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("${instr.name}_{:#010x}:", pc.val);
         vm_base<ARCH>::gen_sync(tu, PRE_SYNC,${idx});
-        uint64_t PC = pc.val;
         <%instr.fields.eachLine{%>${it}
         <%}%>if(this->disass_enabled){
             /* generate console output when executing the command */<%instr.disass.eachLine{%>
             ${it}<%}%>
-            tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
         pc=pc+ ${instr.length/8};
         gen_set_pc(tu, pc, traits::NEXT_PC);
-        tu.open_scope();
+        tu.open_scope();<%instr.behavior.eachLine{%>
-        this->gen_set_tval(tu, instr);
+        ${it}<%}%>
-        <%instr.behavior.eachLine{%>${it}
-        <%}%>
         tu.close_scope();
         vm_base<ARCH>::gen_sync(tu, POST_SYNC,${idx});
         gen_trap_check(tu);
@@ -189,125 +219,89 @@ private:
     /****************************************************************************
      * end opcode definitions
      ****************************************************************************/
-    compile_ret_t illegal_instruction(virt_addr_t &pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr, tu_builder& tu) {
         vm_impl::gen_sync(tu, iss::PRE_SYNC, instr_descr.size());
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, std::string("illegal_instruction"));
-        }
         pc = pc + ((instr & 3) == 3 ? 4 : 2);
-        gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+        gen_raise_trap(tu, 0, 2);     // illegal instruction trap
-        this->gen_set_tval(tu, instr);
         vm_impl::gen_sync(tu, iss::POST_SYNC, instr_descr.size());
         vm_impl::gen_trap_check(tu);
-        return ILLEGAL_INSTR;
+        return BRANCH;
     }
 };
 
-template <typename CODE_WORD> void debug_fn(CODE_WORD instr) {
+template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
-    volatile CODE_WORD x = instr;
+    volatile CODE_WORD x = insn;
-    instr = 2 * x;
+    insn = 2 * x;
 }
 
 template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
 
 template <typename ARCH>
 vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
-: vm_base<ARCH>(core, core_id, cluster_id)
+: vm_base<ARCH>(core, core_id, cluster_id) {
-, instr_decoder([this]() {
+    qlut[0] = lut_00.data();
-        std::vector<generic_instruction_descriptor> g_instr_descr;
+    qlut[1] = lut_01.data();
-        g_instr_descr.reserve(instr_descr.size());
+    qlut[2] = lut_10.data();
-        for (uint32_t i = 0; i < instr_descr.size(); ++i) {
+    qlut[3] = lut_11.data();
-            generic_instruction_descriptor new_instr_descr {instr_descr[i].value, instr_descr[i].mask, i};
+    for (auto instr : instr_descr) {
-            g_instr_descr.push_back(new_instr_descr);
+        auto quantrant = instr.value & 0x3;
+        expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
+    }
 }
-        return std::move(g_instr_descr);
-    }()) {}
 
 template <typename ARCH>
 std::tuple<continuation_e>
 vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, tu_builder& tu) {
     // we fetch at max 4 byte, alignment is 2
     enum {TRAP_ID=1<<16};
-    code_word_t instr = 0;
+    code_word_t insn = 0;
+    // const typename traits::addr_t upper_bits = ~traits::PGMASK;
     phys_addr_t paddr(pc);
-    if(this->core.has_mmu())
+    auto *const data = (uint8_t *)&insn;
-        paddr = this->core.virt2phys(pc);
+    paddr = this->core.v2p(pc);
-    auto res = this->core.read(paddr, 4, reinterpret_cast<uint8_t*>(&instr));
+//    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
-    if (res != iss::Ok)
+//        auto res = this->core.read(paddr, 2, data);
-        return ILLEGAL_FETCH;
+//        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-    if (instr == 0x0000006f || (instr&0xffff)==0xa001) 
+//        if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
-        return JUMP_TO_SELF;
+//            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
+//        }
+//    } else {
+        auto res = this->core.read(paddr, 4, data);
+        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+//    }
+    if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+    // curr pc on stack
     ++inst_cnt;
-    uint32_t inst_index = instr_decoder.decode_instr(instr);
+    auto lut_val = extract_fields(insn);
-    compile_func f = nullptr;
+    auto f = qlut[insn & 0x3][lut_val];
-    if(inst_index < instr_descr.size())
-        f = instr_descr[inst_index].op;
     if (f == nullptr) {
-        f = &this_class::illegal_instruction;
+        f = &this_class::illegal_intruction;
     }
-    return (this->*f)(pc, instr, tu);
+    return (this->*f)(pc, insn, tu);
 }
 
 template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) {
     tu("  *trap_state = {:#x};", 0x80 << 24 | (cause << 16) | trap_id);
+    tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits<uint32_t>::max(), 32));
 }
 
 template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsigned lvl) {
     tu("leave_trap(core_ptr, {});", lvl);
     tu.store(traits::NEXT_PC, tu.read_mem(traits::CSR, (lvl << 8) + 0x41, traits::XLEN));
-    tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(UNKNOWN_JUMP), 32));
+    tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits<uint32_t>::max(), 32));
 }
 
-template <typename ARCH> void vm_impl<ARCH>::gen_set_tval(tu_builder& tu, uint64_t new_tval) {
+template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned type) {
-    tu(fmt::format("tval = {};", new_tval));
-}
-template <typename ARCH> void vm_impl<ARCH>::gen_set_tval(tu_builder& tu, value new_tval) {
-    tu(fmt::format("tval = {};", new_tval.str));
 }
 
 template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
     tu("trap_entry:");
-    this->gen_sync(tu, POST_SYNC, -1);    
+    tu("enter_trap(core_ptr, *trap_state, *pc, 0);");
-    tu("enter_trap(core_ptr, *trap_state, *pc, tval);");
+    tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits<uint32_t>::max(),32));
-    tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(UNKNOWN_JUMP),32));
     tu("return *next_pc;");
 }
-<%
-if(fcsr != null) {%>
-template <typename ARCH> void vm_impl<ARCH>::add_prologue(tu_builder& tu){
-    std::ostringstream os;
-    os << "uint32_t (*fget_flags)()=" << (uintptr_t)&fget_flags << ";\\n";
-    os << "uint32_t (*fadd_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fadd_s << ";\\n";
-    os << "uint32_t (*fsub_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fsub_s << ";\\n";
-    os << "uint32_t (*fmul_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fmul_s << ";\\n";
-    os << "uint32_t (*fdiv_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fdiv_s << ";\\n";
-    os << "uint32_t (*fsqrt_s)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&fsqrt_s << ";\\n";
-    os << "uint32_t (*fcmp_s)(uint32_t v1, uint32_t v2, uint32_t op)=" << (uintptr_t)&fcmp_s << ";\\n";
-    os << "uint32_t (*fcvt_s)(uint32_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_s << ";\\n";
-    os << "uint32_t (*fmadd_s)(uint32_t v1, uint32_t v2, uint32_t v3, uint32_t op, uint8_t mode)=" << (uintptr_t)&fmadd_s << ";\\n";
-    os << "uint32_t (*fsel_s)(uint32_t v1, uint32_t v2, uint32_t op)=" << (uintptr_t)&fsel_s << ";\\n";
-    os << "uint32_t (*fclass_s)( uint32_t v1 )=" << (uintptr_t)&fclass_s << ";\\n";
-    os << "uint32_t (*fconv_d2f)(uint64_t v1, uint8_t mode)=" << (uintptr_t)&fconv_d2f << ";\\n";
-    os << "uint64_t (*fconv_f2d)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&fconv_f2d << ";\\n";
-    os << "uint64_t (*fadd_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fadd_d << ";\\n";
-    os << "uint64_t (*fsub_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fsub_d << ";\\n";
-    os << "uint64_t (*fmul_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fmul_d << ";\\n";
-    os << "uint64_t (*fdiv_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fdiv_d << ";\\n";
-    os << "uint64_t (*fsqrt_d)(uint64_t v1, uint8_t mode)=" << (uintptr_t)&fsqrt_d << ";\\n";
-    os << "uint64_t (*fcmp_d)(uint64_t v1, uint64_t v2, uint32_t op)=" << (uintptr_t)&fcmp_d << ";\\n";
-    os << "uint64_t (*fcvt_d)(uint64_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_d << ";\\n";
-    os << "uint64_t (*fmadd_d)(uint64_t v1, uint64_t v2, uint64_t v3, uint32_t op, uint8_t mode)=" << (uintptr_t)&fmadd_d << ";\\n";
-    os << "uint64_t (*fsel_d)(uint64_t v1, uint64_t v2, uint32_t op)=" << (uintptr_t)&fsel_d << ";\\n";
-    os << "uint64_t (*fclass_d)(uint64_t v1  )=" << (uintptr_t)&fclass_d << ";\\n";
-    os << "uint64_t (*fcvt_32_64)(uint32_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_32_64 << ";\\n";
-    os << "uint32_t (*fcvt_64_32)(uint64_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_64_32 << ";\\n";
-    os << "uint32_t (*unbox_s)(uint64_t v)=" << (uintptr_t)&unbox_s << ";\\n";
-    tu.add_prologue(os.str());
-}
-<%}%>
 
-} // namespace ${coreDef.name.toLowerCase()}
+} // namespace mnrv32
 
 template <>
 std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
@@ -318,33 +312,29 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
 } // namesapce tcc
 } // namespace iss
 
+#include <iss/factory.h>
 #include <iss/arch/riscv_hart_m_p.h>
 #include <iss/arch/riscv_hart_mu_p.h>
-#include <iss/factory.h>
 namespace iss {
 namespace {
-volatile std::array<bool, 2> dummy = {
+std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
             auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
 		    auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
 		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            if(init_data){
-                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
-                cpu->set_semihosting_callback(*cb);
-            }
             return {cpu_ptr{cpu}, vm_ptr{vm}};
         }),
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|tcc", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
             auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
 		    auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
 		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            if(init_data){
-                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
-                cpu->set_semihosting_callback(*cb);
-            }
             return {cpu_ptr{cpu}, vm_ptr{vm}};
         })
 };
 }
 }
-// clang-format on
+extern "C" {
+	bool* get_${coreDef.name.toLowerCase()}_tcc_creators() {
+		return iss::dummy.data();
+	}
+}

softfloat/.gitignore

@@ -1,2 +0,0 @@
-build/*/*.o
-build/*/*.a

softfloat/CMakeLists.txt

@@ -327,7 +327,7 @@ set(OTHERS
 
 set(LIB_SOURCES ${PRIMITIVES} ${SPECIALIZE} ${OTHERS})
 
-add_library(softfloat STATIC ${LIB_SOURCES})
+add_library(softfloat ${LIB_SOURCES})
 set_property(TARGET softfloat PROPERTY C_STANDARD 99)
 target_compile_definitions(softfloat PRIVATE 
 	SOFTFLOAT_ROUND_ODD 
@@ -347,7 +347,7 @@ set_target_properties(softfloat PROPERTIES
 
 install(TARGETS softfloat
   EXPORT ${PROJECT_NAME}Targets            # for downstream dependencies
-  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}/static COMPONENT libs   # static lib
+  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs   # static lib
   LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs   # shared lib
   FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs # for mac
   PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} COMPONENT devel   # headers for mac (note the different component -> different package)

softfloat/README.md

@@ -1,24 +0,0 @@
-
-Package Overview for Berkeley SoftFloat Release 3e
-==================================================
-
-John R. Hauser<br>
-2018 January 20
-
-
-Berkeley SoftFloat is a software implementation of binary floating-point
-that conforms to the IEEE Standard for Floating-Point Arithmetic.  SoftFloat
-is distributed in the form of C source code.  Building the SoftFloat sources
-generates a library file (typically `softfloat.a` or `libsoftfloat.a`)
-containing the floating-point subroutines.
-
-
-The SoftFloat package is documented in the following files in the `doc`
-subdirectory:
-
-* [SoftFloat.html](http://www.jhauser.us/arithmetic/SoftFloat-3/doc/SoftFloat.html) Documentation for using the SoftFloat functions.
-* [SoftFloat-source.html](http://www.jhauser.us/arithmetic/SoftFloat-3/doc/SoftFloat-source.html) Documentation for building SoftFloat.
-* [SoftFloat-history.html](http://www.jhauser.us/arithmetic/SoftFloat-3/doc/SoftFloat-history.html) History of the major changes to SoftFloat.
-
-Other files in the package comprise the source code for SoftFloat.
-

softfloat/build/Linux-RISCV64-GCC/Makefile

@@ -1,399 +0,0 @@
-
-#=============================================================================
-#
-# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
-# Package, Release 3e, by John R. Hauser.
-#
-# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
-# University of California.  All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#
-#  1. Redistributions of source code must retain the above copyright notice,
-#     this list of conditions, and the following disclaimer.
-#
-#  2. Redistributions in binary form must reproduce the above copyright
-#     notice, this list of conditions, and the following disclaimer in the
-#     documentation and/or other materials provided with the distribution.
-#
-#  3. Neither the name of the University nor the names of its contributors
-#     may be used to endorse or promote products derived from this software
-#     without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-#=============================================================================
-
-SOURCE_DIR ?= ../../source
-SPECIALIZE_TYPE ?= RISCV
-MARCH ?= rv64gcv_zfh_zfhmin
-MABI ?= lp64d
-
-SOFTFLOAT_OPTS ?= \
-  -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
-  -DSOFTFLOAT_FAST_DIV64TO32
-
-DELETE = rm -f
-C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
-COMPILE_C = \
-  riscv64-unknown-linux-gnu-gcc -c -march=$(MARCH) -mabi=$(MABI) -Werror-implicit-function-declaration -DSOFTFLOAT_FAST_INT64 \
-    $(SOFTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@
-MAKELIB = ar crs $@
-
-OBJ = .o
-LIB = .a
-
-OTHER_HEADERS = $(SOURCE_DIR)/include/opts-GCC.h
-
-.PHONY: all
-all: softfloat$(LIB)
-
-OBJS_PRIMITIVES = \
-  s_eq128$(OBJ) \
-  s_le128$(OBJ) \
-  s_lt128$(OBJ) \
-  s_shortShiftLeft128$(OBJ) \
-  s_shortShiftRight128$(OBJ) \
-  s_shortShiftRightJam64$(OBJ) \
-  s_shortShiftRightJam64Extra$(OBJ) \
-  s_shortShiftRightJam128$(OBJ) \
-  s_shortShiftRightJam128Extra$(OBJ) \
-  s_shiftRightJam32$(OBJ) \
-  s_shiftRightJam64$(OBJ) \
-  s_shiftRightJam64Extra$(OBJ) \
-  s_shiftRightJam128$(OBJ) \
-  s_shiftRightJam128Extra$(OBJ) \
-  s_shiftRightJam256M$(OBJ) \
-  s_countLeadingZeros8$(OBJ) \
-  s_countLeadingZeros16$(OBJ) \
-  s_countLeadingZeros32$(OBJ) \
-  s_countLeadingZeros64$(OBJ) \
-  s_add128$(OBJ) \
-  s_add256M$(OBJ) \
-  s_sub128$(OBJ) \
-  s_sub256M$(OBJ) \
-  s_mul64ByShifted32To128$(OBJ) \
-  s_mul64To128$(OBJ) \
-  s_mul128By32$(OBJ) \
-  s_mul128To256M$(OBJ) \
-  s_approxRecip_1Ks$(OBJ) \
-  s_approxRecip32_1$(OBJ) \
-  s_approxRecipSqrt_1Ks$(OBJ) \
-  s_approxRecipSqrt32_1$(OBJ) \
-
-OBJS_SPECIALIZE = \
-  softfloat_raiseFlags$(OBJ) \
-  s_f16UIToCommonNaN$(OBJ) \
-  s_commonNaNToF16UI$(OBJ) \
-  s_propagateNaNF16UI$(OBJ) \
-  s_bf16UIToCommonNaN$(OBJ) \
-  s_commonNaNToBF16UI$(OBJ) \
-  s_f32UIToCommonNaN$(OBJ) \
-  s_commonNaNToF32UI$(OBJ) \
-  s_propagateNaNF32UI$(OBJ) \
-  s_f64UIToCommonNaN$(OBJ) \
-  s_commonNaNToF64UI$(OBJ) \
-  s_propagateNaNF64UI$(OBJ) \
-  extF80M_isSignalingNaN$(OBJ) \
-  s_extF80UIToCommonNaN$(OBJ) \
-  s_commonNaNToExtF80UI$(OBJ) \
-  s_propagateNaNExtF80UI$(OBJ) \
-  f128M_isSignalingNaN$(OBJ) \
-  s_f128UIToCommonNaN$(OBJ) \
-  s_commonNaNToF128UI$(OBJ) \
-  s_propagateNaNF128UI$(OBJ) \
-
-OBJS_OTHERS = \
-  s_roundToUI32$(OBJ) \
-  s_roundToUI64$(OBJ) \
-  s_roundToI32$(OBJ) \
-  s_roundToI64$(OBJ) \
-  s_normSubnormalBF16Sig$(OBJ) \
-  s_roundPackToBF16$(OBJ) \
-  s_normSubnormalF16Sig$(OBJ) \
-  s_roundPackToF16$(OBJ) \
-  s_normRoundPackToF16$(OBJ) \
-  s_addMagsF16$(OBJ) \
-  s_subMagsF16$(OBJ) \
-  s_mulAddF16$(OBJ) \
-  s_normSubnormalF32Sig$(OBJ) \
-  s_roundPackToF32$(OBJ) \
-  s_normRoundPackToF32$(OBJ) \
-  s_addMagsF32$(OBJ) \
-  s_subMagsF32$(OBJ) \
-  s_mulAddF32$(OBJ) \
-  s_normSubnormalF64Sig$(OBJ) \
-  s_roundPackToF64$(OBJ) \
-  s_normRoundPackToF64$(OBJ) \
-  s_addMagsF64$(OBJ) \
-  s_subMagsF64$(OBJ) \
-  s_mulAddF64$(OBJ) \
-  s_normSubnormalExtF80Sig$(OBJ) \
-  s_roundPackToExtF80$(OBJ) \
-  s_normRoundPackToExtF80$(OBJ) \
-  s_addMagsExtF80$(OBJ) \
-  s_subMagsExtF80$(OBJ) \
-  s_normSubnormalF128Sig$(OBJ) \
-  s_roundPackToF128$(OBJ) \
-  s_normRoundPackToF128$(OBJ) \
-  s_addMagsF128$(OBJ) \
-  s_subMagsF128$(OBJ) \
-  s_mulAddF128$(OBJ) \
-  softfloat_state$(OBJ) \
-  ui32_to_f16$(OBJ) \
-  ui32_to_f32$(OBJ) \
-  ui32_to_f64$(OBJ) \
-  ui32_to_extF80$(OBJ) \
-  ui32_to_extF80M$(OBJ) \
-  ui32_to_f128$(OBJ) \
-  ui32_to_f128M$(OBJ) \
-  ui64_to_f16$(OBJ) \
-  ui64_to_f32$(OBJ) \
-  ui64_to_f64$(OBJ) \
-  ui64_to_extF80$(OBJ) \
-  ui64_to_extF80M$(OBJ) \
-  ui64_to_f128$(OBJ) \
-  ui64_to_f128M$(OBJ) \
-  i32_to_f16$(OBJ) \
-  i32_to_f32$(OBJ) \
-  i32_to_f64$(OBJ) \
-  i32_to_extF80$(OBJ) \
-  i32_to_extF80M$(OBJ) \
-  i32_to_f128$(OBJ) \
-  i32_to_f128M$(OBJ) \
-  i64_to_f16$(OBJ) \
-  i64_to_f32$(OBJ) \
-  i64_to_f64$(OBJ) \
-  i64_to_extF80$(OBJ) \
-  i64_to_extF80M$(OBJ) \
-  i64_to_f128$(OBJ) \
-  i64_to_f128M$(OBJ) \
-  bf16_isSignalingNaN$(OBJ) \
-  bf16_to_f32$(OBJ) \
-  f16_to_ui32$(OBJ) \
-  f16_to_ui64$(OBJ) \
-  f16_to_i32$(OBJ) \
-  f16_to_i64$(OBJ) \
-  f16_to_ui32_r_minMag$(OBJ) \
-  f16_to_ui64_r_minMag$(OBJ) \
-  f16_to_i32_r_minMag$(OBJ) \
-  f16_to_i64_r_minMag$(OBJ) \
-  f16_to_f32$(OBJ) \
-  f16_to_f64$(OBJ) \
-  f16_to_extF80$(OBJ) \
-  f16_to_extF80M$(OBJ) \
-  f16_to_f128$(OBJ) \
-  f16_to_f128M$(OBJ) \
-  f16_roundToInt$(OBJ) \
-  f16_add$(OBJ) \
-  f16_sub$(OBJ) \
-  f16_mul$(OBJ) \
-  f16_mulAdd$(OBJ) \
-  f16_div$(OBJ) \
-  f16_rem$(OBJ) \
-  f16_sqrt$(OBJ) \
-  f16_eq$(OBJ) \
-  f16_le$(OBJ) \
-  f16_lt$(OBJ) \
-  f16_eq_signaling$(OBJ) \
-  f16_le_quiet$(OBJ) \
-  f16_lt_quiet$(OBJ) \
-  f16_isSignalingNaN$(OBJ) \
-  f32_to_ui32$(OBJ) \
-  f32_to_ui64$(OBJ) \
-  f32_to_i32$(OBJ) \
-  f32_to_i64$(OBJ) \
-  f32_to_ui32_r_minMag$(OBJ) \
-  f32_to_ui64_r_minMag$(OBJ) \
-  f32_to_i32_r_minMag$(OBJ) \
-  f32_to_i64_r_minMag$(OBJ) \
-  f32_to_bf16$(OBJ) \
-  f32_to_f16$(OBJ) \
-  f32_to_f64$(OBJ) \
-  f32_to_extF80$(OBJ) \
-  f32_to_extF80M$(OBJ) \
-  f32_to_f128$(OBJ) \
-  f32_to_f128M$(OBJ) \
-  f32_roundToInt$(OBJ) \
-  f32_add$(OBJ) \
-  f32_sub$(OBJ) \
-  f32_mul$(OBJ) \
-  f32_mulAdd$(OBJ) \
-  f32_div$(OBJ) \
-  f32_rem$(OBJ) \
-  f32_sqrt$(OBJ) \
-  f32_eq$(OBJ) \
-  f32_le$(OBJ) \
-  f32_lt$(OBJ) \
-  f32_eq_signaling$(OBJ) \
-  f32_le_quiet$(OBJ) \
-  f32_lt_quiet$(OBJ) \
-  f32_isSignalingNaN$(OBJ) \
-  f64_to_ui32$(OBJ) \
-  f64_to_ui64$(OBJ) \
-  f64_to_i32$(OBJ) \
-  f64_to_i64$(OBJ) \
-  f64_to_ui32_r_minMag$(OBJ) \
-  f64_to_ui64_r_minMag$(OBJ) \
-  f64_to_i32_r_minMag$(OBJ) \
-  f64_to_i64_r_minMag$(OBJ) \
-  f64_to_f16$(OBJ) \
-  f64_to_f32$(OBJ) \
-  f64_to_extF80$(OBJ) \
-  f64_to_extF80M$(OBJ) \
-  f64_to_f128$(OBJ) \
-  f64_to_f128M$(OBJ) \
-  f64_roundToInt$(OBJ) \
-  f64_add$(OBJ) \
-  f64_sub$(OBJ) \
-  f64_mul$(OBJ) \
-  f64_mulAdd$(OBJ) \
-  f64_div$(OBJ) \
-  f64_rem$(OBJ) \
-  f64_sqrt$(OBJ) \
-  f64_eq$(OBJ) \
-  f64_le$(OBJ) \
-  f64_lt$(OBJ) \
-  f64_eq_signaling$(OBJ) \
-  f64_le_quiet$(OBJ) \
-  f64_lt_quiet$(OBJ) \
-  f64_isSignalingNaN$(OBJ) \
-  extF80_to_ui32$(OBJ) \
-  extF80_to_ui64$(OBJ) \
-  extF80_to_i32$(OBJ) \
-  extF80_to_i64$(OBJ) \
-  extF80_to_ui32_r_minMag$(OBJ) \
-  extF80_to_ui64_r_minMag$(OBJ) \
-  extF80_to_i32_r_minMag$(OBJ) \
-  extF80_to_i64_r_minMag$(OBJ) \
-  extF80_to_f16$(OBJ) \
-  extF80_to_f32$(OBJ) \
-  extF80_to_f64$(OBJ) \
-  extF80_to_f128$(OBJ) \
-  extF80_roundToInt$(OBJ) \
-  extF80_add$(OBJ) \
-  extF80_sub$(OBJ) \
-  extF80_mul$(OBJ) \
-  extF80_div$(OBJ) \
-  extF80_rem$(OBJ) \
-  extF80_sqrt$(OBJ) \
-  extF80_eq$(OBJ) \
-  extF80_le$(OBJ) \
-  extF80_lt$(OBJ) \
-  extF80_eq_signaling$(OBJ) \
-  extF80_le_quiet$(OBJ) \
-  extF80_lt_quiet$(OBJ) \
-  extF80_isSignalingNaN$(OBJ) \
-  extF80M_to_ui32$(OBJ) \
-  extF80M_to_ui64$(OBJ) \
-  extF80M_to_i32$(OBJ) \
-  extF80M_to_i64$(OBJ) \
-  extF80M_to_ui32_r_minMag$(OBJ) \
-  extF80M_to_ui64_r_minMag$(OBJ) \
-  extF80M_to_i32_r_minMag$(OBJ) \
-  extF80M_to_i64_r_minMag$(OBJ) \
-  extF80M_to_f16$(OBJ) \
-  extF80M_to_f32$(OBJ) \
-  extF80M_to_f64$(OBJ) \
-  extF80M_to_f128M$(OBJ) \
-  extF80M_roundToInt$(OBJ) \
-  extF80M_add$(OBJ) \
-  extF80M_sub$(OBJ) \
-  extF80M_mul$(OBJ) \
-  extF80M_div$(OBJ) \
-  extF80M_rem$(OBJ) \
-  extF80M_sqrt$(OBJ) \
-  extF80M_eq$(OBJ) \
-  extF80M_le$(OBJ) \
-  extF80M_lt$(OBJ) \
-  extF80M_eq_signaling$(OBJ) \
-  extF80M_le_quiet$(OBJ) \
-  extF80M_lt_quiet$(OBJ) \
-  f128_to_ui32$(OBJ) \
-  f128_to_ui64$(OBJ) \
-  f128_to_i32$(OBJ) \
-  f128_to_i64$(OBJ) \
-  f128_to_ui32_r_minMag$(OBJ) \
-  f128_to_ui64_r_minMag$(OBJ) \
-  f128_to_i32_r_minMag$(OBJ) \
-  f128_to_i64_r_minMag$(OBJ) \
-  f128_to_f16$(OBJ) \
-  f128_to_f32$(OBJ) \
-  f128_to_extF80$(OBJ) \
-  f128_to_f64$(OBJ) \
-  f128_roundToInt$(OBJ) \
-  f128_add$(OBJ) \
-  f128_sub$(OBJ) \
-  f128_mul$(OBJ) \
-  f128_mulAdd$(OBJ) \
-  f128_div$(OBJ) \
-  f128_rem$(OBJ) \
-  f128_sqrt$(OBJ) \
-  f128_eq$(OBJ) \
-  f128_le$(OBJ) \
-  f128_lt$(OBJ) \
-  f128_eq_signaling$(OBJ) \
-  f128_le_quiet$(OBJ) \
-  f128_lt_quiet$(OBJ) \
-  f128_isSignalingNaN$(OBJ) \
-  f128M_to_ui32$(OBJ) \
-  f128M_to_ui64$(OBJ) \
-  f128M_to_i32$(OBJ) \
-  f128M_to_i64$(OBJ) \
-  f128M_to_ui32_r_minMag$(OBJ) \
-  f128M_to_ui64_r_minMag$(OBJ) \
-  f128M_to_i32_r_minMag$(OBJ) \
-  f128M_to_i64_r_minMag$(OBJ) \
-  f128M_to_f16$(OBJ) \
-  f128M_to_f32$(OBJ) \
-  f128M_to_extF80M$(OBJ) \
-  f128M_to_f64$(OBJ) \
-  f128M_roundToInt$(OBJ) \
-  f128M_add$(OBJ) \
-  f128M_sub$(OBJ) \
-  f128M_mul$(OBJ) \
-  f128M_mulAdd$(OBJ) \
-  f128M_div$(OBJ) \
-  f128M_rem$(OBJ) \
-  f128M_sqrt$(OBJ) \
-  f128M_eq$(OBJ) \
-  f128M_le$(OBJ) \
-  f128M_lt$(OBJ) \
-  f128M_eq_signaling$(OBJ) \
-  f128M_le_quiet$(OBJ) \
-  f128M_lt_quiet$(OBJ) \
-
-OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
-
-$(OBJS_ALL): \
-  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
-  $(SOURCE_DIR)/include/primitives.h
-$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
-  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
-  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
-  $(SOURCE_DIR)/include/softfloat.h
-
-$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
-	$(COMPILE_C) $(SOURCE_DIR)/$*.c
-
-$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
-	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
-
-softfloat$(LIB): $(OBJS_ALL)
-	$(DELETE) $@
-	$(MAKELIB) $^
-
-.PHONY: clean
-clean:
-	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
-

softfloat/build/Linux-RISCV64-GCC/platform.h

@@ -1,54 +0,0 @@
-
-/*============================================================================
-
-This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
-
-Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
-University of California.  All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
-
- 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
-    specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-=============================================================================*/
-
-/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
-#define LITTLEENDIAN 1
-
-/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
-#ifdef __GNUC_STDC_INLINE__
-#define INLINE inline
-#else
-#define INLINE extern inline
-#endif
-
-/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
-#define SOFTFLOAT_BUILTIN_CLZ 1
-#define SOFTFLOAT_INTRINSIC_INT128 1
-#include "opts-GCC.h"
-

softfloat/build/Linux-x86_64-GCC/Makefile

@@ -94,8 +94,6 @@ OBJS_SPECIALIZE = \
   s_f16UIToCommonNaN$(OBJ) \
   s_commonNaNToF16UI$(OBJ) \
   s_propagateNaNF16UI$(OBJ) \
-  s_bf16UIToCommonNaN$(OBJ) \
-  s_commonNaNToBF16UI$(OBJ) \
   s_f32UIToCommonNaN$(OBJ) \
   s_commonNaNToF32UI$(OBJ) \
   s_propagateNaNF32UI$(OBJ) \
@@ -116,8 +114,6 @@ OBJS_OTHERS = \
   s_roundToUI64$(OBJ) \
   s_roundToI32$(OBJ) \
   s_roundToI64$(OBJ) \
-  s_normSubnormalBF16Sig$(OBJ) \
-  s_roundPackToBF16$(OBJ) \
   s_normSubnormalF16Sig$(OBJ) \
   s_roundPackToF16$(OBJ) \
   s_normRoundPackToF16$(OBJ) \
@@ -176,8 +172,6 @@ OBJS_OTHERS = \
   i64_to_extF80M$(OBJ) \
   i64_to_f128$(OBJ) \
   i64_to_f128M$(OBJ) \
-  bf16_isSignalingNaN$(OBJ) \
-  bf16_to_f32$(OBJ) \
   f16_to_ui32$(OBJ) \
   f16_to_ui64$(OBJ) \
   f16_to_i32$(OBJ) \
@@ -215,7 +209,6 @@ OBJS_OTHERS = \
   f32_to_ui64_r_minMag$(OBJ) \
   f32_to_i32_r_minMag$(OBJ) \
   f32_to_i64_r_minMag$(OBJ) \
-  f32_to_bf16$(OBJ) \
   f32_to_f16$(OBJ) \
   f32_to_f64$(OBJ) \
   f32_to_extF80$(OBJ) \

softfloat/build/Linux-x86_64-GCC/platform.h

@@ -54,3 +54,4 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #define SOFTFLOAT_INTRINSIC_INT128 1
 #endif
 #include "opts-GCC.h"
+

softfloat/build/template-FAST_INT64/Makefile

@@ -115,8 +115,6 @@ OBJS_OTHERS = \
   s_roundToUI64$(OBJ) \
   s_roundToI32$(OBJ) \
   s_roundToI64$(OBJ) \
-  s_normSubnormalBF16Sig$(OBJ) \
-  s_roundPackToBF16$(OBJ) \
   s_normSubnormalF16Sig$(OBJ) \
   s_roundPackToF16$(OBJ) \
   s_normRoundPackToF16$(OBJ) \
@@ -175,8 +173,6 @@ OBJS_OTHERS = \
   i64_to_extF80M$(OBJ) \
   i64_to_f128$(OBJ) \
   i64_to_f128M$(OBJ) \
-  bf16_isSignalingNaN$(OBJ) \
-  bf16_to_f32$(OBJ) \
   f16_to_ui32$(OBJ) \
   f16_to_ui64$(OBJ) \
   f16_to_i32$(OBJ) \
@@ -214,7 +210,6 @@ OBJS_OTHERS = \
   f32_to_ui64_r_minMag$(OBJ) \
   f32_to_i32_r_minMag$(OBJ) \
   f32_to_i64_r_minMag$(OBJ) \
-  f32_to_bf16$(OBJ) \
   f32_to_f16$(OBJ) \
   f32_to_f64$(OBJ) \
   f32_to_extF80$(OBJ) \

softfloat/doc/SoftFloat.html

@@ -508,7 +508,7 @@ significant extra cost.
 On computers where the word size is <NOBR>64 bits</NOBR> or larger, both
 function versions (<CODE>f128M_add</CODE> and <CODE>f128_add</CODE>) are
 provided, because the cost of passing by value is then more reasonable.
-Applications that must be portable across both classes of computers must use
+Applications that must be portable accross both classes of computers must use
 the pointer-based functions, as these are always implemented.
 However, if it is known that SoftFloat includes the by-value functions for all
 platforms of interest, programmers can use whichever version they prefer.

softfloat/source/8086-SSE/s_bf16UIToCommonNaN.c

@@ -1,59 +0,0 @@
-
-/*============================================================================
-
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
-
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
-
- 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
-    specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-=============================================================================*/
-
-#include <stdint.h>
-#include "platform.h"
-#include "specialize.h"
-#include "softfloat.h"
-
-/*----------------------------------------------------------------------------
-| Assuming `uiA' has the bit pattern of a BF16 NaN, converts
-| this NaN to the common NaN form, and stores the resulting common NaN at the
-| location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
-| exception is raised.
-*----------------------------------------------------------------------------*/
-void softfloat_bf16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr )
-{
-
-    if ( softfloat_isSigNaNBF16UI( uiA ) ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
-    }
-    zPtr->sign = uiA>>15;
-    zPtr->v64  = (uint_fast64_t) uiA<<56;
-    zPtr->v0   = 0;
-
-}
-

softfloat/source/8086-SSE/s_commonNaNToBF16UI.c

@@ -1,51 +0,0 @@
-
-/*============================================================================
-
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
-
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
-
- 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
-    specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-=============================================================================*/
-
-#include <stdint.h>
-#include "platform.h"
-#include "specialize.h"
-
-/*----------------------------------------------------------------------------
-| Converts the common NaN pointed to by `aPtr' into a BF16 NaN, and 
-| returns the bit pattern of this value as an unsigned integer.
-*----------------------------------------------------------------------------*/
-uint_fast16_t softfloat_commonNaNToBF16UI( const struct commonNaN *aPtr )
-{
-
-    return (uint_fast16_t) aPtr->sign<<15 | 0x7FC0 | aPtr->v64>>56;
-
-}
-

softfloat/source/8086-SSE/specialize.h

@@ -37,10 +37,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifndef specialize_h
 #define specialize_h 1
 
-#include "primitiveTypes.h"
-#include "softfloat.h"
 #include <stdbool.h>
 #include <stdint.h>
+#include "primitiveTypes.h"
+#include "softfloat.h"
 
 /*----------------------------------------------------------------------------
 | Default value for 'softfloat_detectTininess'.
@@ -114,28 +114,8 @@ uint_fast16_t softfloat_commonNaNToF16UI(const struct commonNaN* aPtr);
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB);
+uint_fast16_t
-
+ softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB );
-/*----------------------------------------------------------------------------
-| Returns true when 16-bit unsigned integer 'uiA' has the bit pattern of a
-| 16-bit brain floating-point (BF16) signaling NaN.
-| Note:  This macro evaluates its argument more than once.
-*----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNBF16UI(uiA) ((((uiA)&0x7FC0) == 0x7F80) && ((uiA)&0x003F))
-
-/*----------------------------------------------------------------------------
-| Assuming 'uiA' has the bit pattern of a 16-bit BF16 floating-point NaN, converts
-| this NaN to the common NaN form, and stores the resulting common NaN at the
-| location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
-| exception is raised.
-*----------------------------------------------------------------------------*/
-void softfloat_bf16UIToCommonNaN(uint_fast16_t uiA, struct commonNaN* zPtr);
-
-/*----------------------------------------------------------------------------
-| Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point
-| NaN, and returns the bit pattern of this value as an unsigned integer.
-*----------------------------------------------------------------------------*/
-uint_fast16_t softfloat_commonNaNToBF16UI(const struct commonNaN* aPtr);
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 32-bit floating-point NaN.
@@ -169,7 +149,8 @@ uint_fast32_t softfloat_commonNaNToF32UI(const struct commonNaN* aPtr);
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
+uint_fast32_t
+ softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 64-bit floating-point NaN.
@@ -181,8 +162,7 @@ uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
 | 64-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF64UI(uiA)                                                                                                       \
+#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF )))
-    ((((uiA)&UINT64_C(0x7FF8000000000000)) == UINT64_C(0x7FF0000000000000)) && ((uiA)&UINT64_C(0x0007FFFFFFFFFFFF)))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts
@@ -204,7 +184,8 @@ uint_fast64_t softfloat_commonNaNToF64UI(const struct commonNaN* aPtr);
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
+uint_fast64_t
+ softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 80-bit extended floating-point NaN.
@@ -218,8 +199,7 @@ uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
 | floating-point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNExtF80UI(uiA64, uiA0)                                                                                            \
+#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF )))
-    ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF)))
 
 #ifdef SOFTFLOAT_FAST_INT64
 
@@ -235,7 +215,9 @@ uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_extF80UIToCommonNaN(uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
+void
+ softfloat_extF80UIToCommonNaN(
+     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
@@ -253,7 +235,13 @@ struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr);
 | result.  If either original floating-point value is a signaling NaN, the
 | invalid exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0);
+struct uint128
+ softfloat_propagateNaNExtF80UI(
+     uint_fast16_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast16_t uiB64,
+     uint_fast64_t uiB0
+ );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -267,8 +255,7 @@ struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t
 | point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF128UI(uiA64, uiA0)                                                                                              \
+#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF ))))
-    ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF))))
 
 /*----------------------------------------------------------------------------
 | Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
@@ -277,7 +264,9 @@ struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t
 | pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid exception
 | is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_f128UIToCommonNaN(uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
+void
+ softfloat_f128UIToCommonNaN(
+     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -294,7 +283,13 @@ struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN*);
 | If either original floating-point value is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0);
+struct uint128
+ softfloat_propagateNaNF128UI(
+     uint_fast64_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast64_t uiB64,
+     uint_fast64_t uiB0
+ );
 
 #else
 
@@ -309,14 +304,18 @@ struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t u
 | common NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling
 | NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_extF80MToCommonNaN(const struct extFloat80M* aSPtr, struct commonNaN* zPtr);
+void
+ softfloat_extF80MToCommonNaN(
+     const struct extFloat80M *aSPtr, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
 | floating-point NaN, and stores this NaN at the location pointed to by
 | 'zSPtr'.
 *----------------------------------------------------------------------------*/
-void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr);
+void
+ softfloat_commonNaNToExtF80M(
+     const struct commonNaN *aPtr, struct extFloat80M *zSPtr );
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 80-bit extended floating-point values
@@ -324,7 +323,12 @@ void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat8
 | at the location pointed to by 'zSPtr'.  If either original floating-point
 | value is a signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr);
+void
+ softfloat_propagateNaNExtF80M(
+     const struct extFloat80M *aSPtr,
+     const struct extFloat80M *bSPtr,
+     struct extFloat80M *zSPtr
+ );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -342,7 +346,8 @@ void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct
 | four 32-bit elements that concatenate in the platform's normal endian order
 | to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void softfloat_f128MToCommonNaN(const uint32_t* aWPtr, struct commonNaN* zPtr);
+void
+ softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -350,7 +355,8 @@ void softfloat_f128MToCommonNaN(const uint32_t* aWPtr, struct commonNaN* zPtr);
 | 'zWPtr' points to an array of four 32-bit elements that concatenate in the
 | platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
+void
+ softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr );
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 128-bit floating-point values pointed to by
@@ -360,8 +366,11 @@ void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
 | and 'zWPtr' points to an array of four 32-bit elements that concatenate in
 | the platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr);
+void
+ softfloat_propagateNaNF128M(
+     const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr );
 
 #endif
 
 #endif
+

softfloat/source/8086/specialize.h

@@ -37,10 +37,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifndef specialize_h
 #define specialize_h 1
 
-#include "primitiveTypes.h"
-#include "softfloat.h"
 #include <stdbool.h>
 #include <stdint.h>
+#include "primitiveTypes.h"
+#include "softfloat.h"
 
 /*----------------------------------------------------------------------------
 | Default value for 'softfloat_detectTininess'.
@@ -114,7 +114,8 @@ uint_fast16_t softfloat_commonNaNToF16UI(const struct commonNaN* aPtr);
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB);
+uint_fast16_t
+ softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 32-bit floating-point NaN.
@@ -148,7 +149,8 @@ uint_fast32_t softfloat_commonNaNToF32UI(const struct commonNaN* aPtr);
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
+uint_fast32_t
+ softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 64-bit floating-point NaN.
@@ -160,8 +162,7 @@ uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
 | 64-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF64UI(uiA)                                                                                                       \
+#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF )))
-    ((((uiA)&UINT64_C(0x7FF8000000000000)) == UINT64_C(0x7FF0000000000000)) && ((uiA)&UINT64_C(0x0007FFFFFFFFFFFF)))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts
@@ -183,7 +184,8 @@ uint_fast64_t softfloat_commonNaNToF64UI(const struct commonNaN* aPtr);
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
+uint_fast64_t
+ softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 80-bit extended floating-point NaN.
@@ -197,8 +199,7 @@ uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
 | floating-point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNExtF80UI(uiA64, uiA0)                                                                                            \
+#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF )))
-    ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF)))
 
 #ifdef SOFTFLOAT_FAST_INT64
 
@@ -214,7 +215,9 @@ uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_extF80UIToCommonNaN(uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
+void
+ softfloat_extF80UIToCommonNaN(
+     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
@@ -232,7 +235,13 @@ struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr);
 | result.  If either original floating-point value is a signaling NaN, the
 | invalid exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0);
+struct uint128
+ softfloat_propagateNaNExtF80UI(
+     uint_fast16_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast16_t uiB64,
+     uint_fast64_t uiB0
+ );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -246,8 +255,7 @@ struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t
 | point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF128UI(uiA64, uiA0)                                                                                              \
+#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF ))))
-    ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF))))
 
 /*----------------------------------------------------------------------------
 | Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
@@ -256,7 +264,9 @@ struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t
 | pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid exception
 | is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_f128UIToCommonNaN(uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
+void
+ softfloat_f128UIToCommonNaN(
+     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -273,7 +283,13 @@ struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN*);
 | If either original floating-point value is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0);
+struct uint128
+ softfloat_propagateNaNF128UI(
+     uint_fast64_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast64_t uiB64,
+     uint_fast64_t uiB0
+ );
 
 #else
 
@@ -288,14 +304,18 @@ struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t u
 | common NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling
 | NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_extF80MToCommonNaN(const struct extFloat80M* aSPtr, struct commonNaN* zPtr);
+void
+ softfloat_extF80MToCommonNaN(
+     const struct extFloat80M *aSPtr, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
 | floating-point NaN, and stores this NaN at the location pointed to by
 | 'zSPtr'.
 *----------------------------------------------------------------------------*/
-void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr);
+void
+ softfloat_commonNaNToExtF80M(
+     const struct commonNaN *aPtr, struct extFloat80M *zSPtr );
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 80-bit extended floating-point values
@@ -303,7 +323,12 @@ void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat8
 | at the location pointed to by 'zSPtr'.  If either original floating-point
 | value is a signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr);
+void
+ softfloat_propagateNaNExtF80M(
+     const struct extFloat80M *aSPtr,
+     const struct extFloat80M *bSPtr,
+     struct extFloat80M *zSPtr
+ );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -321,7 +346,8 @@ void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct
 | four 32-bit elements that concatenate in the platform's normal endian order
 | to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void softfloat_f128MToCommonNaN(const uint32_t* aWPtr, struct commonNaN* zPtr);
+void
+ softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -329,7 +355,8 @@ void softfloat_f128MToCommonNaN(const uint32_t* aWPtr, struct commonNaN* zPtr);
 | 'zWPtr' points to an array of four 32-bit elements that concatenate in the
 | platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
+void
+ softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr );
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 128-bit floating-point values pointed to by
@@ -339,8 +366,11 @@ void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
 | and 'zWPtr' points to an array of four 32-bit elements that concatenate in
 | the platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr);
+void
+ softfloat_propagateNaNF128M(
+     const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr );
 
 #endif
 
 #endif
+

softfloat/source/ARM-VFPv2-defaultNaN/specialize.h

@@ -37,10 +37,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifndef specialize_h
 #define specialize_h 1
 
-#include "primitiveTypes.h"
-#include "softfloat.h"
 #include <stdbool.h>
 #include <stdint.h>
+#include "primitiveTypes.h"
+#include "softfloat.h"
 
 /*----------------------------------------------------------------------------
 | Default value for 'softfloat_detectTininess'.
@@ -73,9 +73,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | "Common NaN" structure, used to transfer NaN representations from one format
 | to another.
 *----------------------------------------------------------------------------*/
-struct commonNaN {
+struct commonNaN { char _unused; };
-    char _unused;
-};
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 16-bit floating-point NaN.
@@ -95,9 +93,7 @@ struct commonNaN {
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_f16UIToCommonNaN(uiA, zPtr)                                                                                              \
+#define softfloat_f16UIToCommonNaN( uiA, zPtr ) if ( ! ((uiA) & 0x0200) ) softfloat_raiseFlags( softfloat_flag_invalid )
-    if(!((uiA)&0x0200))                                                                                                                    \
-    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point
@@ -111,7 +107,8 @@ struct commonNaN {
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB);
+uint_fast16_t
+ softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 32-bit floating-point NaN.
@@ -131,9 +128,7 @@ uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB);
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_f32UIToCommonNaN(uiA, zPtr)                                                                                              \
+#define softfloat_f32UIToCommonNaN( uiA, zPtr ) if ( ! ((uiA) & 0x00400000) ) softfloat_raiseFlags( softfloat_flag_invalid )
-    if(!((uiA)&0x00400000))                                                                                                                \
-    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point
@@ -147,7 +142,8 @@ uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB);
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
+uint_fast32_t
+ softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 64-bit floating-point NaN.
@@ -159,8 +155,7 @@ uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
 | 64-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF64UI(uiA)                                                                                                       \
+#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF )))
-    ((((uiA)&UINT64_C(0x7FF8000000000000)) == UINT64_C(0x7FF0000000000000)) && ((uiA)&UINT64_C(0x0007FFFFFFFFFFFF)))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts
@@ -168,9 +163,7 @@ uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_f64UIToCommonNaN(uiA, zPtr)                                                                                              \
+#define softfloat_f64UIToCommonNaN( uiA, zPtr ) if ( ! ((uiA) & UINT64_C( 0x0008000000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
-    if(!((uiA)&UINT64_C(0x0008000000000000)))                                                                                              \
-    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point
@@ -184,7 +177,8 @@ uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
+uint_fast64_t
+ softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 80-bit extended floating-point NaN.
@@ -198,8 +192,7 @@ uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
 | floating-point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNExtF80UI(uiA64, uiA0)                                                                                            \
+#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF )))
-    ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF)))
 
 #ifdef SOFTFLOAT_FAST_INT64
 
@@ -215,9 +208,7 @@ uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_extF80UIToCommonNaN(uiA64, uiA0, zPtr)                                                                                   \
+#define softfloat_extF80UIToCommonNaN( uiA64, uiA0, zPtr ) if ( ! ((uiA0) & UINT64_C( 0x4000000000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
-    if(!((uiA0)&UINT64_C(0x4000000000000000)))                                                                                             \
-    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
@@ -226,7 +217,8 @@ uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
 *----------------------------------------------------------------------------*/
 #if defined INLINE && ! defined softfloat_commonNaNToExtF80UI
 INLINE
-struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr) {
+struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr )
+{
     struct uint128 uiZ;
     uiZ.v64 = defaultNaNExtF80UI64;
     uiZ.v0  = defaultNaNExtF80UI0;
@@ -245,7 +237,13 @@ struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr);
 | result.  If either original floating-point value is a signaling NaN, the
 | invalid exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0);
+struct uint128
+ softfloat_propagateNaNExtF80UI(
+     uint_fast16_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast16_t uiB64,
+     uint_fast64_t uiB0
+ );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -259,8 +257,7 @@ struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t
 | point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF128UI(uiA64, uiA0)                                                                                              \
+#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF ))))
-    ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF))))
 
 /*----------------------------------------------------------------------------
 | Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
@@ -269,9 +266,7 @@ struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t
 | pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid exception
 | is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_f128UIToCommonNaN(uiA64, uiA0, zPtr)                                                                                     \
+#define softfloat_f128UIToCommonNaN( uiA64, uiA0, zPtr ) if ( ! ((uiA64) & UINT64_C( 0x0000800000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
-    if(!((uiA64)&UINT64_C(0x0000800000000000)))                                                                                            \
-    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -279,7 +274,8 @@ struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t
 *----------------------------------------------------------------------------*/
 #if defined INLINE && ! defined softfloat_commonNaNToF128UI
 INLINE
-struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN* aPtr) {
+struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN *aPtr )
+{
     struct uint128 uiZ;
     uiZ.v64 = defaultNaNF128UI64;
     uiZ.v0  = defaultNaNF128UI0;
@@ -298,7 +294,13 @@ struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN*);
 | If either original floating-point value is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0);
+struct uint128
+ softfloat_propagateNaNF128UI(
+     uint_fast64_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast64_t uiB64,
+     uint_fast64_t uiB0
+ );
 
 #else
 
@@ -313,9 +315,7 @@ struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t u
 | common NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling
 | NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_extF80MToCommonNaN(aSPtr, zPtr)                                                                                          \
+#define softfloat_extF80MToCommonNaN( aSPtr, zPtr ) if ( ! ((aSPtr)->signif & UINT64_C( 0x4000000000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
-    if(!((aSPtr)->signif & UINT64_C(0x4000000000000000)))                                                                                  \
-    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
@@ -324,12 +324,17 @@ struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t u
 *----------------------------------------------------------------------------*/
 #if defined INLINE && ! defined softfloat_commonNaNToExtF80M
 INLINE
-void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr) {
+void
+ softfloat_commonNaNToExtF80M(
+     const struct commonNaN *aPtr, struct extFloat80M *zSPtr )
+{
     zSPtr->signExp = defaultNaNExtF80UI64;
     zSPtr->signif  = defaultNaNExtF80UI0;
 }
 #else
-void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr);
+void
+ softfloat_commonNaNToExtF80M(
+     const struct commonNaN *aPtr, struct extFloat80M *zSPtr );
 #endif
 
 /*----------------------------------------------------------------------------
@@ -338,7 +343,12 @@ void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat8
 | at the location pointed to by 'zSPtr'.  If either original floating-point
 | value is a signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr);
+void
+ softfloat_propagateNaNExtF80M(
+     const struct extFloat80M *aSPtr,
+     const struct extFloat80M *bSPtr,
+     struct extFloat80M *zSPtr
+ );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -356,9 +366,7 @@ void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct
 | four 32-bit elements that concatenate in the platform's normal endian order
 | to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-#define softfloat_f128MToCommonNaN(aWPtr, zPtr)                                                                                            \
+#define softfloat_f128MToCommonNaN( aWPtr, zPtr ) if ( ! ((aWPtr)[indexWordHi( 4 )] & UINT64_C( 0x0000800000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
-    if(!((aWPtr)[indexWordHi(4)] & UINT64_C(0x0000800000000000)))                                                                          \
-    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -368,14 +376,17 @@ void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct
 *----------------------------------------------------------------------------*/
 #if defined INLINE && ! defined softfloat_commonNaNToF128M
 INLINE
-void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr) {
+void
+ softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr )
+{
     zWPtr[indexWord( 4, 3 )] = defaultNaNF128UI96;
     zWPtr[indexWord( 4, 2 )] = defaultNaNF128UI64;
     zWPtr[indexWord( 4, 1 )] = defaultNaNF128UI32;
     zWPtr[indexWord( 4, 0 )] = defaultNaNF128UI0;
 }
 #else
-void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
+void
+ softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr );
 #endif
 
 /*----------------------------------------------------------------------------
@@ -386,8 +397,11 @@ void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
 | and 'zWPtr' points to an array of four 32-bit elements that concatenate in
 | the platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr);
+void
+ softfloat_propagateNaNF128M(
+     const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr );
 
 #endif
 
 #endif
+

softfloat/source/ARM-VFPv2/specialize.h

@@ -37,10 +37,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifndef specialize_h
 #define specialize_h 1
 
-#include "primitiveTypes.h"
-#include "softfloat.h"
 #include <stdbool.h>
 #include <stdint.h>
+#include "primitiveTypes.h"
+#include "softfloat.h"
 
 /*----------------------------------------------------------------------------
 | Default value for 'softfloat_detectTininess'.
@@ -114,7 +114,8 @@ uint_fast16_t softfloat_commonNaNToF16UI(const struct commonNaN* aPtr);
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB);
+uint_fast16_t
+ softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 32-bit floating-point NaN.
@@ -148,7 +149,8 @@ uint_fast32_t softfloat_commonNaNToF32UI(const struct commonNaN* aPtr);
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
+uint_fast32_t
+ softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 64-bit floating-point NaN.
@@ -160,8 +162,7 @@ uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
 | 64-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF64UI(uiA)                                                                                                       \
+#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF )))
-    ((((uiA)&UINT64_C(0x7FF8000000000000)) == UINT64_C(0x7FF0000000000000)) && ((uiA)&UINT64_C(0x0007FFFFFFFFFFFF)))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts
@@ -183,7 +184,8 @@ uint_fast64_t softfloat_commonNaNToF64UI(const struct commonNaN* aPtr);
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
+uint_fast64_t
+ softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 80-bit extended floating-point NaN.
@@ -197,8 +199,7 @@ uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
 | floating-point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNExtF80UI(uiA64, uiA0)                                                                                            \
+#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF )))
-    ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF)))
 
 #ifdef SOFTFLOAT_FAST_INT64
 
@@ -214,7 +215,9 @@ uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_extF80UIToCommonNaN(uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
+void
+ softfloat_extF80UIToCommonNaN(
+     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
@@ -232,7 +235,13 @@ struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr);
 | result.  If either original floating-point value is a signaling NaN, the
 | invalid exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0);
+struct uint128
+ softfloat_propagateNaNExtF80UI(
+     uint_fast16_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast16_t uiB64,
+     uint_fast64_t uiB0
+ );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -246,8 +255,7 @@ struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t
 | point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF128UI(uiA64, uiA0)                                                                                              \
+#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF ))))
-    ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF))))
 
 /*----------------------------------------------------------------------------
 | Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
@@ -256,7 +264,9 @@ struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t
 | pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid exception
 | is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_f128UIToCommonNaN(uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
+void
+ softfloat_f128UIToCommonNaN(
+     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -273,7 +283,13 @@ struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN*);
 | If either original floating-point value is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0);
+struct uint128
+ softfloat_propagateNaNF128UI(
+     uint_fast64_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast64_t uiB64,
+     uint_fast64_t uiB0
+ );
 
 #else
 
@@ -288,14 +304,18 @@ struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t u
 | common NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling
 | NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_extF80MToCommonNaN(const struct extFloat80M* aSPtr, struct commonNaN* zPtr);
+void
+ softfloat_extF80MToCommonNaN(
+     const struct extFloat80M *aSPtr, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
 | floating-point NaN, and stores this NaN at the location pointed to by
 | 'zSPtr'.
 *----------------------------------------------------------------------------*/
-void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr);
+void
+ softfloat_commonNaNToExtF80M(
+     const struct commonNaN *aPtr, struct extFloat80M *zSPtr );
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 80-bit extended floating-point values
@@ -303,7 +323,12 @@ void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat8
 | at the location pointed to by 'zSPtr'.  If either original floating-point
 | value is a signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr);
+void
+ softfloat_propagateNaNExtF80M(
+     const struct extFloat80M *aSPtr,
+     const struct extFloat80M *bSPtr,
+     struct extFloat80M *zSPtr
+ );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -321,7 +346,8 @@ void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct
 | four 32-bit elements that concatenate in the platform's normal endian order
 | to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void softfloat_f128MToCommonNaN(const uint32_t* aWPtr, struct commonNaN* zPtr);
+void
+ softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -329,7 +355,8 @@ void softfloat_f128MToCommonNaN(const uint32_t* aWPtr, struct commonNaN* zPtr);
 | 'zWPtr' points to an array of four 32-bit elements that concatenate in the
 | platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
+void
+ softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr );
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 128-bit floating-point values pointed to by
@@ -339,8 +366,11 @@ void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
 | and 'zWPtr' points to an array of four 32-bit elements that concatenate in
 | the platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr);
+void
+ softfloat_propagateNaNF128M(
+     const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr );
 
 #endif
 
 #endif
+

softfloat/source/RISCV/s_bf16UIToCommonNaN.c

@@ -1,5 +0,0 @@
-
-/*----------------------------------------------------------------------------
-| This file intentionally contains no code.
-*----------------------------------------------------------------------------*/
-

softfloat/source/RISCV/s_commonNaNToBF16UI.c

@@ -1,5 +0,0 @@
-
-/*----------------------------------------------------------------------------
-| This file intentionally contains no code.
-*----------------------------------------------------------------------------*/
-

softfloat/source/RISCV/s_commonNaNToExtF80M.c

@@ -4,8 +4,8 @@
 This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
 Package, Release 3e, by John R. Hauser.
 
-Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-California.  All rights reserved.
+All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -34,10 +34,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 =============================================================================*/
 
+#include <stdint.h>
 #include "platform.h"
-#include "softfloat_types.h"
+#include "internals.h"
-
-#define softfloat_commonNaNToExtF80M softfloat_commonNaNToExtF80M
 #include "specialize.h"
 
 /*----------------------------------------------------------------------------
@@ -50,8 +49,8 @@ void
      const struct commonNaN *aPtr, struct extFloat80M *zSPtr )
 {
 
-    zSPtr->signExp = defaultNaNExtF80UI64;
+    zSPtr->signExp = packToExtF80UI64( aPtr->sign, 0x7FFF );
-    zSPtr->signif  = defaultNaNExtF80UI0;
+    zSPtr->signif = UINT64_C( 0xC000000000000000 ) | aPtr->v64>>1;
 
 }
 

softfloat/source/RISCV/s_commonNaNToExtF80UI.c

@@ -4,8 +4,8 @@
 This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
 Package, Release 3e, by John R. Hauser.
 
-Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-California.  All rights reserved.
+All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -34,10 +34,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 =============================================================================*/
 
+#include <stdint.h>
 #include "platform.h"
-#include "primitiveTypes.h"
+#include "primitives.h"
-
-#define softfloat_commonNaNToExtF80UI softfloat_commonNaNToExtF80UI
 #include "specialize.h"
 
 /*----------------------------------------------------------------------------
@@ -49,8 +48,8 @@ struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr )
 {
     struct uint128 uiZ;
 
-    uiZ.v64 = defaultNaNExtF80UI64;
+    uiZ.v64 = (uint_fast16_t) aPtr->sign<<15 | 0x7FFF;
-    uiZ.v0  = defaultNaNExtF80UI0;
+    uiZ.v0 = UINT64_C( 0xC000000000000000 ) | aPtr->v64>>1;
     return uiZ;
 
 }

softfloat/source/RISCV/s_commonNaNToF128M.c

@@ -4,8 +4,8 @@
 This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
 Package, Release 3e, by John R. Hauser.
 
-Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-California.  All rights reserved.
+All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -36,9 +36,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 #include <stdint.h>
 #include "platform.h"
-#include "primitiveTypes.h"
+#include "primitives.h"
-
-#define softfloat_commonNaNToF128M softfloat_commonNaNToF128M
 #include "specialize.h"
 
 /*----------------------------------------------------------------------------
@@ -51,10 +49,8 @@ void
  softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr )
 {
 
-    zWPtr[indexWord( 4, 3 )] = defaultNaNF128UI96;
+    softfloat_shortShiftRight128M( (const uint32_t *) &aPtr->v0, 16, zWPtr );
-    zWPtr[indexWord( 4, 2 )] = defaultNaNF128UI64;
+    zWPtr[indexWordHi( 4 )] |= (uint32_t) aPtr->sign<<31 | 0x7FFF8000;
-    zWPtr[indexWord( 4, 1 )] = defaultNaNF128UI32;
-    zWPtr[indexWord( 4, 0 )] = defaultNaNF128UI0;
 
 }
 

softfloat/source/RISCV/s_commonNaNToF128UI.c

@@ -4,8 +4,8 @@
 This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
 Package, Release 3e, by John R. Hauser.
 
-Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-California.  All rights reserved.
+All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -34,10 +34,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 =============================================================================*/
 
+#include <stdint.h>
 #include "platform.h"
-#include "primitiveTypes.h"
+#include "primitives.h"
-
-#define softfloat_commonNaNToF128UI softfloat_commonNaNToF128UI
 #include "specialize.h"
 
 /*----------------------------------------------------------------------------
@@ -48,8 +47,8 @@ struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN *aPtr )
 {
     struct uint128 uiZ;
 
-    uiZ.v64 = defaultNaNF128UI64;
+    uiZ = softfloat_shortShiftRight128( aPtr->v64, aPtr->v0, 16 );
-    uiZ.v0  = defaultNaNF128UI0;
+    uiZ.v64 |= (uint_fast64_t) aPtr->sign<<63 | UINT64_C( 0x7FFF800000000000 );
     return uiZ;
 
 }

softfloat/source/RISCV/s_commonNaNToF16UI.c

@@ -1,5 +1,51 @@
 
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+
 /*----------------------------------------------------------------------------
-| This file intentionally contains no code.
+| Converts the common NaN pointed to by `aPtr' into a 16-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
+uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr )
+{
+
+    return (uint_fast16_t) aPtr->sign<<15 | 0x7E00 | aPtr->v64>>54;
+
+}
 

softfloat/source/RISCV/s_commonNaNToF32UI.c

@@ -1,5 +1,51 @@
 
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+
 /*----------------------------------------------------------------------------
-| This file intentionally contains no code.
+| Converts the common NaN pointed to by `aPtr' into a 32-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
+uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr )
+{
+
+    return (uint_fast32_t) aPtr->sign<<31 | 0x7FC00000 | aPtr->v64>>41;
+
+}
 

softfloat/source/RISCV/s_commonNaNToF64UI.c

@@ -1,5 +1,53 @@
 
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+
 /*----------------------------------------------------------------------------
-| This file intentionally contains no code.
+| Converts the common NaN pointed to by `aPtr' into a 64-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
+uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr )
+{
+
+    return
+        (uint_fast64_t) aPtr->sign<<63 | UINT64_C( 0x7FF8000000000000 )
+            | aPtr->v64>>12;
+
+}
 

softfloat/source/RISCV/s_extF80MToCommonNaN.c

@@ -1,5 +1,62 @@
 
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
 /*----------------------------------------------------------------------------
-| This file intentionally contains no code.
+| Assuming the 80-bit extended floating-point value pointed to by `aSPtr' is
+| a NaN, converts this NaN to the common NaN form, and stores the resulting
+| common NaN at the location pointed to by `zPtr'.  If the NaN is a signaling
+| NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
+void
+ softfloat_extF80MToCommonNaN(
+     const struct extFloat80M *aSPtr, struct commonNaN *zPtr )
+{
+
+    if ( extF80M_isSignalingNaN( (const extFloat80_t *) aSPtr ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    zPtr->sign = signExtF80UI64( aSPtr->signExp );
+    zPtr->v64 = aSPtr->signif<<1;
+    zPtr->v0  = 0;
+
+}
 

softfloat/source/RISCV/s_extF80UIToCommonNaN.c

@@ -1,5 +1,62 @@
 
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+#include "softfloat.h"
+
 /*----------------------------------------------------------------------------
-| This file intentionally contains no code.
+| Assuming the unsigned integer formed from concatenating `uiA64' and `uiA0'
+| has the bit pattern of an 80-bit extended floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
 *----------------------------------------------------------------------------*/
+void
+ softfloat_extF80UIToCommonNaN(
+     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr )
+{
+
+    if ( softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    zPtr->sign = uiA64>>15;
+    zPtr->v64  = uiA0<<1;
+    zPtr->v0   = 0;
+
+}
 

softfloat/source/RISCV/s_f128MToCommonNaN.c

@@ -1,5 +1,62 @@
 
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "specialize.h"
+#include "softfloat.h"
+
 /*----------------------------------------------------------------------------
-| This file intentionally contains no code.
+| Assuming the 128-bit floating-point value pointed to by `aWPtr' is a NaN,
+| converts this NaN to the common NaN form, and stores the resulting common
+| NaN at the location pointed to by `zPtr'.  If the NaN is a signaling NaN,
+| the invalid exception is raised.  Argument `aWPtr' points to an array of
+| four 32-bit elements that concatenate in the platform's normal endian order
+| to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
+void
+ softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr )
+{
+
+    if ( f128M_isSignalingNaN( (const float128_t *) aWPtr ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    zPtr->sign = aWPtr[indexWordHi( 4 )]>>31;
+    softfloat_shortShiftLeft128M( aWPtr, 16, (uint32_t *) &zPtr->v0 );
+
+}
 

softfloat/source/RISCV/s_f128UIToCommonNaN.c

@@ -1,5 +1,65 @@
 
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "specialize.h"
+#include "softfloat.h"
+
 /*----------------------------------------------------------------------------
-| This file intentionally contains no code.
+| Assuming the unsigned integer formed from concatenating `uiA64' and `uiA0'
+| has the bit pattern of a 128-bit floating-point NaN, converts this NaN to
+| the common NaN form, and stores the resulting common NaN at the location
+| pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid exception
+| is raised.
 *----------------------------------------------------------------------------*/
+void
+ softfloat_f128UIToCommonNaN(
+     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr )
+{
+    struct uint128 NaNSig;
+
+    if ( softfloat_isSigNaNF128UI( uiA64, uiA0 ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    NaNSig = softfloat_shortShiftLeft128( uiA64, uiA0, 16 );
+    zPtr->sign = uiA64>>63;
+    zPtr->v64  = NaNSig.v64;
+    zPtr->v0   = NaNSig.v0;
+
+}
 

softfloat/source/RISCV/s_f16UIToCommonNaN.c

@@ -1,5 +1,59 @@
 
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+#include "softfloat.h"
+
 /*----------------------------------------------------------------------------
-| This file intentionally contains no code.
+| Assuming `uiA' has the bit pattern of a 16-bit floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
 *----------------------------------------------------------------------------*/
+void softfloat_f16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr )
+{
+
+    if ( softfloat_isSigNaNF16UI( uiA ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    zPtr->sign = uiA>>15;
+    zPtr->v64  = (uint_fast64_t) uiA<<54;
+    zPtr->v0   = 0;
+
+}
 

softfloat/source/RISCV/s_f32UIToCommonNaN.c

@@ -1,5 +1,59 @@
 
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+#include "softfloat.h"
+
 /*----------------------------------------------------------------------------
-| This file intentionally contains no code.
+| Assuming `uiA' has the bit pattern of a 32-bit floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
 *----------------------------------------------------------------------------*/
+void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr )
+{
+
+    if ( softfloat_isSigNaNF32UI( uiA ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    zPtr->sign = uiA>>31;
+    zPtr->v64  = (uint_fast64_t) uiA<<41;
+    zPtr->v0   = 0;
+
+}
 

softfloat/source/RISCV/s_f64UIToCommonNaN.c

@@ -1,5 +1,59 @@
 
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+#include "softfloat.h"
+
 /*----------------------------------------------------------------------------
-| This file intentionally contains no code.
+| Assuming `uiA' has the bit pattern of a 64-bit floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
 *----------------------------------------------------------------------------*/
+void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr )
+{
+
+    if ( softfloat_isSigNaNF64UI( uiA ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    zPtr->sign = uiA>>63;
+    zPtr->v64  = uiA<<12;
+    zPtr->v0   = 0;
+
+}
 

softfloat/source/RISCV/s_propagateNaNExtF80M.c

@@ -4,8 +4,8 @@
 This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
 Package, Release 3e, by John R. Hauser.
 
-Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-California.  All rights reserved.
+All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -34,9 +34,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 =============================================================================*/
 
+#include <stdbool.h>
 #include <stdint.h>
 #include "platform.h"
-#include "primitiveTypes.h"
+#include "internals.h"
 #include "specialize.h"
 #include "softfloat.h"
 
@@ -53,22 +54,54 @@ void
      struct extFloat80M *zSPtr
  )
 {
-    uint_fast16_t ui64;
+    bool isSigNaNA;
-    uint_fast64_t ui0;
+    const struct extFloat80M *sPtr;
+    bool isSigNaNB;
+    uint_fast16_t uiB64;
+    uint64_t uiB0;
+    uint_fast16_t uiA64;
+    uint64_t uiA0;
+    uint_fast16_t uiMagA64, uiMagB64;
 
-    ui64 = aSPtr->signExp;
+    isSigNaNA = extF80M_isSignalingNaN( (const extFloat80_t *) aSPtr );
-    ui0  = aSPtr->signif;
+    sPtr = aSPtr;
-    if (
+    if ( ! bSPtr ) {
-        softfloat_isSigNaNExtF80UI( ui64, ui0 )
+        if ( isSigNaNA ) softfloat_raiseFlags( softfloat_flag_invalid );
-            || (bSPtr
+        goto copy;
-                    && (ui64 = bSPtr->signExp,
+    }
-                        ui0  = bSPtr->signif,
+    isSigNaNB = extF80M_isSignalingNaN( (const extFloat80_t *) bSPtr );
-                        softfloat_isSigNaNExtF80UI( ui64, ui0 )))
+    if ( isSigNaNA | isSigNaNB ) {
-    ) {
         softfloat_raiseFlags( softfloat_flag_invalid );
+        if ( isSigNaNA ) {
+            uiB64 = bSPtr->signExp;
+            if ( isSigNaNB ) goto returnLargerUIMag;
+            uiB0 = bSPtr->signif;
+            if ( isNaNExtF80UI( uiB64, uiB0 ) ) goto copyB;
+            goto copy;
+        } else {
+            uiA64 = aSPtr->signExp;
+            uiA0 = aSPtr->signif;
+            if ( isNaNExtF80UI( uiA64, uiA0 ) ) goto copy;
+            goto copyB;
         }
-    zSPtr->signExp = defaultNaNExtF80UI64;
+    }
-    zSPtr->signif  = defaultNaNExtF80UI0;
+    uiB64 = bSPtr->signExp;
+ returnLargerUIMag:
+    uiA64 = aSPtr->signExp;
+    uiMagA64 = uiA64 & 0x7FFF;
+    uiMagB64 = uiB64 & 0x7FFF;
+    if ( uiMagA64 < uiMagB64 ) goto copyB;
+    if ( uiMagB64 < uiMagA64 ) goto copy;
+    uiA0 = aSPtr->signif;
+    uiB0 = bSPtr->signif;
+    if ( uiA0 < uiB0 ) goto copyB;
+    if ( uiB0 < uiA0 ) goto copy;
+    if ( uiA64 < uiB64 ) goto copy;
+ copyB:
+    sPtr = bSPtr;
+ copy:
+    zSPtr->signExp = sPtr->signExp;
+    zSPtr->signif = sPtr->signif | UINT64_C( 0xC000000000000000 );
 
 }
 

softfloat/source/RISCV/s_propagateNaNExtF80UI.c

@@ -4,7 +4,7 @@
 This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
 Package, Release 3e, by John R. Hauser.
 
-Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
 California.  All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
@@ -34,16 +34,17 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 =============================================================================*/
 
+#include <stdbool.h>
 #include <stdint.h>
 #include "platform.h"
-#include "primitiveTypes.h"
+#include "internals.h"
 #include "specialize.h"
 #include "softfloat.h"
 
 /*----------------------------------------------------------------------------
-| Interpreting the unsigned integer formed from concatenating `uiA64' and
+| Interpreting the unsigned integer formed from concatenating 'uiA64' and
-| `uiA0' as an 80-bit extended floating-point value, and likewise interpreting
+| 'uiA0' as an 80-bit extended floating-point value, and likewise interpreting
-| the unsigned integer formed from concatenating `uiB64' and `uiB0' as another
+| the unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another
 | 80-bit extended floating-point value, and assuming at least on of these
 | floating-point values is a NaN, returns the bit pattern of the combined NaN
 | result.  If either original floating-point value is a signaling NaN, the
@@ -57,16 +58,48 @@ struct uint128
      uint_fast64_t uiB0
  )
 {
+    bool isSigNaNA, isSigNaNB;
+    uint_fast64_t uiNonsigA0, uiNonsigB0;
+    uint_fast16_t uiMagA64, uiMagB64;
     struct uint128 uiZ;
 
-    if (
+    /*------------------------------------------------------------------------
-           softfloat_isSigNaNExtF80UI( uiA64, uiA0 )
+    *------------------------------------------------------------------------*/
-        || softfloat_isSigNaNExtF80UI( uiB64, uiB0 )
+    isSigNaNA = softfloat_isSigNaNExtF80UI( uiA64, uiA0 );
-    ) {
+    isSigNaNB = softfloat_isSigNaNExtF80UI( uiB64, uiB0 );
+    /*------------------------------------------------------------------------
+    | Make NaNs non-signaling.
+    *------------------------------------------------------------------------*/
+    uiNonsigA0 = uiA0 | UINT64_C( 0xC000000000000000 );
+    uiNonsigB0 = uiB0 | UINT64_C( 0xC000000000000000 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( isSigNaNA | isSigNaNB ) {
         softfloat_raiseFlags( softfloat_flag_invalid );
+        if ( isSigNaNA ) {
+            if ( isSigNaNB ) goto returnLargerMag;
+            if ( isNaNExtF80UI( uiB64, uiB0 ) ) goto returnB;
+            goto returnA;
+        } else {
+            if ( isNaNExtF80UI( uiA64, uiA0 ) ) goto returnA;
+            goto returnB;
         }
-    uiZ.v64 = defaultNaNExtF80UI64;
+    }
-    uiZ.v0  = defaultNaNExtF80UI0;
+ returnLargerMag:
+    uiMagA64 = uiA64 & 0x7FFF;
+    uiMagB64 = uiB64 & 0x7FFF;
+    if ( uiMagA64 < uiMagB64 ) goto returnB;
+    if ( uiMagB64 < uiMagA64 ) goto returnA;
+    if ( uiA0 < uiB0 ) goto returnB;
+    if ( uiB0 < uiA0 ) goto returnA;
+    if ( uiA64 < uiB64 ) goto returnA;
+ returnB:
+    uiZ.v64 = uiB64;
+    uiZ.v0  = uiNonsigB0;
+    return uiZ;
+ returnA:
+    uiZ.v64 = uiA64;
+    uiZ.v0  = uiNonsigA0;
     return uiZ;
 
 }

softfloat/source/RISCV/s_propagateNaNF128M.c

@@ -4,8 +4,8 @@
 This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
 Package, Release 3e, by John R. Hauser.
 
-Copyright 2011, 2012, 2013, 2014, 2015, 2018 The Regents of the University of
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-California.  All rights reserved.
+All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -34,35 +34,43 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 =============================================================================*/
 
+#include <stdbool.h>
 #include <stdint.h>
 #include "platform.h"
-#include "primitiveTypes.h"
+#include "internals.h"
 #include "specialize.h"
 #include "softfloat.h"
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 128-bit floating-point values pointed to by
-| 'aWPtr' and 'bWPtr' is a NaN, stores the combined NaN result at the location
+| `aWPtr' and `bWPtr' is a NaN, stores the combined NaN result at the location
-| pointed to by 'zWPtr'.  If either original floating-point value is a
+| pointed to by `zWPtr'.  If either original floating-point value is a
-| signaling NaN, the invalid exception is raised.  Each of 'aWPtr', 'bWPtr',
+| signaling NaN, the invalid exception is raised.  Each of `aWPtr', `bWPtr',
-| and 'zWPtr' points to an array of four 32-bit elements that concatenate in
+| and `zWPtr' points to an array of four 32-bit elements that concatenate in
 | the platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
 void
  softfloat_propagateNaNF128M(
      const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr )
 {
+    bool isSigNaNA;
+    const uint32_t *ptr;
 
+    ptr = aWPtr;
+    isSigNaNA = f128M_isSignalingNaN( (const float128_t *) aWPtr );
     if (
-        f128M_isSignalingNaN( (const float128_t *) aWPtr )
+        isSigNaNA
             || (bWPtr && f128M_isSignalingNaN( (const float128_t *) bWPtr ))
     ) {
         softfloat_raiseFlags( softfloat_flag_invalid );
+        if ( isSigNaNA ) goto copy;
     }
-    zWPtr[indexWord( 4, 3 )] = defaultNaNF128UI96;
+    if ( ! softfloat_isNaNF128M( aWPtr ) ) ptr = bWPtr;
-    zWPtr[indexWord( 4, 2 )] = defaultNaNF128UI64;
+ copy:
-    zWPtr[indexWord( 4, 1 )] = defaultNaNF128UI32;
+    zWPtr[indexWordHi( 4 )] = ptr[indexWordHi( 4 )] | 0x00008000;
-    zWPtr[indexWord( 4, 0 )] = defaultNaNF128UI0;
+    zWPtr[indexWord( 4, 2 )] = ptr[indexWord( 4, 2 )];
+    zWPtr[indexWord( 4, 1 )] = ptr[indexWord( 4, 1 )];
+    zWPtr[indexWord( 4, 0 )] = ptr[indexWord( 4, 0 )];
 
 }
 

softfloat/source/RISCV/s_propagateNaNF128UI.c

@@ -4,8 +4,8 @@
 This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
 Package, Release 3e, by John R. Hauser.
 
-Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-California.  All rights reserved.
+All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -34,9 +34,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 =============================================================================*/
 
+#include <stdbool.h>
 #include <stdint.h>
 #include "platform.h"
-#include "primitiveTypes.h"
+#include "internals.h"
 #include "specialize.h"
 #include "softfloat.h"
 
@@ -57,16 +58,23 @@ struct uint128
      uint_fast64_t uiB0
  )
 {
+    bool isSigNaNA;
     struct uint128 uiZ;
 
-    if (
+    isSigNaNA = softfloat_isSigNaNF128UI( uiA64, uiA0 );
-           softfloat_isSigNaNF128UI( uiA64, uiA0 )
+    if ( isSigNaNA || softfloat_isSigNaNF128UI( uiB64, uiB0 ) ) {
-        || softfloat_isSigNaNF128UI( uiB64, uiB0 )
-    ) {
         softfloat_raiseFlags( softfloat_flag_invalid );
+        if ( isSigNaNA ) goto returnNonsigA;
     }
-    uiZ.v64 = defaultNaNF128UI64;
+    if ( isNaNF128UI( uiA64, uiA0 ) ) {
-    uiZ.v0  = defaultNaNF128UI0;
+ returnNonsigA:
+        uiZ.v64 = uiA64;
+        uiZ.v0  = uiA0;
+    } else {
+        uiZ.v64 = uiB64;
+        uiZ.v0  = uiB0;
+    }
+    uiZ.v64 |= UINT64_C( 0x0000800000000000 );
     return uiZ;
 
 }

softfloat/source/RISCV/s_propagateNaNF16UI.c

@@ -4,7 +4,7 @@
 This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
 Package, Release 3e, by John R. Hauser.
 
-Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
 California.  All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
@@ -34,8 +34,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 =============================================================================*/
 
+#include <stdbool.h>
 #include <stdint.h>
 #include "platform.h"
+#include "internals.h"
 #include "specialize.h"
 #include "softfloat.h"
 
@@ -48,11 +50,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 uint_fast16_t
  softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB )
 {
+    bool isSigNaNA;
 
-    if ( softfloat_isSigNaNF16UI( uiA ) || softfloat_isSigNaNF16UI( uiB ) ) {
+    isSigNaNA = softfloat_isSigNaNF16UI( uiA );
+    if ( isSigNaNA || softfloat_isSigNaNF16UI( uiB ) ) {
         softfloat_raiseFlags( softfloat_flag_invalid );
+        if ( isSigNaNA ) return uiA | 0x0200;
     }
-    return defaultNaNF16UI;
+    return (isNaNF16UI( uiA ) ? uiA : uiB) | 0x0200;
 
 }
 

softfloat/source/RISCV/s_propagateNaNF32UI.c

@@ -4,8 +4,8 @@
 This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
 Package, Release 3e, by John R. Hauser.
 
-Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-California.  All rights reserved.
+All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -34,8 +34,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 =============================================================================*/
 
+#include <stdbool.h>
 #include <stdint.h>
 #include "platform.h"
+#include "internals.h"
 #include "specialize.h"
 #include "softfloat.h"
 
@@ -48,11 +50,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 uint_fast32_t
  softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB )
 {
+    bool isSigNaNA;
 
-    if ( softfloat_isSigNaNF32UI( uiA ) || softfloat_isSigNaNF32UI( uiB ) ) {
+    isSigNaNA = softfloat_isSigNaNF32UI( uiA );
+    if ( isSigNaNA || softfloat_isSigNaNF32UI( uiB ) ) {
         softfloat_raiseFlags( softfloat_flag_invalid );
+        if ( isSigNaNA ) return uiA | 0x00400000;
     }
-    return defaultNaNF32UI;
+    return (isNaNF32UI( uiA ) ? uiA : uiB) | 0x00400000;
 
 }
 

softfloat/source/RISCV/s_propagateNaNF64UI.c

@@ -4,8 +4,8 @@
 This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
 Package, Release 3e, by John R. Hauser.
 
-Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-California.  All rights reserved.
+All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -34,8 +34,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 =============================================================================*/
 
+#include <stdbool.h>
 #include <stdint.h>
 #include "platform.h"
+#include "internals.h"
 #include "specialize.h"
 #include "softfloat.h"
 
@@ -48,11 +50,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 uint_fast64_t
  softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB )
 {
+    bool isSigNaNA;
 
-    if ( softfloat_isSigNaNF64UI( uiA ) || softfloat_isSigNaNF64UI( uiB ) ) {
+    isSigNaNA = softfloat_isSigNaNF64UI( uiA );
+    if ( isSigNaNA || softfloat_isSigNaNF64UI( uiB ) ) {
         softfloat_raiseFlags( softfloat_flag_invalid );
+        if ( isSigNaNA ) return uiA | UINT64_C( 0x0008000000000000 );
     }
-    return defaultNaNF64UI;
+    return (isNaNF64UI( uiA ) ? uiA : uiB) | UINT64_C( 0x0008000000000000 );
 
 }
 

softfloat/source/RISCV/specialize.h

@@ -37,10 +37,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifndef specialize_h
 #define specialize_h 1
 
-#include "primitiveTypes.h"
-#include "softfloat.h"
 #include <stdbool.h>
 #include <stdint.h>
+#include "primitiveTypes.h"
+#include "softfloat.h"
 
 /*----------------------------------------------------------------------------
 | Default value for 'softfloat_detectTininess'.
@@ -51,19 +51,19 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | The values to return on conversions to 32-bit integer formats that raise an
 | invalid exception.
 *----------------------------------------------------------------------------*/
-#define ui32_fromPosOverflow 0xFFFFFFFF
+#define ui32_fromPosOverflow UINT32_C(0xFFFFFFFF)
-#define ui32_fromNegOverflow 0
+#define ui32_fromNegOverflow UINT32_C(0x0)
-#define ui32_fromNaN 0xFFFFFFFF
+#define ui32_fromNaN         UINT32_C(0xFFFFFFFF)
-#define i32_fromPosOverflow 0x7FFFFFFF
+#define i32_fromPosOverflow   INT64_C(0x7FFFFFFF)
-#define i32_fromNegOverflow (-0x7FFFFFFF - 1)
+#define i32_fromNegOverflow  (-INT64_C(0x7FFFFFFF)-1)
-#define i32_fromNaN 0x7FFFFFFF
+#define i32_fromNaN           INT64_C(0x7FFFFFFF)
 
 /*----------------------------------------------------------------------------
 | The values to return on conversions to 64-bit integer formats that raise an
 | invalid exception.
 *----------------------------------------------------------------------------*/
 #define ui64_fromPosOverflow UINT64_C( 0xFFFFFFFFFFFFFFFF )
-#define ui64_fromNegOverflow 0
+#define ui64_fromNegOverflow UINT64_C( 0x0 )
 #define ui64_fromNaN         UINT64_C( 0xFFFFFFFFFFFFFFFF)
 #define i64_fromPosOverflow   INT64_C( 0x7FFFFFFFFFFFFFFF)
 #define i64_fromNegOverflow  (-INT64_C( 0x7FFFFFFFFFFFFFFF)-1)
@@ -74,13 +74,18 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | to another.
 *----------------------------------------------------------------------------*/
 struct commonNaN {
-    char _unused;
+    bool sign;
+#ifdef LITTLEENDIAN
+    uint64_t v0, v64;
+#else
+    uint64_t v64, v0;
+#endif
 };
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 16-bit floating-point NaN.
 *----------------------------------------------------------------------------*/
-#define defaultNaNF16UI 0x7E00
+#define defaultNaNF16UI 0xFE00
 
 /*----------------------------------------------------------------------------
 | Returns true when 16-bit unsigned integer 'uiA' has the bit pattern of a
@@ -89,38 +94,19 @@ struct commonNaN {
 *----------------------------------------------------------------------------*/
 #define softfloat_isSigNaNF16UI( uiA ) ((((uiA) & 0x7E00) == 0x7C00) && ((uiA) & 0x01FF))
 
-/*----------------------------------------------------------------------------
-| Returns true when 16-bit unsigned integer 'uiA' has the bit pattern of a
-| 16-bit brain floating-point (BF16) signaling NaN.
-| Note:  This macro evaluates its argument more than once.
-*----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNBF16UI(uiA) ((((uiA)&0x7FC0) == 0x7F80) && ((uiA)&0x003F))
-
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 16-bit floating-point NaN, converts
 | this NaN to the common NaN form, and stores the resulting common NaN at the
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_f16UIToCommonNaN(uiA, zPtr)                                                                                              \
+void softfloat_f16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr );
-    if(!((uiA)&0x0200))                                                                                                                    \
-    softfloat_raiseFlags(softfloat_flag_invalid)
-
-/*----------------------------------------------------------------------------
-| Assuming 'uiA' has the bit pattern of a 16-bit BF16 floating-point NaN, converts
-| this NaN to the common NaN form, and stores the resulting common NaN at the
-| location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
-| exception is raised.
-*----------------------------------------------------------------------------*/
-#define softfloat_bf16UIToCommonNaN(uiA, zPtr)                                                                                             \
-    if(!((uiA)&0x0040))                                                                                                                    \
-    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
-#define softfloat_commonNaNToF16UI(aPtr) ((uint_fast16_t)defaultNaNF16UI)
+uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr );
 
 /*----------------------------------------------------------------------------
 | Interpreting 'uiA' and 'uiB' as the bit patterns of two 16-bit floating-
@@ -128,18 +114,8 @@ struct commonNaN {
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB);
+uint_fast16_t
-
+ softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB );
-/*----------------------------------------------------------------------------
-| The bit pattern for a default generated 16-bit BF16 floating-point NaN.
-*----------------------------------------------------------------------------*/
-#define defaultNaNBF16UI 0x7FC0
-
-/*----------------------------------------------------------------------------
-| Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point
-| NaN, and returns the bit pattern of this value as an unsigned integer.
-*----------------------------------------------------------------------------*/
-#define softfloat_commonNaNToBF16UI(aPtr) ((uint_fast16_t)defaultNaNBF16UI)
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 32-bit floating-point NaN.
@@ -159,15 +135,13 @@ uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB);
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_f32UIToCommonNaN(uiA, zPtr)                                                                                              \
+void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr );
-    if(!((uiA)&0x00400000))                                                                                                                \
-    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
-#define softfloat_commonNaNToF32UI(aPtr) ((uint_fast32_t)defaultNaNF32UI)
+uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr );
 
 /*----------------------------------------------------------------------------
 | Interpreting 'uiA' and 'uiB' as the bit patterns of two 32-bit floating-
@@ -175,7 +149,8 @@ uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB);
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
+uint_fast32_t
+ softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 64-bit floating-point NaN.
@@ -187,8 +162,7 @@ uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
 | 64-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF64UI(uiA)                                                                                                       \
+#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF )))
-    ((((uiA)&UINT64_C(0x7FF8000000000000)) == UINT64_C(0x7FF0000000000000)) && ((uiA)&UINT64_C(0x0007FFFFFFFFFFFF)))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts
@@ -196,15 +170,13 @@ uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_f64UIToCommonNaN(uiA, zPtr)                                                                                              \
+void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr );
-    if(!((uiA)&UINT64_C(0x0008000000000000)))                                                                                              \
-    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
-#define softfloat_commonNaNToF64UI(aPtr) ((uint_fast64_t)defaultNaNF64UI)
+uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr );
 
 /*----------------------------------------------------------------------------
 | Interpreting 'uiA' and 'uiB' as the bit patterns of two 64-bit floating-
@@ -212,12 +184,13 @@ uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
+uint_fast64_t
+ softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 80-bit extended floating-point NaN.
 *----------------------------------------------------------------------------*/
-#define defaultNaNExtF80UI64 0x7FFF
+#define defaultNaNExtF80UI64 0xFFFF
 #define defaultNaNExtF80UI0  UINT64_C( 0xC000000000000000 )
 
 /*----------------------------------------------------------------------------
@@ -226,8 +199,7 @@ uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
 | floating-point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNExtF80UI(uiA64, uiA0)                                                                                            \
+#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF )))
-    ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF)))
 
 #ifdef SOFTFLOAT_FAST_INT64
 
@@ -243,26 +215,16 @@ uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_extF80UIToCommonNaN(uiA64, uiA0, zPtr)                                                                                   \
+void
-    if(!((uiA0)&UINT64_C(0x4000000000000000)))                                                                                             \
+ softfloat_extF80UIToCommonNaN(
-    softfloat_raiseFlags(softfloat_flag_invalid)
+     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
 | floating-point NaN, and returns the bit pattern of this value as an unsigned
 | integer.
 *----------------------------------------------------------------------------*/
-#if defined INLINE && !defined softfloat_commonNaNToExtF80UI
-INLINE
-struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr) {
-    struct uint128 uiZ;
-    uiZ.v64 = defaultNaNExtF80UI64;
-    uiZ.v0 = defaultNaNExtF80UI0;
-    return uiZ;
-}
-#else
 struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr );
-#endif
 
 /*----------------------------------------------------------------------------
 | Interpreting the unsigned integer formed from concatenating 'uiA64' and
@@ -273,12 +235,18 @@ struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr);
 | result.  If either original floating-point value is a signaling NaN, the
 | invalid exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0);
+struct uint128
+ softfloat_propagateNaNExtF80UI(
+     uint_fast16_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast16_t uiB64,
+     uint_fast64_t uiB0
+ );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
 *----------------------------------------------------------------------------*/
-#define defaultNaNF128UI64 UINT64_C(0x7FFF800000000000)
+#define defaultNaNF128UI64 UINT64_C( 0xFFFF800000000000 )
 #define defaultNaNF128UI0  UINT64_C( 0 )
 
 /*----------------------------------------------------------------------------
@@ -287,8 +255,7 @@ struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t
 | point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF128UI(uiA64, uiA0)                                                                                              \
+#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF ))))
-    ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF))))
 
 /*----------------------------------------------------------------------------
 | Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
@@ -297,25 +264,15 @@ struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t
 | pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid exception
 | is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_f128UIToCommonNaN(uiA64, uiA0, zPtr)                                                                                     \
+void
-    if(!((uiA64)&UINT64_C(0x0000800000000000)))                                                                                            \
+ softfloat_f128UIToCommonNaN(
-    softfloat_raiseFlags(softfloat_flag_invalid)
+     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
-#if defined INLINE && !defined softfloat_commonNaNToF128UI
-INLINE
-struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN* aPtr) {
-    struct uint128 uiZ;
-    uiZ.v64 = defaultNaNF128UI64;
-    uiZ.v0 = defaultNaNF128UI0;
-    return uiZ;
-}
-#else
 struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * );
-#endif
 
 /*----------------------------------------------------------------------------
 | Interpreting the unsigned integer formed from concatenating 'uiA64' and
@@ -326,7 +283,13 @@ struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN*);
 | If either original floating-point value is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0);
+struct uint128
+ softfloat_propagateNaNF128UI(
+     uint_fast64_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast64_t uiB64,
+     uint_fast64_t uiB0
+ );
 
 #else
 
@@ -341,24 +304,18 @@ struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t u
 | common NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling
 | NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_extF80MToCommonNaN(aSPtr, zPtr)                                                                                          \
+void
-    if(!((aSPtr)->signif & UINT64_C(0x4000000000000000)))                                                                                  \
+ softfloat_extF80MToCommonNaN(
-    softfloat_raiseFlags(softfloat_flag_invalid)
+     const struct extFloat80M *aSPtr, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
 | floating-point NaN, and stores this NaN at the location pointed to by
 | 'zSPtr'.
 *----------------------------------------------------------------------------*/
-#if defined INLINE && !defined softfloat_commonNaNToExtF80M
+void
-INLINE
+ softfloat_commonNaNToExtF80M(
-void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr) {
+     const struct commonNaN *aPtr, struct extFloat80M *zSPtr );
-    zSPtr->signExp = defaultNaNExtF80UI64;
-    zSPtr->signif = defaultNaNExtF80UI0;
-}
-#else
-void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr);
-#endif
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 80-bit extended floating-point values
@@ -366,12 +323,17 @@ void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat8
 | at the location pointed to by 'zSPtr'.  If either original floating-point
 | value is a signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr);
+void
+ softfloat_propagateNaNExtF80M(
+     const struct extFloat80M *aSPtr,
+     const struct extFloat80M *bSPtr,
+     struct extFloat80M *zSPtr
+ );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
 *----------------------------------------------------------------------------*/
-#define defaultNaNF128UI96 0x7FFF8000
+#define defaultNaNF128UI96 0xFFFF8000
 #define defaultNaNF128UI64 0
 #define defaultNaNF128UI32 0
 #define defaultNaNF128UI0  0
@@ -384,9 +346,8 @@ void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct
 | four 32-bit elements that concatenate in the platform's normal endian order
 | to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-#define softfloat_f128MToCommonNaN(aWPtr, zPtr)                                                                                            \
+void
-    if(!((aWPtr)[indexWordHi(4)] & UINT64_C(0x0000800000000000)))                                                                          \
+ softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr );
-    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -394,17 +355,8 @@ void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct
 | 'zWPtr' points to an array of four 32-bit elements that concatenate in the
 | platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-#if defined INLINE && !defined softfloat_commonNaNToF128M
+void
-INLINE
+ softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr );
-void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr) {
-    zWPtr[indexWord(4, 3)] = defaultNaNF128UI96;
-    zWPtr[indexWord(4, 2)] = defaultNaNF128UI64;
-    zWPtr[indexWord(4, 1)] = defaultNaNF128UI32;
-    zWPtr[indexWord(4, 0)] = defaultNaNF128UI0;
-}
-#else
-void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
-#endif
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 128-bit floating-point values pointed to by
@@ -414,8 +366,11 @@ void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
 | and 'zWPtr' points to an array of four 32-bit elements that concatenate in
 | the platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr);
+void
+ softfloat_propagateNaNF128M(
+     const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr );
 
 #endif
 
 #endif
+

softfloat/source/bf16_isSignalingNaN.c

@@ -1,51 +0,0 @@
-
-/*============================================================================
-
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
-
-Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
-California.  All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
-
- 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
-    specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-=============================================================================*/
-
-#include <stdbool.h>
-#include "platform.h"
-#include "internals.h"
-#include "specialize.h"
-#include "softfloat.h"
-
-bool bf16_isSignalingNaN( bfloat16_t a )
-{
-    union ui16_bf16 uA;
-
-    uA.f = a;
-    return softfloat_isSigNaNBF16UI( uA.ui );
-
-}
-

softfloat/source/bf16_to_f32.c

@@ -1,90 +0,0 @@
-
-/*============================================================================
-
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
-
-Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
-California.  All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
-
- 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
-    specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-=============================================================================*/
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "specialize.h"
-#include "softfloat.h"
-
-float32_t bf16_to_f32( bfloat16_t a )
-{
-    union ui16_bf16 uA;
-    uint_fast16_t uiA;
-    bool sign;
-    int_fast16_t exp;
-    uint_fast16_t frac;
-    struct commonNaN commonNaN;
-    uint_fast32_t uiZ;
-    struct exp8_sig16 normExpSig;
-    union ui32_f32 uZ;
-
-    /*------------------------------------------------------------------------
-    *------------------------------------------------------------------------*/
-    uA.f = a;
-    uiA = uA.ui;
-    sign = signBF16UI( uiA );
-    exp  = expBF16UI( uiA );
-    frac = fracBF16UI( uiA );
-    /*------------------------------------------------------------------------
-    *------------------------------------------------------------------------*/
-    // NaN or Inf
-    if ( exp == 0xFF ) {
-        if ( frac ) {
-            softfloat_bf16UIToCommonNaN( uiA, &commonNaN );
-            uiZ = softfloat_commonNaNToF32UI( &commonNaN );
-        } else {
-            uiZ = packToF32UI( sign, 0xFF, 0 );
-        }
-        goto uiZ;
-    }
-    /*------------------------------------------------------------------------
-    *------------------------------------------------------------------------*/
-    // packToF32UI simply packs bitfields without any numerical change
-    // which means it can be used directly for any BF16 to f32 conversions which
-    // does not require bits manipulation
-    // (that is everything where the 16-bit are just padded right with 16 zeros, including
-    //  subnormal numbers)
-    uiZ = packToF32UI( sign, exp, ((uint_fast32_t) frac) <<16 );
- uiZ:
-    uZ.ui = uiZ;
-    return uZ.f;
-
-}
-
-
-

softfloat/source/f32_to_bf16.c

@@ -1,105 +0,0 @@
-
-/*============================================================================
-
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
-
-Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
-California.  All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
-
- 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
-    specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-=============================================================================*/
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "specialize.h"
-#include "softfloat.h"
-
-#include <inttypes.h>
-#include <stdio.h>
-
-bfloat16_t f32_to_bf16( float32_t a )
-{
-    union ui32_f32 uA;
-    uint_fast32_t uiA;
-    bool sign;
-    int_fast16_t exp;
-    uint_fast32_t frac;
-    struct commonNaN commonNaN;
-    uint_fast16_t uiZ, frac16;
-    union ui16_bf16 uZ;
-
-    /*------------------------------------------------------------------------
-    *------------------------------------------------------------------------*/
-    uA.f = a;
-    uiA = uA.ui;
-    sign = signF32UI( uiA );
-    exp  = expF32UI( uiA );
-    frac = fracF32UI( uiA );
-    /*------------------------------------------------------------------------
-    *------------------------------------------------------------------------*/
-    // infinity or NaN cases
-    if ( exp == 0xFF ) {
-        if ( frac ) {
-            // NaN case
-            softfloat_f32UIToCommonNaN( uiA, &commonNaN );
-            uiZ = softfloat_commonNaNToBF16UI( &commonNaN );
-        } else {
-            // infinity case
-            uiZ = packToBF16UI( sign, 0xFF, 0 );
-        }
-        goto uiZ;
-    }
-    /*------------------------------------------------------------------------
-    *------------------------------------------------------------------------*/
-    // frac is a 24-bit mantissa, right shifted by 9
-    // In the normal case, (24-9) = 15 are set 
-    frac16 = frac>>9 | ((frac & 0x1FF) != 0);
-    if ( ! (exp | frac16) ) {
-        uiZ = packToBF16UI( sign, 0, 0 );
-        goto uiZ;
-    }
-    /*------------------------------------------------------------------------
-    *------------------------------------------------------------------------*/
-    // softfloat_roundPackToBF16 exponent argument (2nd argument)
-    // must correspond to the exponent of fracIn[13] bits
-    // (fracIn is the 3rd and last argument) 
-    uint_fast32_t mask = exp ? 0x4000 : 0x0; // implicit one mask added if input is a normal number
-    // exponent for the lowest normal and largest subnormal should be equal
-    // but is not in IEEE encoding so mantissa must be partially normalized
-    // (by one bit) for subnormal numbers. Such that (exp - 1) corresponds
-    // to the exponent of frac16[13]
-    frac16 = frac16 << (exp ? 0 : 1);
-    return softfloat_roundPackToBF16( sign, exp - 1, frac16 | mask );
- uiZ:
-    uZ.ui = uiZ;
-    return uZ.f;
-
-}
-

softfloat/source/f32_to_f16.c

@@ -72,9 +72,6 @@ float16_t f32_to_f16( float32_t a )
     }
     /*------------------------------------------------------------------------
     *------------------------------------------------------------------------*/
-    // frac is a 24-bit significand, the bottom 9 bits LSB are extracted and OR-red
-    // into a sticky flag, the top 15 MSBs are extracted, the LSB of this top slice
-    // is OR-red with the sticky 
     frac16 = frac>>9 | ((frac & 0x1FF) != 0);
     if ( ! (exp | frac16) ) {
         uiZ = packToF16UI( sign, 0, 0 );

softfloat/source/include/internals.h

@@ -37,47 +37,33 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifndef internals_h
 #define internals_h 1
 
-#include "primitives.h"
-#include "softfloat_types.h"
 #include <stdbool.h>
 #include <stdint.h>
+#include "primitives.h"
+#include "softfloat_types.h"
 
-union ui16_f16 {
+union ui16_f16 { uint16_t ui; float16_t f; };
-    uint16_t ui;
+union ui32_f32 { uint32_t ui; float32_t f; };
-    float16_t f;
+union ui64_f64 { uint64_t ui; float64_t f; };
-};
-union ui16_bf16 {
-    uint16_t ui;
-    bfloat16_t f;
-};
-union ui32_f32 {
-    uint32_t ui;
-    float32_t f;
-};
-union ui64_f64 {
-    uint64_t ui;
-    float64_t f;
-};
 
 #ifdef SOFTFLOAT_FAST_INT64
-union extF80M_extF80 {
+union extF80M_extF80 { struct extFloat80M fM; extFloat80_t f; };
-    struct extFloat80M fM;
+union ui128_f128 { struct uint128 ui; float128_t f; };
-    extFloat80_t f;
-};
-union ui128_f128 {
-    struct uint128 ui;
-    float128_t f;
-};
 #endif
 
-enum { softfloat_mulAdd_subC = 1, softfloat_mulAdd_subProd = 2 };
+enum {
+    softfloat_mulAdd_subC    = 1,
+    softfloat_mulAdd_subProd = 2
+};
 
 /*----------------------------------------------------------------------------
 *----------------------------------------------------------------------------*/
 uint_fast32_t softfloat_roundToUI32( bool, uint_fast64_t, uint_fast8_t, bool );
 
 #ifdef SOFTFLOAT_FAST_INT64
-uint_fast64_t softfloat_roundToUI64(bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool);
+uint_fast64_t
+ softfloat_roundToUI64(
+     bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool );
 #else
 uint_fast64_t softfloat_roundMToUI64( bool, uint32_t *, uint_fast8_t, bool );
 #endif
@@ -85,7 +71,9 @@ uint_fast64_t softfloat_roundMToUI64(bool, uint32_t*, uint_fast8_t, bool);
 int_fast32_t softfloat_roundToI32( bool, uint_fast64_t, uint_fast8_t, bool );
 
 #ifdef SOFTFLOAT_FAST_INT64
-int_fast64_t softfloat_roundToI64(bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool);
+int_fast64_t
+ softfloat_roundToI64(
+     bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool );
 #else
 int_fast64_t softfloat_roundMToI64( bool, uint32_t *, uint_fast8_t, bool );
 #endif
@@ -99,10 +87,7 @@ int_fast64_t softfloat_roundMToI64(bool, uint32_t*, uint_fast8_t, bool);
 
 #define isNaNF16UI( a ) (((~(a) & 0x7C00) == 0) && ((a) & 0x03FF))
 
-struct exp8_sig16 {
+struct exp8_sig16 { int_fast8_t exp; uint_fast16_t sig; };
-    int_fast8_t exp;
-    uint_fast16_t sig;
-};
 struct exp8_sig16 softfloat_normSubnormalF16Sig( uint_fast16_t );
 
 float16_t softfloat_roundPackToF16( bool, int_fast16_t, uint_fast16_t );
@@ -110,19 +95,9 @@ float16_t softfloat_normRoundPackToF16(bool, int_fast16_t, uint_fast16_t);
 
 float16_t softfloat_addMagsF16( uint_fast16_t, uint_fast16_t );
 float16_t softfloat_subMagsF16( uint_fast16_t, uint_fast16_t );
-float16_t softfloat_mulAddF16(uint_fast16_t, uint_fast16_t, uint_fast16_t, uint_fast8_t);
+float16_t
-
+ softfloat_mulAddF16(
-/*----------------------------------------------------------------------------
+     uint_fast16_t, uint_fast16_t, uint_fast16_t, uint_fast8_t );
- *----------------------------------------------------------------------------*/
-#define signBF16UI(a) ((bool)((uint16_t)(a) >> 15))
-#define expBF16UI(a) ((int_fast16_t)((a) >> 7) & 0xFF)
-#define fracBF16UI(a) ((a)&0x07F)
-#define packToBF16UI(sign, exp, sig) (((uint16_t)(sign) << 15) + ((uint16_t)(exp) << 7) + (sig))
-
-#define isNaNBF16UI(a) (((~(a)&0x7FC0) == 0) && ((a)&0x07F))
-
-bfloat16_t softfloat_roundPackToBF16(bool, int_fast16_t, uint_fast16_t);
-struct exp8_sig16 softfloat_normSubnormalBF16Sig(uint_fast16_t);
 
 /*----------------------------------------------------------------------------
 *----------------------------------------------------------------------------*/
@@ -133,10 +108,7 @@ struct exp8_sig16 softfloat_normSubnormalBF16Sig(uint_fast16_t);
 
 #define isNaNF32UI( a ) (((~(a) & 0x7F800000) == 0) && ((a) & 0x007FFFFF))
 
-struct exp16_sig32 {
+struct exp16_sig32 { int_fast16_t exp; uint_fast32_t sig; };
-    int_fast16_t exp;
-    uint_fast32_t sig;
-};
 struct exp16_sig32 softfloat_normSubnormalF32Sig( uint_fast32_t );
 
 float32_t softfloat_roundPackToF32( bool, int_fast16_t, uint_fast32_t );
@@ -144,7 +116,9 @@ float32_t softfloat_normRoundPackToF32(bool, int_fast16_t, uint_fast32_t);
 
 float32_t softfloat_addMagsF32( uint_fast32_t, uint_fast32_t );
 float32_t softfloat_subMagsF32( uint_fast32_t, uint_fast32_t );
-float32_t softfloat_mulAddF32(uint_fast32_t, uint_fast32_t, uint_fast32_t, uint_fast8_t);
+float32_t
+ softfloat_mulAddF32(
+     uint_fast32_t, uint_fast32_t, uint_fast32_t, uint_fast8_t );
 
 /*----------------------------------------------------------------------------
 *----------------------------------------------------------------------------*/
@@ -155,10 +129,7 @@ float32_t softfloat_mulAddF32(uint_fast32_t, uint_fast32_t, uint_fast32_t, uint_
 
 #define isNaNF64UI( a ) (((~(a) & UINT64_C( 0x7FF0000000000000 )) == 0) && ((a) & UINT64_C( 0x000FFFFFFFFFFFFF )))
 
-struct exp16_sig64 {
+struct exp16_sig64 { int_fast16_t exp; uint_fast64_t sig; };
-    int_fast16_t exp;
-    uint_fast64_t sig;
-};
 struct exp16_sig64 softfloat_normSubnormalF64Sig( uint_fast64_t );
 
 float64_t softfloat_roundPackToF64( bool, int_fast16_t, uint_fast64_t );
@@ -166,7 +137,9 @@ float64_t softfloat_normRoundPackToF64(bool, int_fast16_t, uint_fast64_t);
 
 float64_t softfloat_addMagsF64( uint_fast64_t, uint_fast64_t, bool );
 float64_t softfloat_subMagsF64( uint_fast64_t, uint_fast64_t, bool );
-float64_t softfloat_mulAddF64(uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast8_t);
+float64_t
+ softfloat_mulAddF64(
+     uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast8_t );
 
 /*----------------------------------------------------------------------------
 *----------------------------------------------------------------------------*/
@@ -181,17 +154,22 @@ float64_t softfloat_mulAddF64(uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_
 /*----------------------------------------------------------------------------
 *----------------------------------------------------------------------------*/
 
-struct exp32_sig64 {
+struct exp32_sig64 { int_fast32_t exp; uint64_t sig; };
-    int_fast32_t exp;
-    uint64_t sig;
-};
 struct exp32_sig64 softfloat_normSubnormalExtF80Sig( uint_fast64_t );
 
-extFloat80_t softfloat_roundPackToExtF80(bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t);
+extFloat80_t
-extFloat80_t softfloat_normRoundPackToExtF80(bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t);
+ softfloat_roundPackToExtF80(
+     bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t );
+extFloat80_t
+ softfloat_normRoundPackToExtF80(
+     bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t );
 
-extFloat80_t softfloat_addMagsExtF80(uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool);
+extFloat80_t
-extFloat80_t softfloat_subMagsExtF80(uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool);
+ softfloat_addMagsExtF80(
+     uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );
+extFloat80_t
+ softfloat_subMagsExtF80(
+     uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );
 
 /*----------------------------------------------------------------------------
 *----------------------------------------------------------------------------*/
@@ -202,35 +180,67 @@ extFloat80_t softfloat_subMagsExtF80(uint_fast16_t, uint_fast64_t, uint_fast16_t
 
 #define isNaNF128UI( a64, a0 ) (((~(a64) & UINT64_C( 0x7FFF000000000000 )) == 0) && (a0 || ((a64) & UINT64_C( 0x0000FFFFFFFFFFFF ))))
 
-struct exp32_sig128 {
+struct exp32_sig128 { int_fast32_t exp; struct uint128 sig; };
-    int_fast32_t exp;
+struct exp32_sig128
-    struct uint128 sig;
+ softfloat_normSubnormalF128Sig( uint_fast64_t, uint_fast64_t );
-};
-struct exp32_sig128 softfloat_normSubnormalF128Sig(uint_fast64_t, uint_fast64_t);
 
-float128_t softfloat_roundPackToF128(bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast64_t);
+float128_t
-float128_t softfloat_normRoundPackToF128(bool, int_fast32_t, uint_fast64_t, uint_fast64_t);
+ softfloat_roundPackToF128(
+     bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast64_t );
+float128_t
+ softfloat_normRoundPackToF128(
+     bool, int_fast32_t, uint_fast64_t, uint_fast64_t );
 
-float128_t softfloat_addMagsF128(uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool);
+float128_t
-float128_t softfloat_subMagsF128(uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool);
+ softfloat_addMagsF128(
-float128_t softfloat_mulAddF128(uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast8_t);
+     uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool );
+float128_t
+ softfloat_subMagsF128(
+     uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool );
+float128_t
+ softfloat_mulAddF128(
+     uint_fast64_t,
+     uint_fast64_t,
+     uint_fast64_t,
+     uint_fast64_t,
+     uint_fast64_t,
+     uint_fast64_t,
+     uint_fast8_t
+ );
 
 #else
 
 /*----------------------------------------------------------------------------
 *----------------------------------------------------------------------------*/
 
-bool softfloat_tryPropagateNaNExtF80M(const struct extFloat80M*, const struct extFloat80M*, struct extFloat80M*);
+bool
+ softfloat_tryPropagateNaNExtF80M(
+     const struct extFloat80M *,
+     const struct extFloat80M *,
+     struct extFloat80M *
+ );
 void softfloat_invalidExtF80M( struct extFloat80M * );
 
 int softfloat_normExtF80SigM( uint64_t * );
 
-void softfloat_roundPackMToExtF80M(bool, int32_t, uint32_t*, uint_fast8_t, struct extFloat80M*);
+void
-void softfloat_normRoundPackMToExtF80M(bool, int32_t, uint32_t*, uint_fast8_t, struct extFloat80M*);
+ softfloat_roundPackMToExtF80M(
+     bool, int32_t, uint32_t *, uint_fast8_t, struct extFloat80M * );
+void
+ softfloat_normRoundPackMToExtF80M(
+     bool, int32_t, uint32_t *, uint_fast8_t, struct extFloat80M * );
 
-void softfloat_addExtF80M(const struct extFloat80M*, const struct extFloat80M*, struct extFloat80M*, bool);
+void
+ softfloat_addExtF80M(
+     const struct extFloat80M *,
+     const struct extFloat80M *,
+     struct extFloat80M *,
+     bool
+ );
 
-int softfloat_compareNonnormExtF80M(const struct extFloat80M*, const struct extFloat80M*);
+int
+ softfloat_compareNonnormExtF80M(
+     const struct extFloat80M *, const struct extFloat80M * );
 
 /*----------------------------------------------------------------------------
 *----------------------------------------------------------------------------*/
@@ -241,7 +251,9 @@ int softfloat_compareNonnormExtF80M(const struct extFloat80M*, const struct extF
 
 bool softfloat_isNaNF128M( const uint32_t * );
 
-bool softfloat_tryPropagateNaNF128M(const uint32_t*, const uint32_t*, uint32_t*);
+bool
+ softfloat_tryPropagateNaNF128M(
+     const uint32_t *, const uint32_t *, uint32_t * );
 void softfloat_invalidF128M( uint32_t * );
 
 int softfloat_shiftNormSigF128M( const uint32_t *, uint_fast8_t, uint32_t * );
@@ -249,9 +261,18 @@ int softfloat_shiftNormSigF128M(const uint32_t*, uint_fast8_t, uint32_t*);
 void softfloat_roundPackMToF128M( bool, int32_t, uint32_t *, uint32_t * );
 void softfloat_normRoundPackMToF128M( bool, int32_t, uint32_t *, uint32_t * );
 
-void softfloat_addF128M(const uint32_t*, const uint32_t*, uint32_t*, bool);
+void
-void softfloat_mulAddF128M(const uint32_t*, const uint32_t*, const uint32_t*, uint32_t*, uint_fast8_t);
+ softfloat_addF128M( const uint32_t *, const uint32_t *, uint32_t *, bool );
+void
+ softfloat_mulAddF128M(
+     const uint32_t *,
+     const uint32_t *,
+     const uint32_t *,
+     uint32_t *,
+     uint_fast8_t
+ );
 
 #endif
 
 #endif
+

softfloat/source/include/opts-GCC.h

@@ -39,57 +39,57 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 #ifdef INLINE
 
-#include "primitiveTypes.h"
 #include <stdint.h>
+#include "primitiveTypes.h"
 
 #ifdef SOFTFLOAT_BUILTIN_CLZ
 
-INLINE uint_fast8_t softfloat_countLeadingZeros16(uint16_t a) { return a ? __builtin_clz(a) - 16 : 16; }
+INLINE uint_fast8_t softfloat_countLeadingZeros16( uint16_t a )
+    { return a ? __builtin_clz( a ) - 16 : 16; }
 #define softfloat_countLeadingZeros16 softfloat_countLeadingZeros16
 
-INLINE uint_fast8_t softfloat_countLeadingZeros32(uint32_t a) { return a ? __builtin_clz(a) : 32; }
+INLINE uint_fast8_t softfloat_countLeadingZeros32( uint32_t a )
+    { return a ? __builtin_clz( a ) : 32; }
 #define softfloat_countLeadingZeros32 softfloat_countLeadingZeros32
 
-INLINE uint_fast8_t softfloat_countLeadingZeros64(uint64_t a) { return a ? __builtin_clzll(a) : 64; }
+INLINE uint_fast8_t softfloat_countLeadingZeros64( uint64_t a )
+    { return a ? __builtin_clzll( a ) : 64; }
 #define softfloat_countLeadingZeros64 softfloat_countLeadingZeros64
 
 #endif
 
 #ifdef SOFTFLOAT_INTRINSIC_INT128
 
-INLINE struct uint128 softfloat_mul64ByShifted32To128(uint64_t a, uint32_t b) {
+INLINE struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b )
-    union {
+{
-        unsigned __int128 ui;
+    union { unsigned __int128 ui; struct uint128 s; } uZ;
-        struct uint128 s;
-    } uZ;
     uZ.ui = (unsigned __int128) a * ((uint_fast64_t) b<<32);
     return uZ.s;
 }
 #define softfloat_mul64ByShifted32To128 softfloat_mul64ByShifted32To128
 
-INLINE struct uint128 softfloat_mul64To128(uint64_t a, uint64_t b) {
+INLINE struct uint128 softfloat_mul64To128( uint64_t a, uint64_t b )
-    union {
+{
-        unsigned __int128 ui;
+    union { unsigned __int128 ui; struct uint128 s; } uZ;
-        struct uint128 s;
-    } uZ;
     uZ.ui = (unsigned __int128) a * b;
     return uZ.s;
 }
 #define softfloat_mul64To128 softfloat_mul64To128
 
 INLINE
-struct uint128 softfloat_mul128By32(uint64_t a64, uint64_t a0, uint32_t b) {
+struct uint128 softfloat_mul128By32( uint64_t a64, uint64_t a0, uint32_t b )
-    union {
+{
-        unsigned __int128 ui;
+    union { unsigned __int128 ui; struct uint128 s; } uZ;
-        struct uint128 s;
-    } uZ;
     uZ.ui = ((unsigned __int128) a64<<64 | a0) * b;
     return uZ.s;
 }
 #define softfloat_mul128By32 softfloat_mul128By32
 
 INLINE
-void softfloat_mul128To256M(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t* zPtr) {
+void
+ softfloat_mul128To256M(
+     uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t *zPtr )
+{
     unsigned __int128 z0, mid1, mid, z128;
     z0 = (unsigned __int128) a0 * b0;
     mid1 = (unsigned __int128) a64 * b0;
@@ -111,3 +111,4 @@ void softfloat_mul128To256M(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0
 #endif
 
 #endif
+

softfloat/source/include/primitiveTypes.h

@@ -42,27 +42,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifdef SOFTFLOAT_FAST_INT64
 
 #ifdef LITTLEENDIAN
-struct uint128 {
+struct uint128 { uint64_t v0, v64; };
-    uint64_t v0, v64;
+struct uint64_extra { uint64_t extra, v; };
-};
+struct uint128_extra { uint64_t extra; struct uint128 v; };
-struct uint64_extra {
-    uint64_t extra, v;
-};
-struct uint128_extra {
-    uint64_t extra;
-    struct uint128 v;
-};
 #else
-struct uint128 {
+struct uint128 { uint64_t v64, v0; };
-    uint64_t v64, v0;
+struct uint64_extra { uint64_t v, extra; };
-};
+struct uint128_extra { struct uint128 v; uint64_t extra; };
-struct uint64_extra {
-    uint64_t v, extra;
-};
-struct uint128_extra {
-    struct uint128 v;
-    uint64_t extra;
-};
 #endif
 
 #endif
@@ -81,8 +67,7 @@ struct uint128_extra {
 #define indexMultiwordLo( total, n ) 0
 #define indexMultiwordHiBut( total, n ) (n)
 #define indexMultiwordLoBut( total, n ) 0
-#define INIT_UINTM4(v3, v2, v1, v0)                                                                                                        \
+#define INIT_UINTM4( v3, v2, v1, v0 ) { v0, v1, v2, v3 }
-    { v0, v1, v2, v3 }
 #else
 #define wordIncr -1
 #define indexWord( total, n ) ((total) - 1 - (n))
@@ -93,8 +78,8 @@ struct uint128_extra {
 #define indexMultiwordLo( total, n ) ((total) - (n))
 #define indexMultiwordHiBut( total, n ) 0
 #define indexMultiwordLoBut( total, n ) (n)
-#define INIT_UINTM4(v3, v2, v1, v0)                                                                                                        \
+#define INIT_UINTM4( v3, v2, v1, v0 ) { v3, v2, v1, v0 }
-    { v3, v2, v1, v0 }
 #endif
 
 #endif
+

softfloat/source/include/primitives.h

@@ -37,9 +37,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifndef primitives_h
 #define primitives_h 1
 
-#include "primitiveTypes.h"
 #include <stdbool.h>
 #include <stdint.h>
+#include "primitiveTypes.h"
 
 #ifndef softfloat_shortShiftRightJam64
 /*----------------------------------------------------------------------------
@@ -50,7 +50,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-uint64_t softfloat_shortShiftRightJam64(uint64_t a, uint_fast8_t dist) { return a >> dist | ((a & (((uint_fast64_t)1 << dist) - 1)) != 0); }
+uint64_t softfloat_shortShiftRightJam64( uint64_t a, uint_fast8_t dist )
+    { return a>>dist | ((a & (((uint_fast64_t) 1<<dist) - 1)) != 0); }
 #else
 uint64_t softfloat_shortShiftRightJam64( uint64_t a, uint_fast8_t dist );
 #endif
@@ -67,8 +68,10 @@ uint64_t softfloat_shortShiftRightJam64(uint64_t a, uint_fast8_t dist);
 | is zero or nonzero.
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
-INLINE uint32_t softfloat_shiftRightJam32(uint32_t a, uint_fast16_t dist) {
+INLINE uint32_t softfloat_shiftRightJam32( uint32_t a, uint_fast16_t dist )
-    return (dist < 31) ? a >> dist | ((uint32_t)(a << (-dist & 31)) != 0) : (a != 0);
+{
+    return
+        (dist < 31) ? a>>dist | ((uint32_t) (a<<(-dist & 31)) != 0) : (a != 0);
 }
 #else
 uint32_t softfloat_shiftRightJam32( uint32_t a, uint_fast16_t dist );
@@ -86,8 +89,10 @@ uint32_t softfloat_shiftRightJam32(uint32_t a, uint_fast16_t dist);
 | is zero or nonzero.
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (3 <= INLINE_LEVEL)
-INLINE uint64_t softfloat_shiftRightJam64(uint64_t a, uint_fast32_t dist) {
+INLINE uint64_t softfloat_shiftRightJam64( uint64_t a, uint_fast32_t dist )
-    return (dist < 63) ? a >> dist | ((uint64_t)(a << (-dist & 63)) != 0) : (a != 0);
+{
+    return
+        (dist < 63) ? a>>dist | ((uint64_t) (a<<(-dist & 63)) != 0) : (a != 0);
 }
 #else
 uint64_t softfloat_shiftRightJam64( uint64_t a, uint_fast32_t dist );
@@ -107,7 +112,8 @@ extern const uint_least8_t softfloat_countLeadingZeros8[256];
 | 'a'.  If 'a' is zero, 16 is returned.
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
-INLINE uint_fast8_t softfloat_countLeadingZeros16(uint16_t a) {
+INLINE uint_fast8_t softfloat_countLeadingZeros16( uint16_t a )
+{
     uint_fast8_t count = 8;
     if ( 0x100 <= a ) {
         count = 0;
@@ -127,7 +133,8 @@ uint_fast8_t softfloat_countLeadingZeros16(uint16_t a);
 | 'a'.  If 'a' is zero, 32 is returned.
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (3 <= INLINE_LEVEL)
-INLINE uint_fast8_t softfloat_countLeadingZeros32(uint32_t a) {
+INLINE uint_fast8_t softfloat_countLeadingZeros32( uint32_t a )
+{
     uint_fast8_t count = 0;
     if ( a < 0x10000 ) {
         count = 16;
@@ -215,7 +222,8 @@ uint32_t softfloat_approxRecipSqrt32_1(unsigned int oddExpA, uint32_t a);
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (1 <= INLINE_LEVEL)
 INLINE
-bool softfloat_eq128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) { return (a64 == b64) && (a0 == b0); }
+bool softfloat_eq128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
+    { return (a64 == b64) && (a0 == b0); }
 #else
 bool softfloat_eq128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
 #endif
@@ -229,7 +237,8 @@ bool softfloat_eq128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0);
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-bool softfloat_le128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) { return (a64 < b64) || ((a64 == b64) && (a0 <= b0)); }
+bool softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
+    { return (a64 < b64) || ((a64 == b64) && (a0 <= b0)); }
 #else
 bool softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
 #endif
@@ -243,7 +252,8 @@ bool softfloat_le128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0);
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-bool softfloat_lt128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) { return (a64 < b64) || ((a64 == b64) && (a0 < b0)); }
+bool softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
+    { return (a64 < b64) || ((a64 == b64) && (a0 < b0)); }
 #else
 bool softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
 #endif
@@ -256,14 +266,17 @@ bool softfloat_lt128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0);
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-struct uint128 softfloat_shortShiftLeft128(uint64_t a64, uint64_t a0, uint_fast8_t dist) {
+struct uint128
+ softfloat_shortShiftLeft128( uint64_t a64, uint64_t a0, uint_fast8_t dist )
+{
     struct uint128 z;
     z.v64 = a64<<dist | a0>>(-dist & 63);
     z.v0 = a0<<dist;
     return z;
 }
 #else
-struct uint128 softfloat_shortShiftLeft128(uint64_t a64, uint64_t a0, uint_fast8_t dist);
+struct uint128
+ softfloat_shortShiftLeft128( uint64_t a64, uint64_t a0, uint_fast8_t dist );
 #endif
 #endif
 
@@ -274,14 +287,17 @@ struct uint128 softfloat_shortShiftLeft128(uint64_t a64, uint64_t a0, uint_fast8
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-struct uint128 softfloat_shortShiftRight128(uint64_t a64, uint64_t a0, uint_fast8_t dist) {
+struct uint128
+ softfloat_shortShiftRight128( uint64_t a64, uint64_t a0, uint_fast8_t dist )
+{
     struct uint128 z;
     z.v64 = a64>>dist;
     z.v0 = a64<<(-dist & 63) | a0>>dist;
     return z;
 }
 #else
-struct uint128 softfloat_shortShiftRight128(uint64_t a64, uint64_t a0, uint_fast8_t dist);
+struct uint128
+ softfloat_shortShiftRight128( uint64_t a64, uint64_t a0, uint_fast8_t dist );
 #endif
 #endif
 
@@ -292,14 +308,19 @@ struct uint128 softfloat_shortShiftRight128(uint64_t a64, uint64_t a0, uint_fast
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-struct uint64_extra softfloat_shortShiftRightJam64Extra(uint64_t a, uint64_t extra, uint_fast8_t dist) {
+struct uint64_extra
+ softfloat_shortShiftRightJam64Extra(
+     uint64_t a, uint64_t extra, uint_fast8_t dist )
+{
     struct uint64_extra z;
     z.v = a>>dist;
     z.extra = a<<(-dist & 63) | (extra != 0);
     return z;
 }
 #else
-struct uint64_extra softfloat_shortShiftRightJam64Extra(uint64_t a, uint64_t extra, uint_fast8_t dist);
+struct uint64_extra
+ softfloat_shortShiftRightJam64Extra(
+     uint64_t a, uint64_t extra, uint_fast8_t dist );
 #endif
 #endif
 
@@ -313,15 +334,22 @@ struct uint64_extra softfloat_shortShiftRightJam64Extra(uint64_t a, uint64_t ext
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (3 <= INLINE_LEVEL)
 INLINE
-struct uint128 softfloat_shortShiftRightJam128(uint64_t a64, uint64_t a0, uint_fast8_t dist) {
+struct uint128
+ softfloat_shortShiftRightJam128(
+     uint64_t a64, uint64_t a0, uint_fast8_t dist )
+{
     uint_fast8_t negDist = -dist;
     struct uint128 z;
     z.v64 = a64>>dist;
-    z.v0 = a64 << (negDist & 63) | a0 >> dist | ((uint64_t)(a0 << (negDist & 63)) != 0);
+    z.v0 =
+        a64<<(negDist & 63) | a0>>dist
+            | ((uint64_t) (a0<<(negDist & 63)) != 0);
     return z;
 }
 #else
-struct uint128 softfloat_shortShiftRightJam128(uint64_t a64, uint64_t a0, uint_fast8_t dist);
+struct uint128
+ softfloat_shortShiftRightJam128(
+     uint64_t a64, uint64_t a0, uint_fast8_t dist );
 #endif
 #endif
 
@@ -332,7 +360,10 @@ struct uint128 softfloat_shortShiftRightJam128(uint64_t a64, uint64_t a0, uint_f
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (3 <= INLINE_LEVEL)
 INLINE
-struct uint128_extra softfloat_shortShiftRightJam128Extra(uint64_t a64, uint64_t a0, uint64_t extra, uint_fast8_t dist) {
+struct uint128_extra
+ softfloat_shortShiftRightJam128Extra(
+     uint64_t a64, uint64_t a0, uint64_t extra, uint_fast8_t dist )
+{
     uint_fast8_t negDist = -dist;
     struct uint128_extra z;
     z.v.v64 = a64>>dist;
@@ -341,7 +372,9 @@ struct uint128_extra softfloat_shortShiftRightJam128Extra(uint64_t a64, uint64_t
     return z;
 }
 #else
-struct uint128_extra softfloat_shortShiftRightJam128Extra(uint64_t a64, uint64_t a0, uint64_t extra, uint_fast8_t dist);
+struct uint128_extra
+ softfloat_shortShiftRightJam128Extra(
+     uint64_t a64, uint64_t a0, uint64_t extra, uint_fast8_t dist );
 #endif
 #endif
 
@@ -364,7 +397,10 @@ struct uint128_extra softfloat_shortShiftRightJam128Extra(uint64_t a64, uint64_t
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (4 <= INLINE_LEVEL)
 INLINE
-struct uint64_extra softfloat_shiftRightJam64Extra(uint64_t a, uint64_t extra, uint_fast32_t dist) {
+struct uint64_extra
+ softfloat_shiftRightJam64Extra(
+     uint64_t a, uint64_t extra, uint_fast32_t dist )
+{
     struct uint64_extra z;
     if ( dist < 64 ) {
         z.v = a>>dist;
@@ -377,7 +413,9 @@ struct uint64_extra softfloat_shiftRightJam64Extra(uint64_t a, uint64_t extra, u
     return z;
 }
 #else
-struct uint64_extra softfloat_shiftRightJam64Extra(uint64_t a, uint64_t extra, uint_fast32_t dist);
+struct uint64_extra
+ softfloat_shiftRightJam64Extra(
+     uint64_t a, uint64_t extra, uint_fast32_t dist );
 #endif
 #endif
 
@@ -392,7 +430,8 @@ struct uint64_extra softfloat_shiftRightJam64Extra(uint64_t a, uint64_t extra, u
 | greater than 128, the result will be either 0 or 1, depending on whether the
 | original 128 bits are all zeros.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_shiftRightJam128(uint64_t a64, uint64_t a0, uint_fast32_t dist);
+struct uint128
+ softfloat_shiftRightJam128( uint64_t a64, uint64_t a0, uint_fast32_t dist );
 #endif
 
 #ifndef softfloat_shiftRightJam128Extra
@@ -413,7 +452,9 @@ struct uint128 softfloat_shiftRightJam128(uint64_t a64, uint64_t a0, uint_fast32
 | is modified as described above and returned in the 'extra' field of the
 | result.)
 *----------------------------------------------------------------------------*/
-struct uint128_extra softfloat_shiftRightJam128Extra(uint64_t a64, uint64_t a0, uint64_t extra, uint_fast32_t dist);
+struct uint128_extra
+ softfloat_shiftRightJam128Extra(
+     uint64_t a64, uint64_t a0, uint64_t extra, uint_fast32_t dist );
 #endif
 
 #ifndef softfloat_shiftRightJam256M
@@ -429,7 +470,9 @@ struct uint128_extra softfloat_shiftRightJam128Extra(uint64_t a64, uint64_t a0,
 | is greater than 256, the stored result will be either 0 or 1, depending on
 | whether the original 256 bits are all zeros.
 *----------------------------------------------------------------------------*/
-void softfloat_shiftRightJam256M(const uint64_t* aPtr, uint_fast32_t dist, uint64_t* zPtr);
+void
+ softfloat_shiftRightJam256M(
+     const uint64_t *aPtr, uint_fast32_t dist, uint64_t *zPtr );
 #endif
 
 #ifndef softfloat_add128
@@ -440,14 +483,17 @@ void softfloat_shiftRightJam256M(const uint64_t* aPtr, uint_fast32_t dist, uint6
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-struct uint128 softfloat_add128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) {
+struct uint128
+ softfloat_add128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
+{
     struct uint128 z;
     z.v0 = a0 + b0;
     z.v64 = a64 + b64 + (z.v0 < a0);
     return z;
 }
 #else
-struct uint128 softfloat_add128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0);
+struct uint128
+ softfloat_add128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
 #endif
 #endif
 
@@ -459,7 +505,9 @@ struct uint128 softfloat_add128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_
 | an array of four 64-bit elements that concatenate in the platform's normal
 | endian order to form a 256-bit integer.
 *----------------------------------------------------------------------------*/
-void softfloat_add256M(const uint64_t* aPtr, const uint64_t* bPtr, uint64_t* zPtr);
+void
+ softfloat_add256M(
+     const uint64_t *aPtr, const uint64_t *bPtr, uint64_t *zPtr );
 #endif
 
 #ifndef softfloat_sub128
@@ -470,7 +518,9 @@ void softfloat_add256M(const uint64_t* aPtr, const uint64_t* bPtr, uint64_t* zPt
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-struct uint128 softfloat_sub128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) {
+struct uint128
+ softfloat_sub128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
+{
     struct uint128 z;
     z.v0 = a0 - b0;
     z.v64 = a64 - b64;
@@ -478,7 +528,8 @@ struct uint128 softfloat_sub128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_
     return z;
 }
 #else
-struct uint128 softfloat_sub128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0);
+struct uint128
+ softfloat_sub128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
 #endif
 #endif
 
@@ -491,7 +542,9 @@ struct uint128 softfloat_sub128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_
 | 64-bit elements that concatenate in the platform's normal endian order to
 | form a 256-bit integer.
 *----------------------------------------------------------------------------*/
-void softfloat_sub256M(const uint64_t* aPtr, const uint64_t* bPtr, uint64_t* zPtr);
+void
+ softfloat_sub256M(
+     const uint64_t *aPtr, const uint64_t *bPtr, uint64_t *zPtr );
 #endif
 
 #ifndef softfloat_mul64ByShifted32To128
@@ -499,7 +552,8 @@ void softfloat_sub256M(const uint64_t* aPtr, const uint64_t* bPtr, uint64_t* zPt
 | Returns the 128-bit product of 'a', 'b', and 2^32.
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (3 <= INLINE_LEVEL)
-INLINE struct uint128 softfloat_mul64ByShifted32To128(uint64_t a, uint32_t b) {
+INLINE struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b )
+{
     uint_fast64_t mid;
     struct uint128 z;
     mid = (uint_fast64_t) (uint32_t) a * b;
@@ -527,7 +581,8 @@ struct uint128 softfloat_mul64To128(uint64_t a, uint64_t b);
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (4 <= INLINE_LEVEL)
 INLINE
-struct uint128 softfloat_mul128By32(uint64_t a64, uint64_t a0, uint32_t b) {
+struct uint128 softfloat_mul128By32( uint64_t a64, uint64_t a0, uint32_t b )
+{
     struct uint128 z;
     uint_fast64_t mid;
     uint_fast32_t carry;
@@ -550,7 +605,9 @@ struct uint128 softfloat_mul128By32(uint64_t a64, uint64_t a0, uint32_t b);
 | Argument 'zPtr' points to an array of four 64-bit elements that concatenate
 | in the platform's normal endian order to form a 256-bit integer.
 *----------------------------------------------------------------------------*/
-void softfloat_mul128To256M(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t* zPtr);
+void
+ softfloat_mul128To256M(
+     uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t *zPtr );
 #endif
 
 #else
@@ -581,7 +638,8 @@ int_fast8_t softfloat_compare96M(const uint32_t* aPtr, const uint32_t* bPtr);
 | Each of 'aPtr' and 'bPtr' points to an array of four 32-bit elements that
 | concatenate in the platform's normal endian order to form a 128-bit integer.
 *----------------------------------------------------------------------------*/
-int_fast8_t softfloat_compare128M(const uint32_t* aPtr, const uint32_t* bPtr);
+int_fast8_t
+ softfloat_compare128M( const uint32_t *aPtr, const uint32_t *bPtr );
 #endif
 
 #ifndef softfloat_shortShiftLeft64To96M
@@ -594,14 +652,19 @@ int_fast8_t softfloat_compare128M(const uint32_t* aPtr, const uint32_t* bPtr);
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-void softfloat_shortShiftLeft64To96M(uint64_t a, uint_fast8_t dist, uint32_t* zPtr) {
+void
+ softfloat_shortShiftLeft64To96M(
+     uint64_t a, uint_fast8_t dist, uint32_t *zPtr )
+{
     zPtr[indexWord( 3, 0 )] = (uint32_t) a<<dist;
     a >>= 32 - dist;
     zPtr[indexWord( 3, 2 )] = a>>32;
     zPtr[indexWord( 3, 1 )] = a;
 }
 #else
-void softfloat_shortShiftLeft64To96M(uint64_t a, uint_fast8_t dist, uint32_t* zPtr);
+void
+ softfloat_shortShiftLeft64To96M(
+     uint64_t a, uint_fast8_t dist, uint32_t *zPtr );
 #endif
 #endif
 
@@ -615,7 +678,13 @@ void softfloat_shortShiftLeft64To96M(uint64_t a, uint_fast8_t dist, uint32_t* zP
 | that concatenate in the platform's normal endian order to form an N-bit
 | integer.
 *----------------------------------------------------------------------------*/
-void softfloat_shortShiftLeftM(uint_fast8_t size_words, const uint32_t* aPtr, uint_fast8_t dist, uint32_t* zPtr);
+void
+ softfloat_shortShiftLeftM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     uint_fast8_t dist,
+     uint32_t *zPtr
+ );
 #endif
 
 #ifndef softfloat_shortShiftLeft96M
@@ -653,7 +722,13 @@ void softfloat_shortShiftLeftM(uint_fast8_t size_words, const uint32_t* aPtr, ui
 |   The value of 'dist' can be arbitrarily large.  In particular, if 'dist' is
 | greater than N, the stored result will be 0.
 *----------------------------------------------------------------------------*/
-void softfloat_shiftLeftM(uint_fast8_t size_words, const uint32_t* aPtr, uint32_t dist, uint32_t* zPtr);
+void
+ softfloat_shiftLeftM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     uint32_t dist,
+     uint32_t *zPtr
+ );
 #endif
 
 #ifndef softfloat_shiftLeft96M
@@ -690,7 +765,13 @@ void softfloat_shiftLeftM(uint_fast8_t size_words, const uint32_t* aPtr, uint32_
 | that concatenate in the platform's normal endian order to form an N-bit
 | integer.
 *----------------------------------------------------------------------------*/
-void softfloat_shortShiftRightM(uint_fast8_t size_words, const uint32_t* aPtr, uint_fast8_t dist, uint32_t* zPtr);
+void
+ softfloat_shortShiftRightM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     uint_fast8_t dist,
+     uint32_t *zPtr
+ );
 #endif
 
 #ifndef softfloat_shortShiftRight128M
@@ -720,7 +801,9 @@ void softfloat_shortShiftRightM(uint_fast8_t size_words, const uint32_t* aPtr, u
 | to a 'size_words'-long array of 32-bit elements that concatenate in the
 | platform's normal endian order to form an N-bit integer.
 *----------------------------------------------------------------------------*/
-void softfloat_shortShiftRightJamM(uint_fast8_t, const uint32_t*, uint_fast8_t, uint32_t*);
+void
+ softfloat_shortShiftRightJamM(
+     uint_fast8_t, const uint32_t *, uint_fast8_t, uint32_t * );
 #endif
 
 #ifndef softfloat_shortShiftRightJam160M
@@ -742,7 +825,13 @@ void softfloat_shortShiftRightJamM(uint_fast8_t, const uint32_t*, uint_fast8_t,
 |   The value of 'dist' can be arbitrarily large.  In particular, if 'dist' is
 | greater than N, the stored result will be 0.
 *----------------------------------------------------------------------------*/
-void softfloat_shiftRightM(uint_fast8_t size_words, const uint32_t* aPtr, uint32_t dist, uint32_t* zPtr);
+void
+ softfloat_shiftRightM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     uint32_t dist,
+     uint32_t *zPtr
+ );
 #endif
 
 #ifndef softfloat_shiftRight96M
@@ -767,7 +856,13 @@ void softfloat_shiftRightM(uint_fast8_t size_words, const uint32_t* aPtr, uint32
 | is greater than N, the stored result will be either 0 or 1, depending on
 | whether the original N bits are all zeros.
 *----------------------------------------------------------------------------*/
-void softfloat_shiftRightJamM(uint_fast8_t size_words, const uint32_t* aPtr, uint32_t dist, uint32_t* zPtr);
+void
+ softfloat_shiftRightJamM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     uint32_t dist,
+     uint32_t *zPtr
+ );
 #endif
 
 #ifndef softfloat_shiftRightJam96M
@@ -803,7 +898,13 @@ void softfloat_shiftRightJamM(uint_fast8_t size_words, const uint32_t* aPtr, uin
 | elements that concatenate in the platform's normal endian order to form an
 | N-bit integer.
 *----------------------------------------------------------------------------*/
-void softfloat_addM(uint_fast8_t size_words, const uint32_t* aPtr, const uint32_t* bPtr, uint32_t* zPtr);
+void
+ softfloat_addM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     const uint32_t *bPtr,
+     uint32_t *zPtr
+ );
 #endif
 
 #ifndef softfloat_add96M
@@ -839,7 +940,14 @@ void softfloat_addM(uint_fast8_t size_words, const uint32_t* aPtr, const uint32_
 | points to a 'size_words'-long array of 32-bit elements that concatenate in
 | the platform's normal endian order to form an N-bit integer.
 *----------------------------------------------------------------------------*/
-uint_fast8_t softfloat_addCarryM(uint_fast8_t size_words, const uint32_t* aPtr, const uint32_t* bPtr, uint_fast8_t carry, uint32_t* zPtr);
+uint_fast8_t
+ softfloat_addCarryM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     const uint32_t *bPtr,
+     uint_fast8_t carry,
+     uint32_t *zPtr
+ );
 #endif
 
 #ifndef softfloat_addComplCarryM
@@ -848,8 +956,14 @@ uint_fast8_t softfloat_addCarryM(uint_fast8_t size_words, const uint32_t* aPtr,
 | the value of the unsigned integer pointed to by 'bPtr' is bit-wise completed
 | before the addition.
 *----------------------------------------------------------------------------*/
-uint_fast8_t softfloat_addComplCarryM(uint_fast8_t size_words, const uint32_t* aPtr, const uint32_t* bPtr, uint_fast8_t carry,
+uint_fast8_t
-                                      uint32_t* zPtr);
+ softfloat_addComplCarryM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     const uint32_t *bPtr,
+     uint_fast8_t carry,
+     uint32_t *zPtr
+ );
 #endif
 
 #ifndef softfloat_addComplCarry96M
@@ -938,7 +1052,13 @@ void softfloat_sub1XM(uint_fast8_t size_words, uint32_t* zPtr);
 | array of 32-bit elements that concatenate in the platform's normal endian
 | order to form an N-bit integer.
 *----------------------------------------------------------------------------*/
-void softfloat_subM(uint_fast8_t size_words, const uint32_t* aPtr, const uint32_t* bPtr, uint32_t* zPtr);
+void
+ softfloat_subM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     const uint32_t *bPtr,
+     uint32_t *zPtr
+ );
 #endif
 
 #ifndef softfloat_sub96M
@@ -984,7 +1104,9 @@ void softfloat_mul64To128M(uint64_t a, uint64_t b, uint32_t* zPtr);
 | Argument 'zPtr' points to an array of eight 32-bit elements that concatenate
 | to form a 256-bit integer.
 *----------------------------------------------------------------------------*/
-void softfloat_mul128MTo256M(const uint32_t* aPtr, const uint32_t* bPtr, uint32_t* zPtr);
+void
+ softfloat_mul128MTo256M(
+     const uint32_t *aPtr, const uint32_t *bPtr, uint32_t *zPtr );
 #endif
 
 #ifndef softfloat_remStepMBy32
@@ -997,8 +1119,15 @@ void softfloat_mul128MTo256M(const uint32_t* aPtr, const uint32_t* bPtr, uint32_
 | to a 'size_words'-long array of 32-bit elements that concatenate in the
 | platform's normal endian order to form an N-bit integer.
 *----------------------------------------------------------------------------*/
-void softfloat_remStepMBy32(uint_fast8_t size_words, const uint32_t* remPtr, uint_fast8_t dist, const uint32_t* bPtr, uint32_t q,
+void
-                            uint32_t* zPtr);
+ softfloat_remStepMBy32(
+     uint_fast8_t size_words,
+     const uint32_t *remPtr,
+     uint_fast8_t dist,
+     const uint32_t *bPtr,
+     uint32_t q,
+     uint32_t *zPtr
+ );
 #endif
 
 #ifndef softfloat_remStep96MBy32
@@ -1028,3 +1157,4 @@ void softfloat_remStepMBy32(uint_fast8_t size_words, const uint32_t* remPtr, uin
 #endif
 
 #endif
+

softfloat/source/include/softfloat.h

@@ -34,6 +34,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 =============================================================================*/
 
+
 /*============================================================================
 | Note:  If SoftFloat is made available as a general library for programs to
 | use, it is strongly recommended that a platform-specific version of this
@@ -41,12 +42,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | eliminates all dependencies on compile-time macros.
 *============================================================================*/
 
+
 #ifndef softfloat_h
 #define softfloat_h 1
 
-#include "softfloat_types.h"
 #include <stdbool.h>
 #include <stdint.h>
+#include "softfloat_types.h"
 
 #ifndef THREAD_LOCAL
 #define THREAD_LOCAL
@@ -56,7 +58,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | Software floating-point underflow tininess-detection mode.
 *----------------------------------------------------------------------------*/
 extern THREAD_LOCAL uint_fast8_t softfloat_detectTininess;
-enum { softfloat_tininess_beforeRounding = 0, softfloat_tininess_afterRounding = 1 };
+enum {
+    softfloat_tininess_beforeRounding = 0,
+    softfloat_tininess_afterRounding  = 1
+};
 
 /*----------------------------------------------------------------------------
 | Software floating-point rounding mode.  (Mode "odd" is supported only if
@@ -76,13 +81,13 @@ enum {
 | Software floating-point exception flags.
 *----------------------------------------------------------------------------*/
 extern THREAD_LOCAL uint_fast8_t softfloat_exceptionFlags;
-typedef enum {
+enum {
     softfloat_flag_inexact   =  1,
     softfloat_flag_underflow =  2,
     softfloat_flag_overflow  =  4,
     softfloat_flag_infinite  =  8,
     softfloat_flag_invalid   = 16
-} exceptionFlag_t;
+};
 
 /*----------------------------------------------------------------------------
 | Routine to raise any or all of the software floating-point exception flags.
@@ -164,13 +169,6 @@ bool f16_le_quiet(float16_t, float16_t);
 bool f16_lt_quiet( float16_t, float16_t );
 bool f16_isSignalingNaN( float16_t );
 
-/*----------------------------------------------------------------------------
-| 16-bit (brain float 16) floating-point operations.
-*----------------------------------------------------------------------------*/
-float32_t bf16_to_f32(bfloat16_t);
-bfloat16_t f32_to_bf16(float32_t);
-bool bf16_isSignalingNaN(bfloat16_t);
-
 /*----------------------------------------------------------------------------
 | 32-bit (single-precision) floating-point operations.
 *----------------------------------------------------------------------------*/
@@ -290,7 +288,9 @@ float16_t extF80M_to_f16(const extFloat80_t*);
 float32_t extF80M_to_f32( const extFloat80_t * );
 float64_t extF80M_to_f64( const extFloat80_t * );
 void extF80M_to_f128M( const extFloat80_t *, float128_t * );
-void extF80M_roundToInt(const extFloat80_t*, uint_fast8_t, bool, extFloat80_t*);
+void
+ extF80M_roundToInt(
+     const extFloat80_t *, uint_fast8_t, bool, extFloat80_t * );
 void extF80M_add( const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
 void extF80M_sub( const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
 void extF80M_mul( const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
@@ -353,7 +353,10 @@ void f128M_roundToInt(const float128_t*, uint_fast8_t, bool, float128_t*);
 void f128M_add( const float128_t *, const float128_t *, float128_t * );
 void f128M_sub( const float128_t *, const float128_t *, float128_t * );
 void f128M_mul( const float128_t *, const float128_t *, float128_t * );
-void f128M_mulAdd(const float128_t*, const float128_t*, const float128_t*, float128_t*);
+void
+ f128M_mulAdd(
+     const float128_t *, const float128_t *, const float128_t *, float128_t *
+ );
 void f128M_div( const float128_t *, const float128_t *, float128_t * );
 void f128M_rem( const float128_t *, const float128_t *, float128_t * );
 void f128M_sqrt( const float128_t *, float128_t * );
@@ -366,3 +369,4 @@ bool f128M_lt_quiet(const float128_t*, const float128_t*);
 bool f128M_isSignalingNaN( const float128_t * );
 
 #endif
+

softfloat/source/include/softfloat_types.h

@@ -47,21 +47,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | the types below may, if desired, be defined as aliases for the native types
 | (typically 'float' and 'double', and possibly 'long double').
 *----------------------------------------------------------------------------*/
-typedef struct {
+typedef struct { uint16_t v; } float16_t;
-    uint16_t v;
+typedef struct { uint32_t v; } float32_t;
-} float16_t;
+typedef struct { uint64_t v; } float64_t;
-typedef struct {
+typedef struct { uint64_t v[2]; } float128_t;
-    uint16_t v;
-} bfloat16_t;
-typedef struct {
-    uint32_t v;
-} float32_t;
-typedef struct {
-    uint64_t v;
-} float64_t;
-typedef struct {
-    uint64_t v[2];
-} float128_t;
 
 /*----------------------------------------------------------------------------
 | The format of an 80-bit extended floating-point number in memory.  This
@@ -69,15 +58,9 @@ typedef struct {
 | named 'signif'.
 *----------------------------------------------------------------------------*/
 #ifdef LITTLEENDIAN
-struct extFloat80M {
+struct extFloat80M { uint64_t signif; uint16_t signExp; };
-    uint64_t signif;
-    uint16_t signExp;
-};
 #else
-struct extFloat80M {
+struct extFloat80M { uint16_t signExp; uint64_t signif; };
-    uint16_t signExp;
-    uint64_t signif;
-};
 #endif
 
 /*----------------------------------------------------------------------------
@@ -95,3 +78,4 @@ struct extFloat80M {
 typedef struct extFloat80M extFloat80_t;
 
 #endif
+

softfloat/source/s_mulAddF32.c

@@ -221,3 +221,4 @@ float32_t
     return uZ.f;
 
 }
+

softfloat/source/s_normSubnormalBF16Sig.c

@@ -1,52 +0,0 @@
-
-/*============================================================================
-
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
-
-Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
-California.  All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
-
- 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
-    specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-=============================================================================*/
-
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-
-struct exp8_sig16 softfloat_normSubnormalBF16Sig( uint_fast16_t sig )
-{
-    int_fast8_t shiftDist;
-    struct exp8_sig16 z;
-
-    shiftDist = softfloat_countLeadingZeros16( sig ) - 8;
-    z.exp = 1 - shiftDist;
-    z.sig = sig<<shiftDist;
-    return z;
-
-}
-

softfloat/source/s_roundPackToBF16.c

@@ -1,114 +0,0 @@
-
-/*============================================================================
-
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
-
-Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
-California.  All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
-
- 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
-    specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-=============================================================================*/
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "softfloat.h"
-
-/** sig last significant bit is sig[7], the 7 LSBs will be used for rounding */
-bfloat16_t
- softfloat_roundPackToBF16( bool sign, int_fast16_t exp, uint_fast16_t sig )
-{
-    uint_fast8_t roundingMode;
-    bool roundNearEven;
-    uint_fast8_t roundIncrement, roundBits;
-    bool isTiny;
-    uint_fast16_t uiZ;
-    union ui16_bf16 uZ;
-
-    /*------------------------------------------------------------------------
-    *------------------------------------------------------------------------*/
-    roundingMode = softfloat_roundingMode;
-    roundNearEven = (roundingMode == softfloat_round_near_even);
-    roundIncrement = 0x40;
-    if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) {
-        roundIncrement =
-            (roundingMode
-                 == (sign ? softfloat_round_min : softfloat_round_max))
-                ? 0x7F
-                : 0;
-    }
-    roundBits = sig & 0x7F;
-    /*------------------------------------------------------------------------
-    *------------------------------------------------------------------------*/
-    if ( 0xFD <= (unsigned int) exp ) {
-        if ( exp < 0 ) {
-            /*----------------------------------------------------------------
-            *----------------------------------------------------------------*/
-            isTiny =
-                (softfloat_detectTininess == softfloat_tininess_beforeRounding)
-                    || (exp < -1) || (sig + roundIncrement < 0x8000);
-            sig = softfloat_shiftRightJam32( sig, -exp );
-            exp = 0;
-            roundBits = sig & 0x7F;
-            if ( isTiny && roundBits ) {
-                softfloat_raiseFlags( softfloat_flag_underflow );
-            }
-        } else if ( (0xFD < exp) || (0x8000 <= sig + roundIncrement) ) {
-            /*----------------------------------------------------------------
-            *----------------------------------------------------------------*/
-            softfloat_raiseFlags(
-                softfloat_flag_overflow | softfloat_flag_inexact );
-            uiZ = packToBF16UI( sign, 0xFF, 0 ) - ! roundIncrement;
-            goto uiZ;
-        }
-    }
-    /*------------------------------------------------------------------------
-    *------------------------------------------------------------------------*/
-    sig = (sig + roundIncrement)>>7;
-    if ( roundBits ) {
-        softfloat_exceptionFlags |= softfloat_flag_inexact;
-#ifdef SOFTFLOAT_ROUND_ODD
-        if ( roundingMode == softfloat_round_odd ) {
-            sig |= 1;
-            goto packReturn;
-        }
-#endif
-    }
-    sig &= ~(uint_fast16_t) (! (roundBits ^ 0x40) & roundNearEven);
-    if ( ! sig ) exp = 0;
-    /*------------------------------------------------------------------------
-    *------------------------------------------------------------------------*/
- packReturn:
-    uiZ = packToBF16UI( sign, exp, sig );
- uiZ:
-    uZ.ui = uiZ;
-    return uZ.f;
-
-}
-

src-gen/.gitignore

@@ -1,3 +1,2 @@
 /iss
 /vm
-/sysc

src/iss/arch/hwl.h

@@ -35,7 +35,6 @@
 #ifndef _RISCV_HART_M_P_HWL_H
 #define _RISCV_HART_M_P_HWL_H
 
-#include "riscv_hart_common.h"
 #include <iss/vm_types.h>
 
 namespace iss {
@@ -47,17 +46,17 @@ public:
     using this_class = hwl<BASE>;
     using reg_t = typename BASE::reg_t;
 
-    hwl(feature_config cfg = feature_config{});
+    hwl();
     virtual ~hwl() = default;
 
 protected:
-    iss::status read_custom_csr(unsigned addr, reg_t& val) override;
+    iss::status read_custom_csr_reg(unsigned addr, reg_t &val) override;
-    iss::status write_custom_csr(unsigned addr, reg_t val) override;
+    iss::status write_custom_csr_reg(unsigned addr, reg_t val) override;
 };
 
+
 template<typename BASE>
-inline hwl<BASE>::hwl(feature_config cfg)
+inline hwl<BASE>::hwl() {
-: BASE(cfg) {
     for (unsigned addr = 0x800; addr < 0x803; ++addr){
         this->register_custom_csr_rd(addr);
         this->register_custom_csr_wr(addr);
@@ -68,50 +67,28 @@ inline hwl<BASE>::hwl(feature_config cfg)
     }
 }
 
-template <typename BASE> inline iss::status iss::arch::hwl<BASE>::read_custom_csr(unsigned addr, reg_t& val) {
+template<typename BASE>
+inline iss::status iss::arch::hwl<BASE>::read_custom_csr_reg(unsigned addr, reg_t &val) {
     switch(addr){
-    case 0x800:
+    case 0x800: val = this->reg.lpstart0; break;
-        val = this->reg.lpstart0;
+    case 0x801: val = this->reg.lpend0;   break;
-        break;
+    case 0x802: val = this->reg.lpcount0; break;
-    case 0x801:
+    case 0x804: val = this->reg.lpstart1; break;
-        val = this->reg.lpend0;
+    case 0x805: val = this->reg.lpend1;   break;
-        break;
+    case 0x806: val = this->reg.lpcount1; break;
-    case 0x802:
-        val = this->reg.lpcount0;
-        break;
-    case 0x804:
-        val = this->reg.lpstart1;
-        break;
-    case 0x805:
-        val = this->reg.lpend1;
-        break;
-    case 0x806:
-        val = this->reg.lpcount1;
-        break;
     }
     return iss::Ok;
 }
 
-template <typename BASE> inline iss::status iss::arch::hwl<BASE>::write_custom_csr(unsigned addr, reg_t val) {
+template<typename BASE>
+inline iss::status iss::arch::hwl<BASE>::write_custom_csr_reg(unsigned addr, reg_t val) {
     switch(addr){
-    case 0x800:
+    case 0x800: this->reg.lpstart0 = val; break;
-        this->reg.lpstart0 = val;
+    case 0x801: this->reg.lpend0   = val; break;
-        break;
+    case 0x802: this->reg.lpcount0 = val; break;
-    case 0x801:
+    case 0x804: this->reg.lpstart1 = val; break;
-        this->reg.lpend0 = val;
+    case 0x805: this->reg.lpend1   = val; break;
-        break;
+    case 0x806: this->reg.lpcount1 = val; break;
-    case 0x802:
-        this->reg.lpcount0 = val;
-        break;
-    case 0x804:
-        this->reg.lpstart1 = val;
-        break;
-    case 0x805:
-        this->reg.lpend1 = val;
-        break;
-    case 0x806:
-        this->reg.lpcount1 = val;
-        break;
     }
     return iss::Ok;
 }
@@ -119,4 +96,5 @@ template <typename BASE> inline iss::status iss::arch::hwl<BASE>::write_custom_c
 } // namespace arch
 } // namespace iss
 
+
 #endif /* _RISCV_HART_M_P_H */

src/iss/arch/riscv_hart_common.h

@@ -35,22 +35,8 @@
 #ifndef _RISCV_HART_COMMON
 #define _RISCV_HART_COMMON
 
+#include "iss/arch_if.h"
 #include <cstdint>
-#include <elfio/elfio.hpp>
-#include <fmt/format.h>
-#include <iss/arch_if.h>
-#include <iss/log_categories.h>
-#include <string>
-#include <unordered_map>
-#include <util/logging.h>
-
-#if defined(__GNUC__)
-#define likely(x) ::__builtin_expect(!!(x), 1)
-#define unlikely(x) ::__builtin_expect(!!(x), 0)
-#else
-#define likely(x) x
-#define unlikely(x) x
-#endif
 
 namespace iss {
 namespace arch {
@@ -189,6 +175,7 @@ enum riscv_csr {
     dscratch1 = 0x7B3
 };
 
+
 enum {
     PGSHIFT = 12,
     PTE_PPN_SHIFT = 10,
@@ -239,8 +226,6 @@ struct feature_config {
     unsigned clic_num_trigger{0};
     uint64_t tcm_base{0x10000000};
     uint64_t tcm_size{0x8000};
-    uint64_t io_address{0xf0000000};
-    uint64_t io_addr_mask{0xf0000000};
 };
 
 class trap_load_access_fault : public trap_access {
@@ -310,63 +295,8 @@ inline void write_reg_uint32(uint64_t offs, uint32_t& reg, const uint8_t* const
     break;
     }
 }
-struct riscv_hart_common {
-    riscv_hart_common(){};
-    ~riscv_hart_common(){};
-    std::unordered_map<std::string, uint64_t> symbol_table;
 
-    std::unordered_map<std::string, uint64_t> get_sym_table(std::string name) {
-        if(!symbol_table.empty())
-            return symbol_table;
-        FILE* fp = fopen(name.c_str(), "r");
-        if(fp) {
-            std::array<char, 5> buf;
-            auto n = fread(buf.data(), 1, 4, fp);
-            fclose(fp);
-            if(n != 4)
-                throw std::runtime_error("input file has insufficient size");
-            buf[4] = 0;
-            if(strcmp(buf.data() + 1, "ELF") == 0) {
-                // Create elfio reader
-                ELFIO::elfio reader;
-                // Load ELF data
-                if(!reader.load(name))
-                    throw std::runtime_error("could not process elf file");
-                // check elf properties
-                if(reader.get_type() != ET_EXEC)
-                    throw std::runtime_error("wrong elf type in file");
-                if(reader.get_machine() != EM_RISCV)
-                    throw std::runtime_error("wrong elf machine in file");
-                const auto sym_sec = reader.sections[".symtab"];
-                if(SHT_SYMTAB == sym_sec->get_type() || SHT_DYNSYM == sym_sec->get_type()) {
-                    ELFIO::symbol_section_accessor symbols(reader, sym_sec);
-                    auto sym_no = symbols.get_symbols_num();
-                    std::string name;
-                    ELFIO::Elf64_Addr value = 0;
-                    ELFIO::Elf_Xword size = 0;
-                    unsigned char bind = 0;
-                    unsigned char type = 0;
-                    ELFIO::Elf_Half section = 0;
-                    unsigned char other = 0;
-                    for(auto i = 0U; i < sym_no; ++i) {
-                        symbols.get_symbol(i, name, value, size, bind, type, section, other);
-                        if(name != "") {
-                            this->symbol_table[name] = value;
-#ifndef NDEBUG
-                            CPPLOG(DEBUG) << "Found Symbol " << name;
-#endif
 }
 }
-                }
-                return symbol_table;
-            }
-            throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file", name));
-        } else
-            throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name));
-    };
-};
-
-} // namespace arch
-} // namespace iss
 
 #endif

src/iss/arch/riscv_hart_msu_vp.h

@@ -35,34 +35,38 @@
 #ifndef _RISCV_HART_MSU_VP_H
 #define _RISCV_HART_MSU_VP_H
 
+#include "riscv_hart_common.h"
 #include "iss/arch/traits.h"
 #include "iss/instrumentation_if.h"
 #include "iss/log_categories.h"
 #include "iss/vm_if.h"
-#include "iss/vm_types.h"
-#include "riscv_hart_common.h"
-#include <stdexcept>
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
 #endif
 #include <array>
 #include <elfio/elfio.hpp>
 #include <fmt/format.h>
-#include <functional>
 #include <iomanip>
 #include <sstream>
 #include <type_traits>
 #include <unordered_map>
+#include <functional>
 #include <util/bit_field.h>
 #include <util/ities.h>
 #include <util/sparse_array.h>
 
-#include <iss/semihosting/semihosting.h>
+#if defined(__GNUC__)
+#define likely(x) __builtin_expect(!!(x), 1)
+#define unlikely(x) __builtin_expect(!!(x), 0)
+#else
+#define likely(x) x
+#define unlikely(x) x
+#endif
 
 namespace iss {
 namespace arch {
 
-template <typename BASE> class riscv_hart_msu_vp : public BASE, public riscv_hart_common {
+template <typename BASE> class riscv_hart_msu_vp : public BASE {
 protected:
     const std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
     const std::array<const char *, 16> trap_str = {{""
@@ -82,11 +86,10 @@ protected:
                                               "Load page fault",                // d
                                               "Reserved",                       // e
                                               "Store/AMO page fault"}};
-    const std::array<const char*, 12> irq_str = {{"User software interrupt", "Supervisor software interrupt", "Reserved",
+    const std::array<const char *, 12> irq_str = {
-                                                  "Machine software interrupt", "User timer interrupt", "Supervisor timer interrupt",
+        {"User software interrupt", "Supervisor software interrupt", "Reserved", "Machine software interrupt",
-                                                  "Reserved", "Machine timer interrupt", "User external interrupt",
+         "User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt",
-                                                  "Supervisor external interrupt", "Reserved", "Machine external interrupt"}};
+         "User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}};
-
 public:
     using core = BASE;
     using this_class = riscv_hart_msu_vp<BASE>;
@@ -104,8 +107,7 @@ public:
     template <typename T> class hart_state<T, typename std::enable_if<std::is_same<T, uint32_t>::value>::type> {
     public:
         BEGIN_BF_DECL(mstatus_t, T);
-        // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR
+        // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11)))
-        // XS==11)))
         BF_FIELD(SD, 31, 1);
         // Trap SRET
         BF_FIELD(TSR, 22, 1);
@@ -119,8 +121,7 @@ public:
         BF_FIELD(SUM, 18, 1);
         // Modify PRiVilege
         BF_FIELD(MPRV, 17, 1);
-        // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None
+        // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None dirty, some clean/Some dirty
-        // dirty, some clean/Some dirty
         BF_FIELD(XS, 15, 2);
         // floating-point unit status Off/Initial/Clean/Dirty
         BF_FIELD(FS, 13, 2);
@@ -161,27 +162,20 @@ public:
             return priv_lvl == PRIV_U ? 0x80000011UL : priv_lvl == PRIV_S ? 0x800de133UL : 0x807ff9ddUL;
 #else
             switch (priv_lvl) {
-            case PRIV_U:
+            case PRIV_U: return 0x80000011UL; // 0b1000 0000 0000 0000 0000 0000 0001 0001
-                return 0x80000011UL; // 0b1000 0000 0000 0000 0000 0000 0001 0001
+            case PRIV_S: return 0x800de133UL; // 0b1000 0000 0000 1101 1110 0001 0011 0011
-            case PRIV_S:
+            default:     return 0x807ff9ddUL; // 0b1000 0000 0111 1111 1111 1001 1011 1011
-                return 0x800de133UL; // 0b1000 0000 0000 1101 1110 0001 0011 0011
-            default:
-                return 0x807ff9ddUL; // 0b1000 0000 0111 1111 1111 1001 1011 1011
             }
 #endif
         }
 
         static inline vm_info decode_vm_info(uint32_t state, T sptbr) {
-            if(state == PRIV_M)
+            if (state == PRIV_M) return {0, 0, 0, 0};
-                return {0, 0, 0, 0};
             if (state <= PRIV_S)
                 switch (bit_sub<31, 1>(sptbr)) {
-                case 0:
+                case 0:  return {0, 0, 0, 0}; // off
-                    return {0, 0, 0, 0}; // off
+                case 1:  return {2, 10, 4, bit_sub<0, 22>(sptbr) << PGSHIFT}; // SV32
-                case 1:
+                default: abort();
-                    return {2, 10, 4, bit_sub<0, 22>(sptbr) << PGSHIFT}; // SV32
-                default:
-                    abort();
                 }
             abort();
             return {0, 0, 0, 0}; // dummy
@@ -191,8 +185,7 @@ public:
     template <typename T> class hart_state<T, typename std::enable_if<std::is_same<T, uint64_t>::value>::type> {
     public:
         BEGIN_BF_DECL(mstatus_t, T);
-        // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR
+        // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11)))
-        // XS==11)))
         BF_FIELD(SD, 63, 1);
         // value of XLEN for S-mode
         BF_FIELD(SXL, 34, 2);
@@ -210,8 +203,7 @@ public:
         BF_FIELD(SUM, 18, 1);
         // Modify PRiVilege
         BF_FIELD(MPRV, 17, 1);
-        // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None
+        // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None dirty, some clean/Some dirty
-        // dirty, some clean/Some dirty
         BF_FIELD(XS, 15, 2);
         // floating-point unit status Off/Initial/Clean/Dirty
         BF_FIELD(FS, 13, 2);
@@ -257,36 +249,23 @@ public:
         static constexpr T get_mask(unsigned priv_lvl) {
             uint64_t ret;
             switch (priv_lvl) {
-            case PRIV_U:
+            case PRIV_U: ret = 0x8000000f00000011ULL;break; // 0b1...0 1111 0000 0000 0111 1111 1111 1001 1011 1011
-                ret = 0x8000000f00000011ULL;
+            case PRIV_S: ret = 0x8000000f000de133ULL;break; // 0b1...0 0011 0000 0000 0000 1101 1110 0001 0011 0011
-                break; // 0b1...0 1111 0000 0000 0111 1111 1111 1001 1011 1011
+            default:     ret = 0x8000000f007ff9ddULL;break; // 0b1...0 1111 0000 0000 0111 1111 1111 1001 1011 1011
-            case PRIV_S:
-                ret = 0x8000000f000de133ULL;
-                break; // 0b1...0 0011 0000 0000 0000 1101 1110 0001 0011 0011
-            default:
-                ret = 0x8000000f007ff9ddULL;
-                break; // 0b1...0 1111 0000 0000 0111 1111 1111 1001 1011 1011
             }
             return ret;
         }
 
         static inline vm_info decode_vm_info(uint32_t state, T sptbr) {
-            if(state == PRIV_M)
+            if (state == PRIV_M) return {0, 0, 0, 0};
-                return {0, 0, 0, 0};
             if (state <= PRIV_S)
                 switch (bit_sub<60, 4>(sptbr)) {
-                case 0:
+                case 0:  return {0, 0, 0, 0}; // off
-                    return {0, 0, 0, 0}; // off
+                case 8:  return {3, 9, 8, bit_sub<0, 44>(sptbr) << PGSHIFT};// SV39
-                case 8:
+                case 9:  return {4, 9, 8, bit_sub<0, 44>(sptbr) << PGSHIFT};// SV48
-                    return {3, 9, 8, bit_sub<0, 44>(sptbr) << PGSHIFT}; // SV39
+                case 10: return {5, 9, 8, bit_sub<0, 44>(sptbr) << PGSHIFT};// SV57
-                case 9:
+                case 11: return {6, 9, 8, bit_sub<0, 44>(sptbr) << PGSHIFT};// SV64
-                    return {4, 9, 8, bit_sub<0, 44>(sptbr) << PGSHIFT}; // SV48
+                default: abort();
-                case 10:
-                    return {5, 9, 8, bit_sub<0, 44>(sptbr) << PGSHIFT}; // SV57
-                case 11:
-                    return {6, 9, 8, bit_sub<0, 44>(sptbr) << PGSHIFT}; // SV64
-                default:
-                    abort();
                 }
             abort();
             return {0, 0, 0, 0}; // dummy
@@ -307,7 +286,7 @@ public:
         return m[mode];
     }
 
-    riscv_hart_msu_vp(feature_config cfg = feature_config{});
+    riscv_hart_msu_vp();
     virtual ~riscv_hart_msu_vp() = default;
 
     void reset(uint64_t address) override;
@@ -316,10 +295,10 @@ public:
 
     phys_addr_t virt2phys(const iss::addr_t &addr) override;
 
-    iss::status read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length,
+    iss::status read(const address_type type, const access_type access, const uint32_t space,
-                     uint8_t* const data) override;
+            const uint64_t addr, const unsigned length, uint8_t *const data) override;
-    iss::status write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length,
+    iss::status write(const address_type type, const access_type access, const uint32_t space,
-                      const uint8_t* const data) override;
+            const uint64_t addr, const unsigned length, const uint8_t *const data) override;
 
     uint64_t enter_trap(uint64_t flags) override { return riscv_hart_msu_vp::enter_trap(flags, fault_data, fault_data); }
     uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
@@ -327,18 +306,19 @@ public:
     void wait_until(uint64_t flags) override;
 
     void disass_output(uint64_t pc, const std::string instr) override {
-        CLOG(INFO, disass) << fmt::format("0x{:016x}    {:40} [p:{};s:0x{:x};c:{}]", pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus,
+        CLOG(INFO, disass) << fmt::format("0x{:016x}    {:40} [p:{};s:0x{:x};c:{}]",
-                                          this->reg.icount + cycle_offset);
+                pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus, this->reg.icount + cycle_offset);
     };
 
     iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
 
-    void set_csr(unsigned addr, reg_t val) { csr[addr & csr.page_addr_mask] = val; }
+    void set_csr(unsigned addr, reg_t val){
-
+        csr[addr & csr.page_addr_mask] = val;
-    void set_irq_num(unsigned i) { mcause_max_irq = 1 << util::ilog2(i); }
+    }
-
-    void set_semihosting_callback(std::function<void(arch_if*, reg_t, reg_t)>& cb) { semihosting_cb = cb; };
 
+    void set_irq_num(unsigned i) {
+        mcause_max_irq=1<<util::ilog2(i);
+    }
 protected:
     struct riscv_instrumentation_if : public iss::instrumentation_if {
 
@@ -351,9 +331,9 @@ protected:
          */
         const std::string core_type_name() const override { return traits<BASE>::core_type; }
 
-        uint64_t get_pc() override { return arch.reg.PC; }
+        uint64_t get_pc() override { return arch.reg.PC; };
 
-        uint64_t get_next_pc() override { return arch.reg.NEXT_PC; }
+        uint64_t get_next_pc() override { return arch.reg.NEXT_PC; };
 
         uint64_t get_instr_word() override { return arch.reg.instruction; }
 
@@ -363,15 +343,9 @@ protected:
 
         uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }
 
-        void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; }
+        void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
 
-        bool is_branch_taken() override { return arch.reg.last_branch; }
+        bool is_branch_taken() override { return arch.reg.last_branch; };
-
-        unsigned get_reg_num() override { return traits<BASE>::NUM_REGS; }
-
-        unsigned get_reg_size(unsigned num) override { return traits<BASE>::reg_bit_widths[num]; }
-
-        std::unordered_map<std::string, uint64_t> get_symbol_table(std::string name) override { return arch.get_sym_table(name); }
 
         riscv_hart_msu_vp<BASE> &arch;
     };
@@ -395,11 +369,9 @@ protected:
     std::array<vm_info, 2> vm;
     uint64_t tohost = tohost_dflt;
     uint64_t fromhost = fromhost_dflt;
-    bool tohost_lower_written = false;
+    unsigned to_host_wr_cnt = 0;
     riscv_instrumentation_if instr_if;
 
-    std::function<void(arch_if*, reg_t, reg_t)> semihosting_cb;
-
     using mem_type = util::sparse_array<uint8_t, 1ULL << 32>;
     using csr_type = util::sparse_array<typename traits<BASE>::reg_t, 1ULL << 12, 12>;
     using csr_page_type = typename csr_type::page_type;
@@ -442,8 +414,12 @@ protected:
     virtual iss::status read_custom_csr_reg(unsigned addr, reg_t &val) {return iss::status::Err;};
     virtual iss::status write_custom_csr_reg(unsigned addr, reg_t val) {return iss::status::Err;};
 
-    void register_custom_csr_rd(unsigned addr) { csr_rd_cb[addr] = &this_class::read_custom_csr_reg; }
+    void register_custom_csr_rd(unsigned addr){
-    void register_custom_csr_wr(unsigned addr) { csr_wr_cb[addr] = &this_class::write_custom_csr_reg; }
+        csr_rd_cb[addr] = &this_class::read_custom_csr_reg;
+    }
+    void register_custom_csr_wr(unsigned addr){
+        csr_wr_cb[addr] = &this_class::write_custom_csr_reg;
+    }
 
     reg_t mhartid_reg{0x0};
 
@@ -454,7 +430,6 @@ template <typename BASE>
 riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
 : state()
 , instr_if(*this) {
-    this->_has_mmu = true;
     // reset values
     csr[misa] = traits<BASE>::MISA_VAL;
     csr[mvendorid] = 0x669;
@@ -482,36 +457,32 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
         //csr_wr_cb[addr] = &this_class::write_csr_reg;
     }
     // common regs
-    const std::array<unsigned, 22> addrs{{misa,  mvendorid, marchid,  mimpid, mepc,     mtvec,   mscratch, mcause,
+    const std::array<unsigned, 22> addrs{{
-                                          mtval, mscratch,  sepc,     stvec,  sscratch, scause,  stval,    sscratch,
+        misa, mvendorid, marchid, mimpid,
-                                          uepc,  utvec,     uscratch, ucause, utval,    uscratch}};
+        mepc, mtvec, mscratch, mcause, mtval, mscratch,
+        sepc, stvec, sscratch, scause, stval, sscratch,
+        uepc, utvec, uscratch, ucause, utval, uscratch
+    }};
     for(auto addr: addrs) {
         csr_rd_cb[addr] = &this_class::read_csr_reg;
         csr_wr_cb[addr] = &this_class::write_csr_reg;
     }
     // special handling & overrides
     csr_rd_cb[time] = &this_class::read_time;
-    if(traits<BASE>::XLEN == 32)
+    if(traits<BASE>::XLEN==32)  csr_rd_cb[timeh] = &this_class::read_time;
-        csr_rd_cb[timeh] = &this_class::read_time;
     csr_rd_cb[cycle] = &this_class::read_cycle;
-    if(traits<BASE>::XLEN == 32)
+    if(traits<BASE>::XLEN==32) csr_rd_cb[cycleh] = &this_class::read_cycle;
-        csr_rd_cb[cycleh] = &this_class::read_cycle;
     csr_rd_cb[instret] = &this_class::read_instret;
-    if(traits<BASE>::XLEN == 32)
+    if(traits<BASE>::XLEN==32) csr_rd_cb[instreth] = &this_class::read_instret;
-        csr_rd_cb[instreth] = &this_class::read_instret;
 
     csr_rd_cb[mcycle] = &this_class::read_cycle;
     csr_wr_cb[mcycle] = &this_class::write_cycle;
-    if(traits<BASE>::XLEN == 32)
+    if(traits<BASE>::XLEN==32) csr_rd_cb[mcycleh] = &this_class::read_cycle;
-        csr_rd_cb[mcycleh] = &this_class::read_cycle;
+    if(traits<BASE>::XLEN==32) csr_wr_cb[mcycleh] = &this_class::write_cycle;
-    if(traits<BASE>::XLEN == 32)
-        csr_wr_cb[mcycleh] = &this_class::write_cycle;
     csr_rd_cb[minstret] = &this_class::read_instret;
     csr_wr_cb[minstret] = &this_class::write_instret;
-    if(traits<BASE>::XLEN == 32)
+    if(traits<BASE>::XLEN==32) csr_rd_cb[minstreth] = &this_class::read_instret;
-        csr_rd_cb[minstreth] = &this_class::read_instret;
+    if(traits<BASE>::XLEN==32) csr_wr_cb[minstreth] = &this_class::write_instret;
-    if(traits<BASE>::XLEN == 32)
-        csr_wr_cb[minstreth] = &this_class::write_instret;
     csr_rd_cb[mstatus] = &this_class::read_status;
     csr_wr_cb[mstatus] = &this_class::write_status;
     csr_wr_cb[mcause] = &this_class::write_cause;
@@ -562,38 +533,35 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_msu_vp<BASE>::load
         std::array<char, 5> buf;
         auto n = fread(buf.data(), 1, 4, fp);
         fclose(fp);
-        if(n != 4)
+        if (n != 4) throw std::runtime_error("input file has insufficient size");
-            throw std::runtime_error("input file has insufficient size");
         buf[4] = 0;
         if (strcmp(buf.data() + 1, "ELF") == 0) {
             // Create elfio reader
             ELFIO::elfio reader;
             // Load ELF data
-            if(!reader.load(name))
+            if (!reader.load(name)) throw std::runtime_error("could not process elf file");
-                throw std::runtime_error("could not process elf file");
             // check elf properties
             if (reader.get_class() != ELFCLASS32)
-                if(sizeof(reg_t) == 4)
+                if (sizeof(reg_t) == 4) throw std::runtime_error("wrong elf class in file");
-                    throw std::runtime_error("wrong elf class in file");
+            if (reader.get_type() != ET_EXEC) throw std::runtime_error("wrong elf type in file");
-            if(reader.get_type() != ET_EXEC)
+            if (reader.get_machine() != EM_RISCV) throw std::runtime_error("wrong elf machine in file");
-                throw std::runtime_error("wrong elf type in file");
-            if(reader.get_machine() != EM_RISCV)
-                throw std::runtime_error("wrong elf machine in file");
             auto entry = reader.get_entry();
             for (const auto pseg : reader.segments) {
                 const auto fsize = pseg->get_file_size(); // 0x42c/0x0
                 const auto seg_data = pseg->get_data();
-                const auto type = pseg->get_type();
+                if (fsize > 0) {
-                if(type == 1 && fsize > 0) {
+                    auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE,
-                    auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM,
+                            traits<BASE>::MEM, pseg->get_physical_address(),
-                                           pseg->get_physical_address(), fsize, reinterpret_cast<const uint8_t* const>(seg_data));
+                            fsize, reinterpret_cast<const uint8_t *const>(seg_data));
                     if (res != iss::Ok)
-                        CPPLOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address();
+                        LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex
+                                   << pseg->get_physical_address();
                 }
             }
             for(const auto sec : reader.sections) {
                 if(sec->get_name() == ".symtab") {
-                    if(SHT_SYMTAB == sec->get_type() || SHT_DYNSYM == sec->get_type()) {
+                    if ( SHT_SYMTAB == sec->get_type() ||
+                            SHT_DYNSYM == sec->get_type() ) {
                         ELFIO::symbol_section_accessor symbols( reader, sec );
                         auto sym_no = symbols.get_symbols_num();
                         std::string   name;
@@ -616,6 +584,7 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_msu_vp<BASE>::load
                     tohost = sec->get_address();
                     fromhost = tohost + 0x40;
                 }
+
             }
             return std::make_pair(entry, true);
         }
@@ -625,15 +594,15 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_msu_vp<BASE>::load
 }
 
 template <typename BASE>
-iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr,
+iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_type access, const uint32_t space,
-                                          const unsigned length, uint8_t* const data) {
+        const uint64_t addr, const unsigned length, uint8_t *const data) {
 #ifndef NDEBUG
     if (access && iss::access_type::DEBUG) {
-        CPPLOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
+        LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
     } else if(access && iss::access_type::FETCH){
-        CPPLOG(TRACEALL) << "fetch of " << length << " bytes  @addr 0x" << std::hex << addr;
+        LOG(TRACEALL) << "fetch of " << length << " bytes  @addr 0x" << std::hex << addr;
     } else {
-        CPPLOG(TRACE) << "read of " << length << " bytes  @addr 0x" << std::hex << addr;
+        LOG(TRACE) << "read of " << length << " bytes  @addr 0x" << std::hex << addr;
    }
 #endif
     try {
@@ -642,8 +611,7 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
             auto alignment = is_fetch(access)? (traits<BASE>::MISA_VAL&0x100? 2 : 4) : length;
             if (unlikely(is_fetch(access) && (addr&(alignment-1)))) {
                 fault_data = addr;
-                if(access && iss::access_type::DEBUG)
+                if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                    throw trap_access(0, addr);
                 this->reg.trap_state = (1 << 31); // issue trap 0
                 return iss::Err;
             }
@@ -664,28 +632,26 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
                         return res;
                     }
                 }
-                auto res = read_mem(BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
+                auto res = type==iss::address_type::PHYSICAL?
-                if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
+                        read_mem( BASE::v2p(phys_addr_t{access, space, addr}), length, data):
+                        read_mem( BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
+                if (unlikely(res != iss::Ok)){
                 	this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
                     fault_data=addr;
                 }
                 return res;
             } catch (trap_access &ta) {
-                if((access & access_type::DEBUG) == 0) {
+                this->reg.trap_state = (1 << 31) | ta.id;
-                    this->reg.trap_state = (1UL << 31) | ta.id;
                 fault_data=ta.addr;
-                }
                 return iss::Err;
             }
         } break;
         case traits<BASE>::CSR: {
-            if(length != sizeof(reg_t))
+            if (length != sizeof(reg_t)) return iss::Err;
-                return iss::Err;
             return read_csr(addr, *reinterpret_cast<reg_t *const>(data));
         } break;
         case traits<BASE>::FENCE: {
-            if((addr + length) > mem.size())
+            if ((addr + length) > mem.size()) return iss::Err;
-                return iss::Err;
             switch (addr) {
             case 2:   // SFENCE:VMA lower
             case 3: { // SFENCE:VMA upper
@@ -712,38 +678,36 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
         }
         return iss::Ok;
     } catch (trap_access &ta) {
-        if((access & access_type::DEBUG) == 0) {
         this->reg.trap_state = (1UL << 31) | ta.id;
         fault_data=ta.addr;
-        }
         return iss::Err;
     }
 }
 
 template <typename BASE>
-iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr,
+iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access_type access, const uint32_t space,
-                                           const unsigned length, const uint8_t* const data) {
+        const uint64_t addr, const unsigned length, const uint8_t *const data) {
 #ifndef NDEBUG
     const char *prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
     switch (length) {
     case 8:
-        CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x"
+        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t *)&data[0] << std::dec
-                      << std::hex << addr;
+                   << ") @addr 0x" << std::hex << addr;
         break;
     case 4:
-        CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x"
+        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t *)&data[0] << std::dec
-                      << std::hex << addr;
+                   << ") @addr 0x" << std::hex << addr;
         break;
     case 2:
-        CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x"
+        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t *)&data[0] << std::dec
-                      << std::hex << addr;
+                   << ") @addr 0x" << std::hex << addr;
         break;
     case 1:
-        CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x"
+        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec
-                      << std::hex << addr;
+                   << ") @addr 0x" << std::hex << addr;
         break;
     default:
-        CPPLOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
+        LOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
     }
 #endif
     try {
@@ -751,12 +715,10 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
         case traits<BASE>::MEM: {
             if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) {
                 fault_data = addr;
-                if(access && iss::access_type::DEBUG)
+                if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                    throw trap_access(0, addr);
                 this->reg.trap_state = (1 << 31); // issue trap 0
                 return iss::Err;
             }
-            phys_addr_t paddr = BASE::v2p(iss::addr_t{access, type, space, addr});
             try {
                 if (unlikely((addr & ~PGMASK) != ((addr + length - 1) & ~PGMASK))) { // we may cross a page boundary
                     vm_info vm = hart_state_type::decode_vm_info(this->reg.PRIV, state.satp);
@@ -769,8 +731,10 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
                         return res;
                     }
                 }
-                auto res = write_mem(paddr, length, data);
+                auto res = type==iss::address_type::PHYSICAL?
-                if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
+                        write_mem(phys_addr_t{access, space, addr}, length, data):
+                        write_mem(BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
+                if (unlikely(res != iss::Ok)) {
                     this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault)
                     fault_data=addr;
                 }
@@ -781,14 +745,14 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
                 return iss::Err;
             }
 
-            if((paddr.val + length) > mem.size())
+            phys_addr_t paddr = BASE::v2p(iss::addr_t{access, type, space, addr});
-                return iss::Err;
+            if ((paddr.val + length) > mem.size()) return iss::Err;
             switch (paddr.val) {
             case 0x10013000: // UART0 base, TXFIFO reg
             case 0x10023000: // UART1 base, TXFIFO reg
                 uart_buf << (char)data[0];
                 if (((char)data[0]) == '\n' || data[0] == 0) {
-                    // CPPLOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
+                    // LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
                     // '"<<uart_buf.str()<<"'";
                     std::cout << uart_buf.str();
                     uart_buf.str("");
@@ -799,8 +763,7 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
                 auto offs = paddr.val & mem.page_addr_mask;
                 std::copy(data, data + length, p.data() + offs);
                 auto &x = *(p.data() + offs + 3);
-                if(x & 0x40)
+                if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1
-                    x |= 0x80; // hfroscrdy = 1 if hfroscen==1
                 return iss::Ok;
             }
             case 0x10008008: { // HFROSC base, pllcfg reg
@@ -811,18 +774,15 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
                 x |= 0x80; // set pll lock upon writing
                 return iss::Ok;
             } break;
-            default: {
+            default: {}
-            }
             }
         } break;
         case traits<BASE>::CSR: {
-            if(length != sizeof(reg_t))
+            if (length != sizeof(reg_t)) return iss::Err;
-                return iss::Err;
             return write_csr(addr, *reinterpret_cast<const reg_t *>(data));
         } break;
         case traits<BASE>::FENCE: {
-            if((addr + length) > mem.size())
+            if ((addr + length) > mem.size()) return iss::Err;
-                return iss::Err;
             switch (addr) {
             case 2:
             case 3: {
@@ -845,17 +805,14 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
         }
         return iss::Ok;
     } catch (trap_access &ta) {
-        if((access & access_type::DEBUG) == 0) {
         this->reg.trap_state = (1UL << 31) | ta.id;
         fault_data=ta.addr;
-        }
         return iss::Err;
     }
 }
 
 template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_csr(unsigned addr, reg_t &val) {
-    if(addr >= csr.size())
+    if (addr >= csr.size()) return iss::Err;
-        return iss::Err;
     auto req_priv_lvl = (addr >> 8) & 0x3;
     if (this->reg.PRIV < req_priv_lvl) // not having required privileges
     	throw illegal_instruction_fault(this->fault_data);
@@ -866,8 +823,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_csr(unsigned
 }
 
 template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_csr(unsigned addr, reg_t val) {
-    if(addr >= csr.size())
+    if (addr >= csr.size()) return iss::Err;
-        return iss::Err;
     auto req_priv_lvl = (addr >> 8) & 0x3;
     if (this->reg.PRIV < req_priv_lvl) // not having required privileges
         throw illegal_instruction_fault(this->fault_data);
@@ -899,8 +855,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_cycle(unsigne
     if (addr == mcycle) {
         val = static_cast<reg_t>(cycle_val);
     } else if (addr == mcycleh) {
-        if(sizeof(typename traits<BASE>::reg_t) != 4)
+        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
-            return iss::Err;
         val = static_cast<reg_t>(cycle_val >> 32);
     }
     return iss::Ok;
@@ -948,8 +903,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_time(unsigned
     if (addr == time) {
         val = static_cast<reg_t>(time_val);
     } else if (addr == timeh) {
-        if(sizeof(typename traits<BASE>::reg_t) != 4)
+        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
-            return iss::Err;
         val = static_cast<reg_t>(time_val >> 32);
     }
     return iss::Ok;
@@ -981,10 +935,8 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_cause(unsign
 
 template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_ie(unsigned addr, reg_t &val) {
     val = csr[mie];
-    if(addr < mie)
+    if (addr < mie) val &= csr[mideleg];
-        val &= csr[mideleg];
+    if (addr < sie) val &= csr[sideleg];
-    if(addr < sie)
-        val &= csr[sideleg];
     return iss::Ok;
 }
 
@@ -1003,10 +955,8 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_ie(unsigned
 
 template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_ip(unsigned addr, reg_t &val) {
     val = csr[mip];
-    if(addr < mip)
+    if (addr < mip) val &= csr[mideleg];
-        val &= csr[mideleg];
+    if (addr < sip) val &= csr[sideleg];
-    if(addr < sip)
-        val &= csr[sideleg];
     return iss::Ok;
 }
 
@@ -1071,7 +1021,8 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_fcsr(unsigne
     return iss::Ok;
 }
 
-template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_mem(phys_addr_t paddr, unsigned length, uint8_t* const data) {
+template <typename BASE>
+iss::status riscv_hart_msu_vp<BASE>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
     switch (paddr.val) {
     default: {
         for(auto offs=0U; offs<length; ++offs) {
@@ -1082,11 +1033,12 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_mem(phys_addr
     return iss::Ok;
 }
 
-template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) {
+template <typename BASE>
+iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
     switch (paddr.val) {
     case 0xFFFF0000: // UART0 base, TXFIFO reg
         if (((char)data[0]) == '\n' || data[0] == 0) {
-            CPPLOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'";
+            LOG(INFO)<<"UART"<<((paddr.val>>12)&0x3)<<" send '"<<uart_buf.str()<<"'";
             uart_buf.str("");
         } else if(((char)data[0]) != '\r')
             uart_buf << (char)data[0];
@@ -1096,43 +1048,42 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_add
         std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
         // tohost handling in case of riscv-test
         if (paddr.access && iss::access_type::FUNC) {
-            auto tohost_upper =
+            auto tohost_upper = (traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4)) ||
-                (traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4)) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
+                                (traits<BASE>::XLEN == 64 && paddr.val == tohost);
-            auto tohost_lower = (traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
+            auto tohost_lower =
+                (traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
             if (tohost_lower || tohost_upper) {
                 uint64_t hostvar = *reinterpret_cast<uint64_t *>(p.data() + (tohost & mem.page_addr_mask));
-                // in case of 32 bit system, two writes to tohost are needed, only evaluate on the second (high) write
+                if (tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) {
-                if(tohost_upper && (tohost_lower || tohost_lower_written)) {
                     switch (hostvar >> 48) {
                     case 0:
                         if (hostvar != 0x1) {
-                            CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
+                            LOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
                                        << "), stopping simulation";
                         } else {
-                            CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
+                            LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
                                       << "), stopping simulation";
                         }
                         this->reg.trap_state=std::numeric_limits<uint32_t>::max();
                         this->interrupt_sim=hostvar;
-#ifndef WITH_TCC
-                        throw(iss::simulation_stopped(hostvar));
-#endif
                         break;
+                        //throw(iss::simulation_stopped(hostvar));
                     case 0x0101: {
                         char c = static_cast<char>(hostvar & 0xff);
                         if (c == '\n' || c == 0) {
-                            CPPLOG(INFO) << "tohost send '" << uart_buf.str() << "'";
+                            LOG(INFO) << "tohost send '" << uart_buf.str() << "'";
                             uart_buf.str("");
                         } else
                             uart_buf << c;
+                        to_host_wr_cnt = 0;
                     } break;
                     default:
                         break;
                     }
-                    tohost_lower_written = false;
                 } else if (tohost_lower)
-                    tohost_lower_written = true;
+                    to_host_wr_cnt++;
-            } else if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
+            } else if ((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) ||
+                       (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
                 uint64_t fhostvar = *reinterpret_cast<uint64_t *>(p.data() + (fromhost & mem.page_addr_mask));
                 *reinterpret_cast<uint64_t *>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
             }
@@ -1181,13 +1132,13 @@ template <typename BASE> void riscv_hart_msu_vp<BASE>::check_interrupt() {
     }
     if (enabled_interrupts != 0) {
         int res = 0;
-        while((enabled_interrupts & 1) == 0)
+        while ((enabled_interrupts & 1) == 0) enabled_interrupts >>= 1, res++;
-            enabled_interrupts >>= 1, res++;
         this->reg.pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id
     }
 }
 
-template <typename BASE> typename riscv_hart_msu_vp<BASE>::phys_addr_t riscv_hart_msu_vp<BASE>::virt2phys(const iss::addr_t& addr) {
+template <typename BASE>
+typename riscv_hart_msu_vp<BASE>::phys_addr_t riscv_hart_msu_vp<BASE>::virt2phys(const iss::addr_t &addr) {
     const auto type = addr.access & iss::access_type::FUNC;
     auto it = ptw.find(addr.val >> PGSHIFT);
     if (it != ptw.end()) {
@@ -1206,8 +1157,8 @@ template <typename BASE> typename riscv_hart_msu_vp<BASE>::phys_addr_t riscv_har
 #endif
     } else {
         uint32_t mode = type != iss::access_type::FETCH && state.mstatus.MPRV ? // MPRV
-                            state.mstatus.MPP
+                            state.mstatus.MPP :
-                                                                              : this->reg.PRIV;
+                            this->reg.PRIV;
 
         const vm_info &vm = this->vm[static_cast<uint16_t>(type) / 2];
 
@@ -1228,10 +1179,9 @@ template <typename BASE> typename riscv_hart_msu_vp<BASE>::phys_addr_t riscv_har
 
             // check that physical address of PTE is legal
             reg_t pte = 0;
-            const uint8_t res = this->read(iss::address_type::PHYSICAL, addr.access, traits<BASE>::MEM, base + idx * vm.ptesize, vm.ptesize,
+            const uint8_t res = this->read(iss::address_type::PHYSICAL, addr.access,
-                                           (uint8_t*)&pte);
+                    traits<BASE>::MEM, base + idx * vm.ptesize, vm.ptesize, (uint8_t *)&pte);
-            if(res != 0)
+            if (res != 0) throw trap_load_access_fault(addr.val);
-                throw trap_load_access_fault(addr.val);
             const reg_t ppn = pte >> PTE_PPN_SHIFT;
 
             if (PTE_TABLE(pte)) { // next level of page table
@@ -1240,9 +1190,10 @@ template <typename BASE> typename riscv_hart_msu_vp<BASE>::phys_addr_t riscv_har
                 break;
             } else if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) {
                 break;
-            } else if(type == (iss::access_type::FETCH          ? !(pte & PTE_X)
+            } else if (type == iss::access_type::FETCH
+                           ? !(pte & PTE_X)
                            : type == iss::access_type::READ ? !(pte & PTE_R) && !(mxr && (pte & PTE_X))
-                                                                : !((pte & PTE_R) && (pte & PTE_W)))) {
+                                                            : !((pte & PTE_R) && (pte & PTE_W))) {
                 break;
             } else if ((ppn & ((reg_t(1) << ptshift) - 1)) != 0) {
                 break;
@@ -1253,8 +1204,7 @@ template <typename BASE> typename riscv_hart_msu_vp<BASE>::phys_addr_t riscv_har
                 *(uint32_t *)ppte |= ad;
 #else
                 // take exception if access or possibly dirty bit is not set.
-                if((pte & ad) != ad)
+                if ((pte & ad) != ad) break;
-                    break;
 #endif
                 // for superpage mappings, make a fake leaf PTE for the TLB's benefit.
                 const reg_t vpn = addr.val >> PGSHIFT;
@@ -1284,12 +1234,10 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t f
     auto cur_priv = this->reg.PRIV;
     // flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
     // calculate and write mcause val
-    if(flags == std::numeric_limits<uint64_t>::max())
+    if(flags==std::numeric_limits<uint64_t>::max()) flags=this->reg.trap_state;
-        flags = this->reg.trap_state;
     auto trap_id = bit_sub<0, 16>(flags);
     auto cause = bit_sub<16, 15>(flags);
-    if(trap_id == 0 && cause == 11)
+    if (trap_id == 0 && cause == 11) cause = 0x8 + cur_priv; // adjust environment call cause
-        cause = 0x8 + cur_priv; // adjust environment call cause
     // calculate effective privilege level
     auto new_priv = PRIV_M;
     if (trap_id == 0) { // exception
@@ -1316,31 +1264,6 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t f
             // csr[dpc] = addr;
             // csr[dcsr] = (csr[dcsr] & ~0x1c3) | (1<<6) | PRIV_M; //FIXME: cause should not be 4 (stepi)
             csr[utval | (new_priv << 8)] = addr;
-            if(semihosting_cb) {
-                // Check for semihosting call
-                phys_addr_t p_addr(access_type::DEBUG_READ, traits<BASE>::MEM, addr - 4);
-                std::array<uint8_t, 8> data;
-                // check for SLLI_X0_X0_0X1F and SRAI_X0_X0_0X07
-                this->read_mem(p_addr, 4, data.data());
-                p_addr.val += 8;
-                this->read_mem(p_addr, 4, data.data() + 4);
-
-                const std::array<uint8_t, 8> ref_data = {0x13, 0x10, 0xf0, 0x01, 0x13, 0x50, 0x70, 0x40};
-                if(data == ref_data) {
-                    this->reg.NEXT_PC = addr + 8;
-
-                    std::array<char, 32> buffer;
-#if defined(_MSC_VER)
-                    sprintf(buffer.data(), "0x%016llx", addr);
-#else
-                    sprintf(buffer.data(), "0x%016lx", addr);
-#endif
-                    CLOG(INFO, disass) << "Semihosting call at address " << buffer.data() << " occurred ";
-
-                    semihosting_callback(this, this->reg.X10 /*a0*/, this->reg.X11 /*a1*/);
-                    return this->reg.NEXT_PC;
-                }
-            }
             break;
         case 4:
         case 6:
@@ -1358,7 +1281,7 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t f
         this->reg.pending_trap = 0;
     }
     size_t adr = ucause | (new_priv << 8);
-    csr[adr] = (trap_id << (traits<BASE>::XLEN - 1)) + cause;
+    csr[adr] = (trap_id << 31) + cause;
     // update mstatus
     // xPP field of mstatus is written with the active privilege mode at the time
     // of the trap; the x PIE field of mstatus
@@ -1390,15 +1313,14 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t f
     // calculate addr// set NEXT_PC to trap addressess to jump to based on MODE
     // bits in mtvec
     this->reg.NEXT_PC = ivec & ~0x3UL;
-    if((ivec & 0x1) == 1 && trap_id != 0)
+    if ((ivec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
-        this->reg.NEXT_PC += 4 * cause;
     std::array<char, 32> buffer;
     sprintf(buffer.data(), "0x%016lx", addr);
     if((flags&0xffffffff) != 0xffffffff)
-        CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '" << (trap_id ? irq_str[cause] : trap_str[cause]) << "' ("
+    CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '"
-                           << cause << ")"
+                       << (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << cause << ")"
-                           << " at address " << buffer.data() << " occurred, changing privilege level from " << lvl[cur_priv] << " to "
+                       << " at address " << buffer.data() << " occurred, changing privilege level from "
-                           << lvl[new_priv];
+                       << lvl[cur_priv] << " to " << lvl[new_priv];
     // reset trap state
     this->reg.PRIV = new_priv;
     this->reg.trap_state = 0;
@@ -1441,7 +1363,8 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::leave_trap(uint64_t f
     }
     // sets the pc to the value stored in the x epc register.
     this->reg.NEXT_PC = csr[uepc | inst_priv << 8];
-    CLOG(INFO, disass) << "Executing xRET , changing privilege level from " << lvl[cur_priv] << " to " << lvl[this->reg.PRIV];
+    CLOG(INFO, disass) << "Executing xRET , changing privilege level from " << lvl[cur_priv] << " to "
+                       << lvl[this->reg.PRIV];
     update_vm_info();
     check_interrupt();
     return this->reg.NEXT_PC;
@@ -1455,7 +1378,7 @@ template <typename BASE> void riscv_hart_msu_vp<BASE>::wait_until(uint64_t flags
         this->fault_data = this->reg.PC;
     }
 }
-} // namespace arch
+}
-} // namespace iss
+}
 
 #endif /* _RISCV_HART_MSU_VP_H */

src/iss/arch/tgc_c.cpp

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2024 MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2020 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -30,8 +30,7 @@
  *
  *******************************************************************************/
 
-// clang-format off
+#include "tgc_c.h"
-#include "tgc5c.h"
 #include "util/ities.h"
 #include <util/logging.h>
 #include <cstdio>
@@ -40,18 +39,18 @@
 
 using namespace iss::arch;
 
-constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc5c>::reg_names;
+constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc_c>::reg_names;
-constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc5c>::reg_aliases;
+constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc_c>::reg_aliases;
-constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc5c>::reg_bit_widths;
+constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths;
-constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc5c>::reg_byte_offsets;
+constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets;
 
-tgc5c::tgc5c()  = default;
+tgc_c::tgc_c()  = default;
 
-tgc5c::~tgc5c() = default;
+tgc_c::~tgc_c() = default;
 
-void tgc5c::reset(uint64_t address) {
+void tgc_c::reset(uint64_t address) {
-    auto base_ptr = reinterpret_cast<traits<tgc5c>::reg_t*>(get_regs_base_ptr());
+    auto base_ptr = reinterpret_cast<traits<tgc_c>::reg_t*>(get_regs_base_ptr());
-    for(size_t i=0; i<traits<tgc5c>::NUM_REGS; ++i)
+    for(size_t i=0; i<traits<tgc_c>::NUM_REGS; ++i)
         *(base_ptr+i)=0;
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
@@ -60,11 +59,11 @@ void tgc5c::reset(uint64_t address) {
     reg.icount=0;
 }
 
-uint8_t *tgc5c::get_regs_base_ptr() {
+uint8_t *tgc_c::get_regs_base_ptr() {
 	return reinterpret_cast<uint8_t*>(&reg);
 }
 
-tgc5c::phys_addr_t tgc5c::virt2phys(const iss::addr_t &addr) {
+tgc_c::phys_addr_t tgc_c::virt2phys(const iss::addr_t &pc) {
-    return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc5c>::addr_mask);
+    return phys_addr_t(pc); // change logical address to physical address
 }
-// clang-format on
+

src/iss/arch/tgc_c.h

@@ -0,0 +1,270 @@
+/*******************************************************************************
+ * Copyright (C) 2017 - 2021 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+#ifndef _TGC_C_H_
+#define _TGC_C_H_
+
+#include <array>
+#include <iss/arch/traits.h>
+#include <iss/arch_if.h>
+#include <iss/vm_if.h>
+
+namespace iss {
+namespace arch {
+
+struct tgc_c;
+
+template <> struct traits<tgc_c> {
+
+    constexpr static char const* const core_type = "TGC_C";
+    
+    static constexpr std::array<const char*, 36> reg_names{
+        {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV", "DPC"}};
+ 
+    static constexpr std::array<const char*, 36> reg_aliases{
+        {"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV", "DPC"}};
+
+    enum constants {MISA_VAL=1073746180, MARCHID_VAL=2147483651, XLEN=32, INSTR_ALIGNMENT=2, RFS=32, fence=0, fencei=1, fencevmal=2, fencevmau=3, CSR_SIZE=4096, MUL_LEN=64};
+
+    constexpr static unsigned FP_REGS_SIZE = 0;
+
+    enum reg_e {
+        X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, DPC, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
+    };
+
+    using reg_t = uint32_t;
+
+    using addr_t = uint32_t;
+
+    using code_word_t = uint32_t; //TODO: check removal
+
+    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
+
+    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
+
+    static constexpr std::array<const uint32_t, 43> reg_bit_widths{
+        {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,32,64,64,64,32,32}};
+
+    static constexpr std::array<const uint32_t, 43> reg_byte_offsets{
+        {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,149,157,165,173,177}};
+
+    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
+
+    enum sreg_flag_e { FLAGS };
+
+    enum mem_type_e { MEM, FENCE, RES, CSR };
+    
+    enum class opcode_e {
+        LUI = 0,
+        AUIPC = 1,
+        JAL = 2,
+        JALR = 3,
+        BEQ = 4,
+        BNE = 5,
+        BLT = 6,
+        BGE = 7,
+        BLTU = 8,
+        BGEU = 9,
+        LB = 10,
+        LH = 11,
+        LW = 12,
+        LBU = 13,
+        LHU = 14,
+        SB = 15,
+        SH = 16,
+        SW = 17,
+        ADDI = 18,
+        SLTI = 19,
+        SLTIU = 20,
+        XORI = 21,
+        ORI = 22,
+        ANDI = 23,
+        SLLI = 24,
+        SRLI = 25,
+        SRAI = 26,
+        ADD = 27,
+        SUB = 28,
+        SLL = 29,
+        SLT = 30,
+        SLTU = 31,
+        XOR = 32,
+        SRL = 33,
+        SRA = 34,
+        OR = 35,
+        AND = 36,
+        FENCE = 37,
+        ECALL = 38,
+        EBREAK = 39,
+        MRET = 40,
+        WFI = 41,
+        CSRRW = 42,
+        CSRRS = 43,
+        CSRRC = 44,
+        CSRRWI = 45,
+        CSRRSI = 46,
+        CSRRCI = 47,
+        FENCE_I = 48,
+        MUL = 49,
+        MULH = 50,
+        MULHSU = 51,
+        MULHU = 52,
+        DIV = 53,
+        DIVU = 54,
+        REM = 55,
+        REMU = 56,
+        CADDI4SPN = 57,
+        CLW = 58,
+        CSW = 59,
+        CADDI = 60,
+        CNOP = 61,
+        CJAL = 62,
+        CLI = 63,
+        CLUI = 64,
+        CADDI16SP = 65,
+        __reserved_clui = 66,
+        CSRLI = 67,
+        CSRAI = 68,
+        CANDI = 69,
+        CSUB = 70,
+        CXOR = 71,
+        COR = 72,
+        CAND = 73,
+        CJ = 74,
+        CBEQZ = 75,
+        CBNEZ = 76,
+        CSLLI = 77,
+        CLWSP = 78,
+        CMV = 79,
+        CJR = 80,
+        __reserved_cmv = 81,
+        CADD = 82,
+        CJALR = 83,
+        CEBREAK = 84,
+        CSWSP = 85,
+        DII = 86,
+        MAX_OPCODE
+    };
+};
+
+struct tgc_c: public arch_if {
+
+    using virt_addr_t = typename traits<tgc_c>::virt_addr_t;
+    using phys_addr_t = typename traits<tgc_c>::phys_addr_t;
+    using reg_t =  typename traits<tgc_c>::reg_t;
+    using addr_t = typename traits<tgc_c>::addr_t;
+
+    tgc_c();
+    ~tgc_c();
+
+    void reset(uint64_t address=0) override;
+
+    uint8_t* get_regs_base_ptr() override;
+
+    inline uint64_t get_icount() { return reg.icount; }
+
+    inline bool should_stop() { return interrupt_sim; }
+
+    inline uint64_t stop_code() { return interrupt_sim; }
+
+    inline phys_addr_t v2p(const iss::addr_t& addr){
+        if (addr.space != traits<tgc_c>::MEM || addr.type == iss::address_type::PHYSICAL ||
+                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
+            return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc_c>::addr_mask);
+        } else
+            return virt2phys(addr);
+    }
+
+    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
+
+    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
+
+    inline uint32_t get_last_branch() { return reg.last_branch; }
+
+
+#pragma pack(push, 1)
+    struct TGC_C_regs { 
+        uint32_t X0 = 0; 
+        uint32_t X1 = 0; 
+        uint32_t X2 = 0; 
+        uint32_t X3 = 0; 
+        uint32_t X4 = 0; 
+        uint32_t X5 = 0; 
+        uint32_t X6 = 0; 
+        uint32_t X7 = 0; 
+        uint32_t X8 = 0; 
+        uint32_t X9 = 0; 
+        uint32_t X10 = 0; 
+        uint32_t X11 = 0; 
+        uint32_t X12 = 0; 
+        uint32_t X13 = 0; 
+        uint32_t X14 = 0; 
+        uint32_t X15 = 0; 
+        uint32_t X16 = 0; 
+        uint32_t X17 = 0; 
+        uint32_t X18 = 0; 
+        uint32_t X19 = 0; 
+        uint32_t X20 = 0; 
+        uint32_t X21 = 0; 
+        uint32_t X22 = 0; 
+        uint32_t X23 = 0; 
+        uint32_t X24 = 0; 
+        uint32_t X25 = 0; 
+        uint32_t X26 = 0; 
+        uint32_t X27 = 0; 
+        uint32_t X28 = 0; 
+        uint32_t X29 = 0; 
+        uint32_t X30 = 0; 
+        uint32_t X31 = 0; 
+        uint32_t PC = 0; 
+        uint32_t NEXT_PC = 0; 
+        uint8_t PRIV = 0; 
+        uint32_t DPC = 0;
+        uint32_t trap_state = 0, pending_trap = 0;
+        uint64_t icount = 0;
+        uint64_t cycle = 0;
+        uint64_t instret = 0;
+        uint32_t instruction = 0;
+        uint32_t last_branch = 0;
+    } reg;
+#pragma pack(pop)
+    std::array<address_type, 4> addr_mode;
+    
+    uint64_t interrupt_sim=0;
+
+    uint32_t get_fcsr(){return 0;}
+    void set_fcsr(uint32_t val){}
+
+};
+
+}
+}            
+#endif /* _TGC_C_H_ */

src/iss/arch/tgc_c_decoder.cpp

@@ -0,0 +1,175 @@
+#include "tgc_c.h"
+#include <vector>
+#include <array>
+#include <cstdlib>
+#include <algorithm>
+
+namespace iss {
+namespace arch {
+namespace {
+// according to
+// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
+#ifdef __GCC__
+constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); }
+#elif __cplusplus < 201402L
+constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); }
+constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; }
+#else
+constexpr size_t bit_count(uint32_t u) {
+    size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111);
+    return ((uCount + (uCount >> 3)) & 030707070707) % 63;
+}
+#endif
+
+using opcode_e = traits<tgc_c>::opcode_e;
+
+/****************************************************************************
+ * start opcode definitions
+ ****************************************************************************/
+struct instruction_desriptor {
+    size_t length;
+    uint32_t value;
+    uint32_t mask;
+    opcode_e op;
+};
+
+const std::array<instruction_desriptor, 90> instr_descr = {{
+     /* entries are: size, valid value, valid mask, function ptr */
+    {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, opcode_e::LUI},
+    {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, opcode_e::AUIPC},
+    {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, opcode_e::JAL},
+    {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, opcode_e::JALR},
+    {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, opcode_e::BEQ},
+    {32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, opcode_e::BNE},
+    {32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, opcode_e::BLT},
+    {32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, opcode_e::BGE},
+    {32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, opcode_e::BLTU},
+    {32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, opcode_e::BGEU},
+    {32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, opcode_e::LB},
+    {32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, opcode_e::LH},
+    {32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, opcode_e::LW},
+    {32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, opcode_e::LBU},
+    {32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, opcode_e::LHU},
+    {32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, opcode_e::SB},
+    {32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, opcode_e::SH},
+    {32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, opcode_e::SW},
+    {32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, opcode_e::ADDI},
+    {32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, opcode_e::SLTI},
+    {32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, opcode_e::SLTIU},
+    {32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, opcode_e::XORI},
+    {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, opcode_e::ORI},
+    {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, opcode_e::ANDI},
+    {32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, opcode_e::SLLI},
+    {32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, opcode_e::SRLI},
+    {32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, opcode_e::SRAI},
+    {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, opcode_e::ADD},
+    {32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, opcode_e::SUB},
+    {32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, opcode_e::SLL},
+    {32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, opcode_e::SLT},
+    {32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, opcode_e::SLTU},
+    {32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, opcode_e::XOR},
+    {32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, opcode_e::SRL},
+    {32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, opcode_e::SRA},
+    {32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, opcode_e::OR},
+    {32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, opcode_e::AND},
+    {32, 0b00000000000000000000000000001111, 0b00000000000000000111000001111111, opcode_e::FENCE},
+    {32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, opcode_e::ECALL},
+    {32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, opcode_e::EBREAK},
+    {32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::URET},
+    {32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::SRET},
+    {32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::MRET},
+    {32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, opcode_e::WFI},
+    {32, 0b01111011001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::DRET},
+    {32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRW},
+    {32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRS},
+    {32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRC},
+    {32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRWI},
+    {32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRSI},
+    {32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRCI},
+    {32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, opcode_e::FENCE_I},
+    {32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, opcode_e::MUL},
+    {32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, opcode_e::MULH},
+    {32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, opcode_e::MULHSU},
+    {32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, opcode_e::MULHU},
+    {32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, opcode_e::DIV},
+    {32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, opcode_e::DIVU},
+    {32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, opcode_e::REM},
+    {32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, opcode_e::REMU},
+    {16, 0b0000000000000000, 0b1110000000000011, opcode_e::CADDI4SPN},
+    {16, 0b0100000000000000, 0b1110000000000011, opcode_e::CLW},
+    {16, 0b1100000000000000, 0b1110000000000011, opcode_e::CSW},
+    {16, 0b0000000000000001, 0b1110000000000011, opcode_e::CADDI},
+    {16, 0b0000000000000001, 0b1110111110000011, opcode_e::CNOP},
+    {16, 0b0010000000000001, 0b1110000000000011, opcode_e::CJAL},
+    {16, 0b0100000000000001, 0b1110000000000011, opcode_e::CLI},
+    {16, 0b0110000000000001, 0b1110000000000011, opcode_e::CLUI},
+    {16, 0b0110000100000001, 0b1110111110000011, opcode_e::CADDI16SP},
+    {16, 0b0110000000000001, 0b1111000001111111, opcode_e::__reserved_clui},
+    {16, 0b1000000000000001, 0b1111110000000011, opcode_e::CSRLI},
+    {16, 0b1000010000000001, 0b1111110000000011, opcode_e::CSRAI},
+    {16, 0b1000100000000001, 0b1110110000000011, opcode_e::CANDI},
+    {16, 0b1000110000000001, 0b1111110001100011, opcode_e::CSUB},
+    {16, 0b1000110000100001, 0b1111110001100011, opcode_e::CXOR},
+    {16, 0b1000110001000001, 0b1111110001100011, opcode_e::COR},
+    {16, 0b1000110001100001, 0b1111110001100011, opcode_e::CAND},
+    {16, 0b1010000000000001, 0b1110000000000011, opcode_e::CJ},
+    {16, 0b1100000000000001, 0b1110000000000011, opcode_e::CBEQZ},
+    {16, 0b1110000000000001, 0b1110000000000011, opcode_e::CBNEZ},
+    {16, 0b0000000000000010, 0b1111000000000011, opcode_e::CSLLI},
+    {16, 0b0100000000000010, 0b1110000000000011, opcode_e::CLWSP},
+    {16, 0b1000000000000010, 0b1111000000000011, opcode_e::CMV},
+    {16, 0b1000000000000010, 0b1111000001111111, opcode_e::CJR},
+    {16, 0b1000000000000010, 0b1111111111111111, opcode_e::__reserved_cmv},
+    {16, 0b1001000000000010, 0b1111000000000011, opcode_e::CADD},
+    {16, 0b1001000000000010, 0b1111000001111111, opcode_e::CJALR},
+    {16, 0b1001000000000010, 0b1111111111111111, opcode_e::CEBREAK},
+    {16, 0b1100000000000010, 0b1110000000000011, opcode_e::CSWSP},
+    {16, 0b0000000000000000, 0b1111111111111111, opcode_e::DII},
+}};
+
+}
+
+template<>
+struct instruction_decoder<tgc_c> {
+    using opcode_e = traits<tgc_c>::opcode_e;
+    using code_word_t=traits<tgc_c>::code_word_t;
+
+    struct instruction_pattern {
+        uint32_t value;
+        uint32_t mask;
+        opcode_e id;
+    };
+
+    std::array<std::vector<instruction_pattern>, 4> qlut;
+
+    template<typename T>
+    unsigned decode_instruction(T);
+
+    instruction_decoder() {
+        for (auto instr : instr_descr) {
+            auto quadrant = instr.value & 0x3;
+            qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
+        }
+        for(auto& lut: qlut){
+            std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
+                return bit_count(a.mask) > bit_count(b.mask);
+            });
+        }
+    }
+};
+
+template<>
+unsigned instruction_decoder<tgc_c>::decode_instruction<traits<tgc_c>::code_word_t>(traits<tgc_c>::code_word_t instr){
+    auto res = std::find_if(std::begin(qlut[instr&0x3]), std::end(qlut[instr&0x3]), [instr](instruction_pattern const& e){
+        return !((instr&e.mask) ^ e.value );
+    });
+    return static_cast<unsigned>(res!=std::end(qlut[instr&0x3])? res->id : opcode_e::MAX_OPCODE);
+}
+
+
+std::unique_ptr<instruction_decoder<tgc_c>> traits<tgc_c>::get_decoder(){
+    return std::make_unique<instruction_decoder<tgc_c>>();
+}
+
+}
+}

src/iss/arch/tgc_mapper.h

@@ -2,56 +2,49 @@
 #define _ISS_ARCH_TGC_MAPPER_H
 
 #include "riscv_hart_m_p.h"
-#include "tgc5c.h"
+#include "tgc_c.h"
-using tgc5c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc5c>;
+using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
-#ifdef CORE_TGC5A
+#ifdef CORE_TGC_A
 #include "riscv_hart_m_p.h"
-#include <iss/arch/tgc5a.h>
+#include <iss/arch/tgc_a.h>
-using tgc5a_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc5a>;
+using tgc_a_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_a>;
 #endif
-#ifdef CORE_TGC5B
+#ifdef CORE_TGC_B
 #include "riscv_hart_m_p.h"
-#include <iss/arch/tgc5b.h>
+#include <iss/arch/tgc_b.h>
-using tgc5b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc5b>;
+using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
 #endif
-#ifdef CORE_TGC5C_XRB_NN
+#ifdef CORE_TGC_C_XRB_NN
+#include "riscv_hart_m_p.h"
 #include "hwl.h"
-#include "riscv_hart_m_p.h"
+#include <iss/arch/tgc_c_xrb_nn.h>
-#include <iss/arch/tgc5c_xrb_nn.h>
+using tgc_c_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_m_p<iss::arch::tgc_c_xrb_nn>>;
-using tgc5c_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_m_p<iss::arch::tgc5c_xrb_nn>>;
 #endif
-#ifdef CORE_TGC5D
+#ifdef CORE_TGC_D
 #include "riscv_hart_mu_p.h"
-#include <iss/arch/tgc5d.h>
+#include <iss/arch/tgc_d.h>
-using tgc5d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc5d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC |
+using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
-                                                                                             iss::arch::FEAT_EXT_N)>;
 #endif
-#ifdef CORE_TGC5D_XRB_MAC
+#ifdef CORE_TGC_D_XRB_MAC
 #include "riscv_hart_mu_p.h"
-#include <iss/arch/tgc5d_xrb_mac.h>
+#include <iss/arch/tgc_d_xrb_mac.h>
-using tgc5d_xrb_mac_plat_type =
+using tgc_d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_mac, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
-    iss::arch::riscv_hart_mu_p<iss::arch::tgc5d_xrb_mac,
-                               (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
 #endif
-#ifdef CORE_TGC5D_XRB_NN
+#ifdef CORE_TGC_D_XRB_NN
+#include "riscv_hart_mu_p.h"
 #include "hwl.h"
-#include "riscv_hart_mu_p.h"
+#include <iss/arch/tgc_d_xrb_nn.h>
-#include <iss/arch/tgc5d_xrb_nn.h>
+using tgc_d_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_nn, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>>;
-using tgc5d_xrb_nn_plat_type =
-    iss::arch::hwl<iss::arch::riscv_hart_mu_p<iss::arch::tgc5d_xrb_nn,
-                                              (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>>;
 #endif
-#ifdef CORE_TGC5E
+#ifdef CORE_TGC_E
 #include "riscv_hart_mu_p.h"
-#include <iss/arch/tgc5e.h>
+#include <iss/arch/tgc_e.h>
-using tgc5e_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc5e, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC |
+using tgc_e_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_e, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
-                                                                                             iss::arch::FEAT_EXT_N)>;
 #endif
-#ifdef CORE_TGC5X
+#ifdef CORE_TGC_X
 #include "riscv_hart_mu_p.h"
-#include <iss/arch/tgc5x.h>
+#include <iss/arch/tgc_x.h>
-using tgc5x_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc5x, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC |
+using tgc_x_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_x, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N | iss::arch::FEAT_TCM)>;
-                                                                                             iss::arch::FEAT_EXT_N | iss::arch::FEAT_TCM)>;
 #endif
 
 #endif

src/iss/arch/wt_cache.h

@@ -36,10 +36,10 @@
 #define _RISCV_HART_M_P_WT_CACHE_H
 
 #include <iss/vm_types.h>
-#include <map>
-#include <memory>
 #include <util/ities.h>
 #include <vector>
+#include <map>
+#include <memory>
 
 namespace iss {
 namespace arch {
@@ -50,13 +50,11 @@ struct line {
     uint64_t tag_addr{0};
     state st{state::INVALID};
     std::vector<uint8_t> data;
-    line(unsigned line_sz)
+    line(unsigned line_sz):  data(line_sz) {}
-    : data(line_sz) {}
 };
 struct set {
     std::vector<line> ways;
-    set(unsigned ways_count, line const& l)
+    set(unsigned ways_count, line const& l): ways(ways_count, l) {}
-    : ways(ways_count, l) {}
 };
 struct cache {
     std::vector<set> sets;
@@ -71,7 +69,7 @@ struct cache {
 struct wt_policy {
     bool is_cacheline_hit(cache& c );
 };
-} // namespace cache
+}
 
 // write thru, allocate on read, direct mapped or set-associative with round-robin replacement policy
 template <typename BASE> class wt_cache : public BASE {
@@ -83,15 +81,14 @@ public:
     using mem_write_f = typename BASE::mem_write_f;
     using phys_addr_t = typename BASE::phys_addr_t;
 
-    wt_cache(feature_config cfg = feature_config{});
+    wt_cache();
     virtual ~wt_cache() = default;
 
     unsigned size{4096};
-    unsigned line_sz{64};
+    unsigned line_sz{32};
     unsigned ways{1};
     uint64_t io_address{0xf0000000};
     uint64_t io_addr_mask{0xf0000000};
-
 protected:
     iss::status read_cache(phys_addr_t addr, unsigned, uint8_t *const);
     iss::status write_cache(phys_addr_t addr, unsigned, uint8_t const *const);
@@ -99,14 +96,14 @@ protected:
     std::function<mem_write_f> cache_mem_wr_delegate;
     std::unique_ptr<cache::cache> dcache_ptr;
     std::unique_ptr<cache::cache> icache_ptr;
-    size_t get_way_select() { return 0; }
+    size_t get_way_select() {
+        return 0;
+    }
 };
 
+
 template<typename BASE>
-inline wt_cache<BASE>::wt_cache(feature_config cfg)
+inline wt_cache<BASE>::wt_cache() {
-: BASE(cfg)
-, io_address{cfg.io_address}
-, io_addr_mask{cfg.io_addr_mask} {
     auto cb = base_class::replace_mem_access(
             [this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status { return read_cache(a, l,d);},
             [this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status { return write_cache(a, l,d);});
@@ -114,12 +111,13 @@ inline wt_cache<BASE>::wt_cache(feature_config cfg)
     cache_mem_wr_delegate = cb.second;
 }
 
-template <typename BASE> iss::status iss::arch::wt_cache<BASE>::read_cache(phys_addr_t a, unsigned l, uint8_t* const d) {
+template<typename BASE>
+iss::status iss::arch::wt_cache<BASE>::read_cache(phys_addr_t a, unsigned l, uint8_t* const d) {
     if(!icache_ptr) {
         icache_ptr.reset(new cache::cache(size, line_sz, ways));
         dcache_ptr.reset(new cache::cache(size, line_sz, ways));
     }
-    if((a.access & iss::access_type::FETCH) == iss::access_type::FETCH || (a.val & io_addr_mask) != io_address) {
+    if((a.val&io_addr_mask) != io_address) {
         auto set_addr=(a.val&(size-1))>>util::ilog2(line_sz*ways);
         auto tag_addr=a.val>>util::ilog2(line_sz);
         auto& set = (is_fetch(a.access)?icache_ptr:dcache_ptr)->sets[set_addr];
@@ -145,7 +143,8 @@ template <typename BASE> iss::status iss::arch::wt_cache<BASE>::read_cache(phys_
         return cache_mem_rd_delegate(a, l, d);
 }
 
-template <typename BASE> iss::status iss::arch::wt_cache<BASE>::write_cache(phys_addr_t a, unsigned l, const uint8_t* const d) {
+template<typename BASE>
+iss::status iss::arch::wt_cache<BASE>::write_cache(phys_addr_t a, unsigned l, const uint8_t* const d) {
     if(!dcache_ptr)
         dcache_ptr.reset(new cache::cache(size, line_sz, ways));
     auto res = cache_mem_wr_delegate(a, l, d);
@@ -165,6 +164,8 @@ template <typename BASE> iss::status iss::arch::wt_cache<BASE>::write_cache(phys
     return res;
 }
 
+
+
 } // namespace arch
 } // namespace iss
 

src/iss/debugger/riscv_target_adapter.h

@@ -30,8 +30,8 @@
  *
  *******************************************************************************/
 
-#ifndef _ISS_ARCH_DEBUGGER_RISCV_TARGET_ADAPTER_H_
+#ifndef _ISS_DEBUGGER_RISCV_TARGET_ADAPTER_H_
-#define _ISS_ARCH_DEBUGGER_RISCV_TARGET_ADAPTER_H_
+#define _ISS_DEBUGGER_RISCV_TARGET_ADAPTER_H_
 
 #include "iss/arch_if.h"
 #include <iss/arch/traits.h>
@@ -48,10 +48,6 @@
 
 namespace iss {
 namespace debugger {
-
-char const* const get_csr_name(unsigned);
-constexpr auto csr_offset = 100U;
-
 using namespace iss::arch;
 using namespace iss::debugger;
 
@@ -88,7 +84,8 @@ public:
      target byte order. If  register is not available
      corresponding bytes in avail_buf are 0, otherwise
      avail buf is 1 */
-    status read_single_register(unsigned int reg_no, std::vector<uint8_t>& buf, std::vector<uint8_t>& avail_buf) override;
+    status read_single_register(unsigned int reg_no, std::vector<uint8_t> &buf,
+            std::vector<uint8_t> &avail_buf) override;
 
     /* Write one register. buf is 4-byte aligned and it is in target byte
      order */
@@ -106,8 +103,8 @@ public:
 
     status process_query(unsigned int &mask, const rp_thread_ref &arg, rp_thread_info &info) override;
 
-    status thread_list_query(int first, const rp_thread_ref& arg, std::vector<rp_thread_ref>& result, size_t max_num, size_t& num,
+    status thread_list_query(int first, const rp_thread_ref &arg, std::vector<rp_thread_ref> &result, size_t max_num,
-                             bool& done) override;
+            size_t &num, bool &done) override;
 
     status current_thread_query(rp_thread_ref &thread) override;
 
@@ -127,23 +124,18 @@ public:
 
     status remove_break(break_type type, uint64_t addr, unsigned int length) override;
 
-    status resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread, std::function<void(unsigned)> stop_callback) override;
+    status resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
+            std::function<void(unsigned)> stop_callback) override;
 
     status target_xml_query(std::string &out_buf) override;
 
 protected:
     static inline constexpr addr_t map_addr(const addr_t &i) { return i; }
-    std::string csr_xml;
+
     iss::arch_if *core;
     rp_thread_ref thread_idx;
 };
 
-template <typename ARCH> typename std::enable_if<iss::arch::traits<ARCH>::FLEN != 0, unsigned>::type get_f0_offset() {
-    return iss::arch::traits<ARCH>::F0;
-}
-
-template <typename ARCH> typename std::enable_if<iss::arch::traits<ARCH>::FLEN == 0, unsigned>::type get_f0_offset() { return 0; }
-
 template <typename ARCH> status riscv_target_adapter<ARCH>::set_gen_thread(rp_thread_ref &thread) {
     thread_idx = thread;
     return Ok;
@@ -166,8 +158,9 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::is_thread_alive(rp_t
  * set if all threads are processed.
  */
 template <typename ARCH>
-status riscv_target_adapter<ARCH>::thread_list_query(int first, const rp_thread_ref& arg, std::vector<rp_thread_ref>& result,
+status riscv_target_adapter<ARCH>::thread_list_query(int first, const rp_thread_ref &arg,
-                                                     size_t max_num, size_t& num, bool& done) {
+        std::vector<rp_thread_ref> &result, size_t max_num, size_t &num,
+        bool &done) {
     if (first == 0) {
         result.clear();
         result.push_back(thread_idx);
@@ -183,31 +176,15 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::current_thread_query
     return Ok;
 }
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
+template <typename ARCH>
-    CPPLOG(TRACE) << "reading target registers";
+status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t> &data, std::vector<uint8_t> &avail) {
+    LOG(TRACE) << "reading target registers";
+    // return idx<0?:;
     data.clear();
     avail.clear();
     const uint8_t *reg_base = core->get_regs_base_ptr();
     auto start_reg=arch::traits<ARCH>::X0;
-    for(size_t i = 0; i < 33; ++i) {
+    for (size_t reg_no = start_reg; reg_no < start_reg+33/*arch::traits<ARCH>::NUM_REGS*/; ++reg_no) {
-        if(i < arch::traits<ARCH>::RFS || i == arch::traits<ARCH>::PC) {
-            auto reg_no = i < 32 ? start_reg + i : arch::traits<ARCH>::PC;
-            unsigned offset = traits<ARCH>::reg_byte_offsets[reg_no];
-            for(size_t j = 0; j < arch::traits<ARCH>::XLEN / 8; ++j) {
-                data.push_back(*(reg_base + offset + j));
-                avail.push_back(0xff);
-            }
-        } else {
-            for(size_t j = 0; j < arch::traits<ARCH>::XLEN / 8; ++j) {
-                data.push_back(0);
-                avail.push_back(0);
-            }
-        }
-    }
-    if(iss::arch::traits<ARCH>::FLEN > 0) {
-        auto fstart_reg = get_f0_offset<ARCH>();
-        for(size_t i = 0; i < 32; ++i) {
-            auto reg_no = fstart_reg + i;
         auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
         unsigned offset = traits<ARCH>::reg_byte_offsets[reg_no];
         for (size_t j = 0; j < reg_width; ++j) {
@@ -215,7 +192,21 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::read_registers(std::
             avail.push_back(0xff);
         }
     }
-    }
+    // work around fill with F type registers
+    //    if (arch::traits<ARCH>::NUM_REGS < 65) {
+    //        auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
+    //        for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
+    //            for (size_t j = 0; j < reg_width; ++j) {
+    //                data.push_back(0x0);
+    //                avail.push_back(0x00);
+    //            }
+    //            // if(arch::traits<ARCH>::XLEN < 64)
+    //            //     for(unsigned j=0; j<4; ++j){
+    //            //         data.push_back(0x0);
+    //            //         avail.push_back(0x00);
+    //            //     }
+    //        }
+    //    }
     return Ok;
 }
 
@@ -223,33 +214,34 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(cons
     auto start_reg=arch::traits<ARCH>::X0;
     auto *reg_base = core->get_regs_base_ptr();
     auto iter = data.data();
-    auto iter_end = data.data() + data.size();
+    bool e_ext = arch::traits<ARCH>::PC<32;
-    for(size_t i = 0; i < 33 && iter < iter_end; ++i) {
+    for (size_t reg_no = 0; reg_no < start_reg+33/*arch::traits<ARCH>::NUM_REGS*/; ++reg_no) {
-        auto reg_width = arch::traits<ARCH>::XLEN / 8;
+        if(e_ext && reg_no>15){
-        if(i < arch::traits<ARCH>::RFS) {
+            if(reg_no==32){
-            auto offset = traits<ARCH>::reg_byte_offsets[start_reg + i];
+                auto reg_width = arch::traits<ARCH>::reg_bit_widths[arch::traits<ARCH>::PC] / 8;
-            std::copy(iter, iter + reg_width, reg_base + offset);
-        } else if(i == 32) {
                 auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
-            std::copy(iter, iter + reg_width, reg_base + offset);
+                std::copy(iter, iter + reg_width, reg_base);
+            } else {
+                const uint64_t zero_val=0;
+                auto reg_width = arch::traits<ARCH>::reg_bit_widths[15] / 8;
+                auto iter = (uint8_t*)&zero_val;
+                std::copy(iter, iter + reg_width, reg_base);
             }
-        iter += reg_width;
+        } else {
-    }
+            auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
-    if(iss::arch::traits<ARCH>::FLEN > 0) {
+            auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
-        auto fstart_reg = get_f0_offset<ARCH>();
+            std::copy(iter, iter + reg_width, reg_base);
-        auto reg_width = arch::traits<ARCH>::FLEN / 8;
+            iter += 4;
-        for(size_t i = 0; i < 32 && iter < iter_end; ++i) {
+            reg_base += offset;
-            unsigned offset = traits<ARCH>::reg_byte_offsets[fstart_reg + i];
-            std::copy(iter, iter + reg_width, reg_base + offset);
-            iter += reg_width;
         }
     }
     return Ok;
 }
 
 template <typename ARCH>
-status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
+status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t> &data,
-    if(reg_no < csr_offset) {
+        std::vector<uint8_t> &avail) {
+    if (reg_no < 65) {
         // auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename
         // arch::traits<ARCH>::reg_e>(reg_no))/8;
         auto *reg_base = core->get_regs_base_ptr();
@@ -260,24 +252,24 @@ status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std
         std::copy(reg_base + offset, reg_base + offset + reg_width, data.begin());
         std::fill(avail.begin(), avail.end(), 0xff);
     } else {
-        typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_READ, traits<ARCH>::CSR, reg_no - csr_offset);
+        typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_READ, traits<ARCH>::CSR, reg_no - 65);
         data.resize(sizeof(typename traits<ARCH>::reg_t));
         avail.resize(sizeof(typename traits<ARCH>::reg_t));
         std::fill(avail.begin(), avail.end(), 0xff);
         core->read(a, data.size(), data.data());
-        std::fill(avail.begin(), avail.end(), 0xff);
     }
     return data.size() > 0 ? Ok : Err;
 }
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::write_single_register(unsigned int reg_no, const std::vector<uint8_t>& data) {
+template <typename ARCH>
-    if(reg_no < csr_offset) {
+status riscv_target_adapter<ARCH>::write_single_register(unsigned int reg_no, const std::vector<uint8_t> &data) {
+    if (reg_no < 65) {
         auto *reg_base = core->get_regs_base_ptr();
         auto reg_width = arch::traits<ARCH>::reg_bit_widths[static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)] / 8;
         auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
         std::copy(data.begin(), data.begin() + reg_width, reg_base + offset);
     } else {
-        typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_WRITE, traits<ARCH>::CSR, reg_no - csr_offset);
+        typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_WRITE, traits<ARCH>::CSR, reg_no - 65);
         core->write(a, data.size(), data.data());
     }
     return Ok;
@@ -290,7 +282,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::read_mem(uint64_t ad
 }
 
 template <typename ARCH> status riscv_target_adapter<ARCH>::write_mem(uint64_t addr, const std::vector<uint8_t> &data) {
-    auto a = map_addr({iss::access_type::DEBUG_WRITE, iss::address_type::VIRTUAL, 0, addr});
+    auto a = map_addr({iss::access_type::DEBUG_READ, iss::address_type::VIRTUAL, 0, addr});
     auto f = [&]() -> status { return core->write(a, data.size(), data.data()); };
     return srv->execute_syncronized(f);
 }
@@ -300,16 +292,21 @@ status riscv_target_adapter<ARCH>::process_query(unsigned int& mask, const rp_th
     return NotSupported;
 }
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::offsets_query(uint64_t& text, uint64_t& data, uint64_t& bss) {
+template <typename ARCH>
+status riscv_target_adapter<ARCH>::offsets_query(uint64_t &text, uint64_t &data, uint64_t &bss) {
     text = 0;
     data = 0;
     bss = 0;
     return Ok;
 }
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::crc_query(uint64_t addr, size_t len, uint32_t& val) { return NotSupported; }
+template <typename ARCH> status riscv_target_adapter<ARCH>::crc_query(uint64_t addr, size_t len, uint32_t &val) {
+    return NotSupported;
+}
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::raw_query(std::string in_buf, std::string& out_buf) { return NotSupported; }
+template <typename ARCH> status riscv_target_adapter<ARCH>::raw_query(std::string in_buf, std::string &out_buf) {
+    return NotSupported;
+}
 
 template <typename ARCH> status riscv_target_adapter<ARCH>::threadinfo_query(int first, std::string &out_buf) {
     if (first) {
@@ -320,7 +317,8 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::threadinfo_query(int
     return Ok;
 }
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::threadextrainfo_query(const rp_thread_ref& thread, std::string& out_buf) {
+template <typename ARCH>
+status riscv_target_adapter<ARCH>::threadextrainfo_query(const rp_thread_ref &thread, std::string &out_buf) {
     std::array<char, 20> buf;
     memset(buf.data(), 0, 20);
     sprintf(buf.data(), "%02x%02x%02x%02x%02x%02x%02x%02x%02x", 'R', 'u', 'n', 'n', 'a', 'b', 'l', 'e', 0);
@@ -342,9 +340,9 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(break_type
         auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
         auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
         target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
-        CPPLOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex << saddr.val
+        LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex
-                      << std::dec;
+                << saddr.val << std::dec;
-        CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
+        LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
         return Ok;
     }
     }
@@ -359,13 +357,14 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(break_t
         auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
         unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
         if (handle) {
-            CPPLOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val << std::dec;
+            LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val
+                    << std::dec;
             // TODO: check length of addr range
             target_adapter_base::bp_lut.removeEntry(handle);
-            CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
+            LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
             return Ok;
         }
-        CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
+        LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
         return Err;
     }
     }
@@ -383,56 +382,93 @@ status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t
 }
 
 template <typename ARCH> status riscv_target_adapter<ARCH>::target_xml_query(std::string &out_buf) {
-    if(!csr_xml.size()) {
+    const std::string res{"<?xml version=\"1.0\"?><!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
-        std::ostringstream oss;
+        "<target><architecture>riscv:rv32</architecture>"
-        oss << "<?xml version=\"1.0\"?><!DOCTYPE feature SYSTEM \"gdb-target.dtd\"><target version=\"1.0\">\n";
+        //"  <feature name=\"org.gnu.gdb.riscv.rv32i\">\n"
-        if(iss::arch::traits<ARCH>::XLEN == 32)
+        //"    <reg name=\"x0\"  bitsize=\"32\" group=\"general\"/>\n"
-            oss << "<architecture>riscv:rv32</architecture>\n";
+        //"    <reg name=\"x1\"  bitsize=\"32\" group=\"general\"/>\n"
-        else if(iss::arch::traits<ARCH>::XLEN == 64)
+        //"    <reg name=\"x2\"  bitsize=\"32\" group=\"general\"/>\n"
-            oss << "  <architectureriscv:rv64</architecture>\n";
+        //"    <reg name=\"x3\"  bitsize=\"32\" group=\"general\"/>\n"
-        oss << "  <feature name=\"org.gnu.gdb.riscv.cpu\">\n";
+        //"    <reg name=\"x4\"  bitsize=\"32\" group=\"general\"/>\n"
-        auto reg_base_num = iss::arch::traits<ARCH>::X0;
+        //"    <reg name=\"x5\"  bitsize=\"32\" group=\"general\"/>\n"
-        for(auto i = 0U; i < iss::arch::traits<ARCH>::RFS; ++i) {
+        //"    <reg name=\"x6\"  bitsize=\"32\" group=\"general\"/>\n"
-            oss << "    <reg name=\"x" << i << "\" bitsize=\"" << iss::arch::traits<ARCH>::reg_bit_widths[reg_base_num + i]
+        //"    <reg name=\"x7\"  bitsize=\"32\" group=\"general\"/>\n"
-                << "\" type=\"int\" regnum=\"" << i << "\"/>\n";
+        //"    <reg name=\"x8\"  bitsize=\"32\" group=\"general\"/>\n"
-        }
+        //"    <reg name=\"x9\"  bitsize=\"32\" group=\"general\"/>\n"
-        oss << "    <reg name=\"pc\" bitsize=\"" << iss::arch::traits<ARCH>::reg_bit_widths[iss::arch::traits<ARCH>::PC]
+        //"    <reg name=\"x10\" bitsize=\"32\" group=\"general\"/>\n"
-            << "\" type=\"code_ptr\" regnum=\"" << 32U << "\"/>\n";
+        //"    <reg name=\"x11\" bitsize=\"32\" group=\"general\"/>\n"
-        oss << "  </feature>\n";
+        //"    <reg name=\"x12\" bitsize=\"32\" group=\"general\"/>\n"
-        if(iss::arch::traits<ARCH>::FLEN > 0) {
+        //"    <reg name=\"x13\" bitsize=\"32\" group=\"general\"/>\n"
-            oss << "  <feature name=\"org.gnu.gdb.riscv.fpu\">\n";
+        //"    <reg name=\"x14\" bitsize=\"32\" group=\"general\"/>\n"
-            auto reg_base_num = get_f0_offset<ARCH>();
+        //"    <reg name=\"x15\" bitsize=\"32\" group=\"general\"/>\n"
-            auto type = iss::arch::traits<ARCH>::FLEN == 32 ? "ieee_single" : "riscv_double";
+        //"    <reg name=\"x16\" bitsize=\"32\" group=\"general\"/>\n"
-            for(auto i = 0U; i < 32; ++i) {
+        //"    <reg name=\"x17\" bitsize=\"32\" group=\"general\"/>\n"
-                oss << "    <reg name=\"f" << i << "\" bitsize=\"" << iss::arch::traits<ARCH>::reg_bit_widths[reg_base_num + i]
+        //"    <reg name=\"x18\" bitsize=\"32\" group=\"general\"/>\n"
-                    << "\" type=\"" << type << "\" regnum=\"" << i + 33 << "\"/>\n";
+        //"    <reg name=\"x19\" bitsize=\"32\" group=\"general\"/>\n"
-            }
+        //"    <reg name=\"x20\" bitsize=\"32\" group=\"general\"/>\n"
-            oss << "    <reg name=\"fcsr\" bitsize=\"" << iss::arch::traits<ARCH>::XLEN << "\" regnum=\"103\" type int/>\n";
+        //"    <reg name=\"x21\" bitsize=\"32\" group=\"general\"/>\n"
-            oss << "    <reg name=\"fflags\" bitsize=\"" << iss::arch::traits<ARCH>::XLEN << "\" regnum=\"101\" type int/>\n";
+        //"    <reg name=\"x22\" bitsize=\"32\" group=\"general\"/>\n"
-            oss << "    <reg name=\"frm\" bitsize=\"" << iss::arch::traits<ARCH>::XLEN << "\" regnum=\"102\" type int/>\n";
+        //"    <reg name=\"x23\" bitsize=\"32\" group=\"general\"/>\n"
-            oss << "  </feature>\n";
+        //"    <reg name=\"x24\" bitsize=\"32\" group=\"general\"/>\n"
-        }
+        //"    <reg name=\"x25\" bitsize=\"32\" group=\"general\"/>\n"
-        oss << "  <feature name=\"org.gnu.gdb.riscv.csr\">\n";
+        //"    <reg name=\"x26\" bitsize=\"32\" group=\"general\"/>\n"
-        std::vector<uint8_t> data;
+        //"    <reg name=\"x27\" bitsize=\"32\" group=\"general\"/>\n"
-        std::vector<uint8_t> avail;
+        //"    <reg name=\"x28\" bitsize=\"32\" group=\"general\"/>\n"
-        data.resize(sizeof(typename traits<ARCH>::reg_t));
+        //"    <reg name=\"x29\" bitsize=\"32\" group=\"general\"/>\n"
-        avail.resize(sizeof(typename traits<ARCH>::reg_t));
+        //"    <reg name=\"x30\" bitsize=\"32\" group=\"general\"/>\n"
-        for(auto i = 0U; i < 4096; ++i) {
+        //"    <reg name=\"x31\" bitsize=\"32\" group=\"general\"/>\n"
-            typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_READ, traits<ARCH>::CSR, i);
+        //"  </feature>\n"
-            std::fill(avail.begin(), avail.end(), 0xff);
+        "</target>"};
-            auto res = core->read(a, data.size(), data.data());
+    out_buf = res;
-            if(res == iss::Ok) {
-                oss << "    <reg name=\"" << get_csr_name(i) << "\" bitsize=\"" << iss::arch::traits<ARCH>::XLEN
-                    << "\"  type=\"int\" regnum=\"" << (i + csr_offset) << "\"/>\n";
-            }
-        }
-        oss << "  </feature>\n";
-        oss << "</target>\n";
-    }
-    out_buf = csr_xml;
     return Ok;
 }
-} // namespace debugger
-} // namespace iss
 
-#endif /* _ISS_ARCH_DEBUGGER_RISCV_TARGET_ADAPTER_H_ */
+/*
+ *
+<?xml version="1.0"?>
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+  <architecture>riscv:rv32</architecture>
+
+  <feature name="org.gnu.gdb.riscv.rv32i">
+    <reg name="x0"  bitsize="32" group="general"/>
+    <reg name="x1"  bitsize="32" group="general"/>
+    <reg name="x2"  bitsize="32" group="general"/>
+    <reg name="x3"  bitsize="32" group="general"/>
+    <reg name="x4"  bitsize="32" group="general"/>
+    <reg name="x5"  bitsize="32" group="general"/>
+    <reg name="x6"  bitsize="32" group="general"/>
+    <reg name="x7"  bitsize="32" group="general"/>
+    <reg name="x8"  bitsize="32" group="general"/>
+    <reg name="x9"  bitsize="32" group="general"/>
+    <reg name="x10" bitsize="32" group="general"/>
+    <reg name="x11" bitsize="32" group="general"/>
+    <reg name="x12" bitsize="32" group="general"/>
+    <reg name="x13" bitsize="32" group="general"/>
+    <reg name="x14" bitsize="32" group="general"/>
+    <reg name="x15" bitsize="32" group="general"/>
+    <reg name="x16" bitsize="32" group="general"/>
+    <reg name="x17" bitsize="32" group="general"/>
+    <reg name="x18" bitsize="32" group="general"/>
+    <reg name="x19" bitsize="32" group="general"/>
+    <reg name="x20" bitsize="32" group="general"/>
+    <reg name="x21" bitsize="32" group="general"/>
+    <reg name="x22" bitsize="32" group="general"/>
+    <reg name="x23" bitsize="32" group="general"/>
+    <reg name="x24" bitsize="32" group="general"/>
+    <reg name="x25" bitsize="32" group="general"/>
+    <reg name="x26" bitsize="32" group="general"/>
+    <reg name="x27" bitsize="32" group="general"/>
+    <reg name="x28" bitsize="32" group="general"/>
+    <reg name="x29" bitsize="32" group="general"/>
+    <reg name="x30" bitsize="32" group="general"/>
+    <reg name="x31" bitsize="32" group="general"/>
+  </feature>
+
+</target>
+
+ */
+}
+}
+
+#endif /* _ISS_DEBUGGER_RISCV_TARGET_ADAPTER_H_ */

src/iss/factory.h

@@ -33,12 +33,12 @@
 #ifndef _ISS_FACTORY_H_
 #define _ISS_FACTORY_H_
 
-#include <algorithm>
-#include <functional>
 #include <iss/iss.h>
 #include <memory>
-#include <string>
 #include <unordered_map>
+#include <functional>
+#include <string>
+#include <algorithm>
 #include <vector>
 
 namespace iss {
@@ -46,7 +46,8 @@ namespace iss {
 using cpu_ptr = std::unique_ptr<iss::arch_if>;
 using vm_ptr= std::unique_ptr<iss::vm_if>;
 
-template <typename PLAT> std::tuple<cpu_ptr, vm_ptr> create_cpu(std::string const& backend, unsigned gdb_port) {
+template<typename PLAT>
+std::tuple<cpu_ptr, vm_ptr> create_cpu(std::string const& backend, unsigned gdb_port){
     using core_type = typename PLAT::core;
     core_type* lcpu = new PLAT();
     if(backend == "interp")
@@ -62,6 +63,7 @@ template <typename PLAT> std::tuple<cpu_ptr, vm_ptr> create_cpu(std::string cons
     return {nullptr, nullptr};
 }
 
+
 class core_factory {
     using cpu_ptr = std::unique_ptr<iss::arch_if>;
     using vm_ptr= std::unique_ptr<iss::vm_if>;
@@ -76,31 +78,33 @@ class core_factory {
     core_factory & operator=(const core_factory &) = delete;
 
 public:
-    static core_factory& instance() {
+    static core_factory & instance() { static core_factory bf; return bf; }
-        static core_factory bf;
-        return bf;
-    }
 
-    bool register_creator(const std::string& className, create_fn const& fn) {
+    bool register_creator(const std::string &, create_fn const&);
-        registry[className] = fn;
-        return true;
-    }
 
-    base_t create(std::string const& className, unsigned gdb_port = 0, void* init_data = nullptr) const {
+    base_t create(const std::string &, unsigned gdb_port=0, void* init_data=nullptr) const;
-        registry_t::const_iterator regEntry = registry.find(className);
-        if(regEntry != registry.end())
-            return regEntry->second(gdb_port, init_data);
-        return {nullptr, nullptr};
-    }
 
     std::vector<std::string> get_names() {
         std::vector<std::string> keys{registry.size()};
-        std::transform(std::begin(registry), std::end(registry), std::begin(keys),
+        std::transform(std::begin(registry), std::end(registry), std::begin(keys), [](std::pair<std::string, create_fn> const& p){
-                       [](std::pair<std::string, create_fn> const& p) { return p.first; });
+            return p.first;
+        });
         return keys;
     }
 };
 
-} // namespace iss
+inline bool core_factory::register_creator(const std::string & className, create_fn const& fn) {
+    registry[className] = fn;
+    return true;
+}
+
+inline core_factory::base_t core_factory::create(const std::string &className, unsigned gdb_port, void* data) const {
+    registry_t::const_iterator regEntry = registry.find(className);
+    if (regEntry != registry.end())
+        return regEntry->second(gdb_port, data);
+    return {nullptr, nullptr};
+}
+
+}
 
 #endif /* _ISS_FACTORY_H_ */