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a45fcd28db
| Author | SHA1 | Date | |
|---|---|---|---|
| a45fcd28db | |||
| 0f15032210 | |||
| efc11d87a5 | |||
| 4a19e27926 | |||
| c15cdb0955 | |||
| 6609d12582 | |||
| b5341700aa | |||
| 0b5062d21c | |||
| fbca690b3b | |||
| 235a7e6e24 | |||
| 62d21e1156 | |||
| 9c51d6eade | |||
| 2878dca6b5 | |||
| c28e8fd00c | |||
| b3cc9d2346 |
@ -38,7 +38,9 @@
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#include <asmjit/asmjit.h>
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#include <util/logging.h>
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#include <iss/instruction_decoder.h>
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<%def fcsr = registers.find {it.name=='FCSR'}
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if(fcsr != null) {%>
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#include <vm/fp_functions.h><%}%>
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#ifndef FMT_HEADER_ONLY
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#define FMT_HEADER_ONLY
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#endif
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@ -88,7 +90,6 @@ protected:
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using super::write_reg_to_mem;
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using super::gen_read_mem;
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using super::gen_write_mem;
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using super::gen_wait;
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using super::gen_leave;
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using super::gen_sync;
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@ -100,7 +101,9 @@ protected:
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void gen_block_prologue(jit_holder& jh) override;
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void gen_block_epilogue(jit_holder& jh) override;
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inline const char *name(size_t index){return traits::reg_aliases.at(index);}
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<%if(fcsr != null) {%>
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inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}
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<%}%>
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void gen_instr_prologue(jit_holder& jh);
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void gen_instr_epilogue(jit_holder& jh);
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inline void gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause);
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@ -113,6 +116,9 @@ protected:
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auto sign_mask = 1ULL<<(W-1);
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return (from & mask) | ((from & sign_mask) ? ~mask : 0);
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}
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<%functions.each{ it.eachLine { %>
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${it}<%}%>
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<%}%>
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private:
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/****************************************************************************
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* start opcode definitions
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@ -195,7 +201,7 @@ private:
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gen_raise(jh, 0, 2);
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gen_sync(jh, POST_SYNC, instr_descr.size());
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gen_instr_epilogue(jh);
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return BRANCH;
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return ILLEGAL_INSTR;
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}
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};
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@ -224,9 +230,9 @@ continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned
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paddr = this->core.virt2phys(pc);
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auto res = this->core.read(paddr, 4, data);
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if (res != iss::Ok)
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throw trap_access(TRAP_ID, pc.val);
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return ILLEGAL_FETCH;
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if (instr == 0x0000006f || (instr&0xffff)==0xa001)
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throw simulation_stopped(0); // 'J 0' or 'C.J 0'
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return JUMP_TO_SELF;
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++inst_cnt;
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uint32_t inst_index = instr_decoder.decode_instr(instr);
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compile_func f = nullptr;
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@ -267,7 +267,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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uint32_t inst_index = instr_decoder.decode_instr(instr);
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opcode_e inst_id = arch::traits<ARCH>::opcode_e::MAX_OPCODE;;
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if(inst_index <instr_descr.size())
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inst_id = instr_descr.at(instr_decoder.decode_instr(instr)).op;
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inst_id = instr_descr[inst_index].op;
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// pre execution stuff
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this->core.reg.last_branch = 0;
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@ -279,6 +279,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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<%}%>if(this->disass_enabled){
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/* generate console output when executing the command */<%instr.disass.eachLine{%>
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${it}<%}%>
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this->core.disass_output(pc.val, mnemonic);
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}
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// used registers<%instr.usedVariables.each{ k,v->
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if(v.isArray) {%>
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@ -37,7 +37,9 @@
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#include <iss/llvm/vm_base.h>
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#include <util/logging.h>
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#include <iss/instruction_decoder.h>
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<%def fcsr = registers.find {it.name=='FCSR'}
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if(fcsr != null) {%>
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#include <vm/fp_functions.h><%}%>
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#ifndef FMT_HEADER_ONLY
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#define FMT_HEADER_ONLY
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#endif
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@ -83,7 +85,9 @@ protected:
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using vm_base<ARCH>::get_reg_ptr;
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inline const char *name(size_t index){return traits::reg_aliases.at(index);}
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<%if(fcsr != null) {%>
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inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}
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<%}%>
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template <typename T> inline ConstantInt *size(T type) {
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return ConstantInt::get(getContext(), APInt(32, type->getType()->getScalarSizeInBits()));
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}
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@ -131,7 +135,9 @@ protected:
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auto sign_mask = 1ULL<<(W-1);
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return (from & mask) | ((from & sign_mask) ? ~mask : 0);
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}
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<%functions.each{ it.eachLine { %>
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${it}<%}%>
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<%}%>
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private:
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/****************************************************************************
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* start opcode definitions
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@ -212,7 +218,7 @@ private:
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bb = this->leave_blk;
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this->gen_instr_epilogue(bb);
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this->builder.CreateBr(bb);
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return std::make_tuple(BRANCH, nullptr);
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return std::make_tuple(ILLEGAL_INSTR, nullptr);
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}
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};
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@ -247,19 +253,11 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
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auto *const data = (uint8_t *)&instr;
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if(this->core.has_mmu())
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paddr = this->core.virt2phys(pc);
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//TODO: re-add page handling
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// if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
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// auto res = this->core.read(paddr, 2, data);
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// if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
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// if ((instr & 0x3) == 0x3) { // this is a 32bit instruction
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// res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
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// }
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// } else {
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auto res = this->core.read(paddr, 4, data);
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if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
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// }
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if (instr == 0x0000006f || (instr&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
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// curr pc on stack
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if (res != iss::Ok)
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return std::make_tuple(ILLEGAL_FETCH, nullptr);
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if (instr == 0x0000006f || (instr&0xffff)==0xa001)
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return std::make_tuple(JUMP_TO_SELF, nullptr);
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++inst_cnt;
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uint32_t inst_index = instr_decoder.decode_instr(instr);
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compile_func f = nullptr;
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@ -38,7 +38,9 @@
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#include <util/logging.h>
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#include <sstream>
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#include <iss/instruction_decoder.h>
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<%def fcsr = registers.find {it.name=='FCSR'}
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if(fcsr != null) {%>
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#include <vm/fp_functions.h><%}%>
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#ifndef FMT_HEADER_ONLY
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#define FMT_HEADER_ONLY
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#endif
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@ -85,7 +87,12 @@ protected:
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using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, tu_builder&);
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inline const char *name(size_t index){return traits::reg_aliases.at(index);}
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<%
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if(fcsr != null) {%>
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inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}
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void add_prologue(tu_builder& tu) override;
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<%}%>
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void setup_module(std::string m) override {
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super::setup_module(m);
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}
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@ -98,8 +105,6 @@ protected:
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void gen_leave_trap(tu_builder& tu, unsigned lvl);
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void gen_wait(tu_builder& tu, unsigned type);
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inline void gen_set_tval(tu_builder& tu, uint64_t new_tval);
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inline void gen_set_tval(tu_builder& tu, value new_tval);
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@ -133,6 +138,9 @@ protected:
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return (from & mask) | ((from & sign_mask) ? ~mask : 0);
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}
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<%functions.each{ it.eachLine { %>
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${it}<%}%>
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<%}%>
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private:
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/****************************************************************************
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* start opcode definitions
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@ -163,6 +171,7 @@ private:
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<%}%>if(this->disass_enabled){
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/* generate console output when executing the command */<%instr.disass.eachLine{%>
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${it}<%}%>
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tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
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}
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auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
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pc=pc+ ${instr.length/8};
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@ -187,11 +196,11 @@ private:
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tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, std::string("illegal_instruction"));
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}
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pc = pc + ((instr & 3) == 3 ? 4 : 2);
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gen_raise_trap(tu, 0, 2); // illegal instruction trap
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gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
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this->gen_set_tval(tu, instr);
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vm_impl::gen_sync(tu, iss::POST_SYNC, instr_descr.size());
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vm_impl::gen_trap_check(tu);
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return BRANCH;
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return ILLEGAL_INSTR;
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}
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};
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@ -224,19 +233,11 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
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phys_addr_t paddr(pc);
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if(this->core.has_mmu())
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paddr = this->core.virt2phys(pc);
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//TODO: re-add page handling
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// if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
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// auto res = this->core.read(paddr, 2, data);
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// if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
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// if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
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// res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
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// }
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// } else {
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auto res = this->core.read(paddr, 4, reinterpret_cast<uint8_t*>(&instr));
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if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
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// }
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if (instr == 0x0000006f || (instr&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
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// curr pc on stack
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if (res != iss::Ok)
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return ILLEGAL_FETCH;
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if (instr == 0x0000006f || (instr&0xffff)==0xa001)
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return JUMP_TO_SELF;
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++inst_cnt;
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uint32_t inst_index = instr_decoder.decode_instr(instr);
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compile_func f = nullptr;
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@ -258,9 +259,6 @@ template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsi
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tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(UNKNOWN_JUMP), 32));
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}
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template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned type) {
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}
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template <typename ARCH> void vm_impl<ARCH>::gen_set_tval(tu_builder& tu, uint64_t new_tval) {
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tu(fmt::format("tval = {};", new_tval));
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}
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@ -275,6 +273,39 @@ template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
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tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(UNKNOWN_JUMP),32));
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tu("return *next_pc;");
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}
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<%
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if(fcsr != null) {%>
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template <typename ARCH> void vm_impl<ARCH>::add_prologue(tu_builder& tu){
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std::ostringstream os;
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os << "uint32_t (*fget_flags)()=" << (uintptr_t)&fget_flags << ";\\n";
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os << "uint32_t (*fadd_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fadd_s << ";\\n";
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os << "uint32_t (*fsub_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fsub_s << ";\\n";
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os << "uint32_t (*fmul_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fmul_s << ";\\n";
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os << "uint32_t (*fdiv_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fdiv_s << ";\\n";
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os << "uint32_t (*fsqrt_s)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&fsqrt_s << ";\\n";
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os << "uint32_t (*fcmp_s)(uint32_t v1, uint32_t v2, uint32_t op)=" << (uintptr_t)&fcmp_s << ";\\n";
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os << "uint32_t (*fcvt_s)(uint32_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_s << ";\\n";
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os << "uint32_t (*fmadd_s)(uint32_t v1, uint32_t v2, uint32_t v3, uint32_t op, uint8_t mode)=" << (uintptr_t)&fmadd_s << ";\\n";
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os << "uint32_t (*fsel_s)(uint32_t v1, uint32_t v2, uint32_t op)=" << (uintptr_t)&fsel_s << ";\\n";
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os << "uint32_t (*fclass_s)( uint32_t v1 )=" << (uintptr_t)&fclass_s << ";\\n";
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os << "uint32_t (*fconv_d2f)(uint64_t v1, uint8_t mode)=" << (uintptr_t)&fconv_d2f << ";\\n";
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os << "uint64_t (*fconv_f2d)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&fconv_f2d << ";\\n";
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os << "uint64_t (*fadd_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fadd_d << ";\\n";
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os << "uint64_t (*fsub_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fsub_d << ";\\n";
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os << "uint64_t (*fmul_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fmul_d << ";\\n";
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os << "uint64_t (*fdiv_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fdiv_d << ";\\n";
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os << "uint64_t (*fsqrt_d)(uint64_t v1, uint8_t mode)=" << (uintptr_t)&fsqrt_d << ";\\n";
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os << "uint64_t (*fcmp_d)(uint64_t v1, uint64_t v2, uint32_t op)=" << (uintptr_t)&fcmp_d << ";\\n";
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os << "uint64_t (*fcvt_d)(uint64_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_d << ";\\n";
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os << "uint64_t (*fmadd_d)(uint64_t v1, uint64_t v2, uint64_t v3, uint32_t op, uint8_t mode)=" << (uintptr_t)&fmadd_d << ";\\n";
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os << "uint64_t (*fsel_d)(uint64_t v1, uint64_t v2, uint32_t op)=" << (uintptr_t)&fsel_d << ";\\n";
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os << "uint64_t (*fclass_d)(uint64_t v1 )=" << (uintptr_t)&fclass_d << ";\\n";
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os << "uint64_t (*fcvt_32_64)(uint32_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_32_64 << ";\\n";
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os << "uint32_t (*fcvt_64_32)(uint64_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_64_32 << ";\\n";
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os << "uint32_t (*unbox_s)(uint64_t v)=" << (uintptr_t)&unbox_s << ";\\n";
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tu.add_prologue(os.str());
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}
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<%}%>
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} // namespace ${coreDef.name.toLowerCase()}
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@ -613,7 +613,7 @@ std::pair<uint64_t, bool> riscv_hart_m_p<BASE, FEAT, LOGCAT>::load_file(std::str
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CPPLOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address();
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}
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}
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for(const auto sec : reader.sections) {
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for(const auto& sec : reader.sections) {
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if(sec->get_name() == ".tohost") {
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tohost = sec->get_address();
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fromhost = tohost + 0x40;
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14
src/main.cpp
14
src/main.cpp
@ -69,7 +69,8 @@ int main(int argc, char* argv[]) {
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("logfile,l", po::value<std::string>(), "Sets default log file.")
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("disass,d", po::value<std::string>()->implicit_value(""), "Enables disassembly")
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("gdb-port,g", po::value<unsigned>()->default_value(0), "enable gdb server and specify port to use")
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("instructions,i", po::value<uint64_t>()->default_value(std::numeric_limits<uint64_t>::max()), "max. number of instructions to simulate")
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("ilimit,i", po::value<uint64_t>()->default_value(std::numeric_limits<uint64_t>::max()), "max. number of instructions to simulate")
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("flimit", po::value<uint64_t>()->default_value(std::numeric_limits<uint64_t>::max()), "max. number of fetches to simulate")
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("reset,r", po::value<std::string>(), "reset address")
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("dump-ir", "dump the intermediate representation")
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("elf,f", po::value<std::vector<std::string>>(), "ELF file(s) to load")
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@ -215,8 +216,15 @@ int main(int argc, char* argv[]) {
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start_address = str.find("0x") == 0 ? std::stoull(str.substr(2), nullptr, 16) : std::stoull(str, nullptr, 10);
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}
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vm->reset(start_address);
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auto cycles = clim["instructions"].as<uint64_t>();
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res = vm->start(cycles, dump);
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auto limit = clim["ilimit"].as<uint64_t>();
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auto cond = iss::finish_cond_e::JUMP_TO_SELF;
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if(clim.count("flimit")) {
|
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cond = cond | iss::finish_cond_e::FCOUNT_LIMIT;
|
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limit = clim["flimit"].as<uint64_t>();
|
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} else {
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cond = cond | iss::finish_cond_e::ICOUNT_LIMIT;
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||||
}
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res = vm->start(limit, dump, cond);
|
||||
|
||||
auto instr_if = vm->get_arch()->get_instrumentation_if();
|
||||
// this assumes a single input file
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||||
|
||||
@ -199,7 +199,8 @@ struct core_trace {
|
||||
|
||||
SC_HAS_PROCESS(core_complex); // NOLINT
|
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#ifndef CWR_SYSTEMC
|
||||
core_complex::core_complex(sc_module_name const& name)
|
||||
template <unsigned int BUSWIDTH>
|
||||
core_complex<BUSWIDTH>::core_complex(sc_module_name const& name)
|
||||
: sc_module(name)
|
||||
, fetch_lut(tlm_dmi_ext())
|
||||
, read_lut(tlm_dmi_ext())
|
||||
@ -208,7 +209,8 @@ core_complex::core_complex(sc_module_name const& name)
|
||||
}
|
||||
#endif
|
||||
|
||||
void core_complex::init() {
|
||||
template <unsigned int BUSWIDTH>
|
||||
void core_complex<BUSWIDTH>::init() {
|
||||
trc = new core_trace();
|
||||
ibus.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
|
||||
auto lut_entry = fetch_lut.getEntry(start);
|
||||
@ -227,6 +229,7 @@ void core_complex::init() {
|
||||
}
|
||||
});
|
||||
|
||||
SC_HAS_PROCESS(core_complex<BUSWIDTH>); // NOLINT
|
||||
SC_THREAD(run);
|
||||
SC_METHOD(rst_cb);
|
||||
sensitive << rst_i;
|
||||
@ -252,16 +255,19 @@ void core_complex::init() {
|
||||
#endif
|
||||
}
|
||||
|
||||
core_complex::~core_complex() {
|
||||
template <unsigned int BUSWIDTH>
|
||||
core_complex<BUSWIDTH>::~core_complex() {
|
||||
delete cpu;
|
||||
delete trc;
|
||||
for(auto* p : plugin_list)
|
||||
delete p;
|
||||
}
|
||||
|
||||
void core_complex::trace(sc_trace_file* trf) const {}
|
||||
template <unsigned int BUSWIDTH>
|
||||
void core_complex<BUSWIDTH>::trace(sc_trace_file* trf) const {}
|
||||
|
||||
void core_complex::before_end_of_elaboration() {
|
||||
template <unsigned int BUSWIDTH>
|
||||
void core_complex<BUSWIDTH>::before_end_of_elaboration() {
|
||||
SCCDEBUG(SCMOD) << "instantiating iss::arch::tgf with " << GET_PROP_VALUE(backend) << " backend";
|
||||
// cpu = scc::make_unique<core_wrapper>(this);
|
||||
cpu = new core_wrapper(this);
|
||||
@ -302,7 +308,8 @@ void core_complex::before_end_of_elaboration() {
|
||||
}
|
||||
}
|
||||
|
||||
void core_complex::start_of_simulation() {
|
||||
template <unsigned int BUSWIDTH>
|
||||
void core_complex<BUSWIDTH>::start_of_simulation() {
|
||||
// quantum_keeper.reset();
|
||||
if(GET_PROP_VALUE(elf_file).size() > 0) {
|
||||
istringstream is(GET_PROP_VALUE(elf_file));
|
||||
@ -325,7 +332,8 @@ void core_complex::start_of_simulation() {
|
||||
}
|
||||
}
|
||||
|
||||
bool core_complex::disass_output(uint64_t pc, const std::string instr_str) {
|
||||
template <unsigned int BUSWIDTH>
|
||||
bool core_complex<BUSWIDTH>::disass_output(uint64_t pc, const std::string instr_str) {
|
||||
if(trc->m_db == nullptr)
|
||||
return false;
|
||||
if(trc->tr_handle.is_active())
|
||||
@ -339,7 +347,8 @@ bool core_complex::disass_output(uint64_t pc, const std::string instr_str) {
|
||||
return true;
|
||||
}
|
||||
|
||||
void core_complex::forward() {
|
||||
template <unsigned int BUSWIDTH>
|
||||
void core_complex<BUSWIDTH>::forward() {
|
||||
#ifndef CWR_SYSTEMC
|
||||
set_clock_period(clk_i.read());
|
||||
#else
|
||||
@ -348,24 +357,30 @@ void core_complex::forward() {
|
||||
#endif
|
||||
}
|
||||
|
||||
void core_complex::set_clock_period(sc_core::sc_time period) {
|
||||
template <unsigned int BUSWIDTH>
|
||||
void core_complex<BUSWIDTH>::set_clock_period(sc_core::sc_time period) {
|
||||
curr_clk = period;
|
||||
if(period == SC_ZERO_TIME)
|
||||
cpu->set_interrupt_execution(true);
|
||||
}
|
||||
|
||||
void core_complex::rst_cb() {
|
||||
template <unsigned int BUSWIDTH>
|
||||
void core_complex<BUSWIDTH>::rst_cb() {
|
||||
if(rst_i.read())
|
||||
cpu->set_interrupt_execution(true);
|
||||
}
|
||||
|
||||
void core_complex::sw_irq_cb() { cpu->local_irq(3, sw_irq_i.read()); }
|
||||
template <unsigned int BUSWIDTH>
|
||||
void core_complex<BUSWIDTH>::sw_irq_cb() { cpu->local_irq(3, sw_irq_i.read()); }
|
||||
|
||||
void core_complex::timer_irq_cb() { cpu->local_irq(7, timer_irq_i.read()); }
|
||||
template <unsigned int BUSWIDTH>
|
||||
void core_complex<BUSWIDTH>::timer_irq_cb() { cpu->local_irq(7, timer_irq_i.read()); }
|
||||
|
||||
void core_complex::ext_irq_cb() { cpu->local_irq(11, ext_irq_i.read()); }
|
||||
template <unsigned int BUSWIDTH>
|
||||
void core_complex<BUSWIDTH>::ext_irq_cb() { cpu->local_irq(11, ext_irq_i.read()); }
|
||||
|
||||
void core_complex::local_irq_cb() {
|
||||
template <unsigned int BUSWIDTH>
|
||||
void core_complex<BUSWIDTH>::local_irq_cb() {
|
||||
for(auto i = 0U; i < local_irq_i.size(); ++i) {
|
||||
if(local_irq_i[i].event()) {
|
||||
cpu->local_irq(16 + i, local_irq_i[i].read());
|
||||
@ -373,7 +388,8 @@ void core_complex::local_irq_cb() {
|
||||
}
|
||||
}
|
||||
|
||||
void core_complex::run() {
|
||||
template <unsigned int BUSWIDTH>
|
||||
void core_complex<BUSWIDTH>::run() {
|
||||
wait(SC_ZERO_TIME); // separate from elaboration phase
|
||||
do {
|
||||
wait(SC_ZERO_TIME);
|
||||
@ -391,7 +407,8 @@ void core_complex::run() {
|
||||
sc_stop();
|
||||
}
|
||||
|
||||
bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) {
|
||||
template <unsigned int BUSWIDTH>
|
||||
bool core_complex<BUSWIDTH>::read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) {
|
||||
auto& dmi_lut = is_fetch ? fetch_lut : read_lut;
|
||||
auto lut_entry = dmi_lut.getEntry(addr);
|
||||
if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && addr + length <= lut_entry.get_end_address() + 1) {
|
||||
@ -449,7 +466,8 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t* const data,
|
||||
}
|
||||
}
|
||||
|
||||
bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t* const data) {
|
||||
template <unsigned int BUSWIDTH>
|
||||
bool core_complex<BUSWIDTH>::write_mem(uint64_t addr, unsigned length, const uint8_t* const data) {
|
||||
auto lut_entry = write_lut.getEntry(addr);
|
||||
if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && addr + length <= lut_entry.get_end_address() + 1) {
|
||||
auto offset = addr - lut_entry.get_start_address();
|
||||
@ -497,7 +515,8 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t* cons
|
||||
}
|
||||
}
|
||||
|
||||
bool core_complex::read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) {
|
||||
template <unsigned int BUSWIDTH>
|
||||
bool core_complex<BUSWIDTH>::read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) {
|
||||
tlm::tlm_generic_payload gp;
|
||||
gp.set_command(tlm::TLM_READ_COMMAND);
|
||||
gp.set_address(addr);
|
||||
@ -507,7 +526,8 @@ bool core_complex::read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const d
|
||||
return dbus->transport_dbg(gp) == length;
|
||||
}
|
||||
|
||||
bool core_complex::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) {
|
||||
template <unsigned int BUSWIDTH>
|
||||
bool core_complex<BUSWIDTH>::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) {
|
||||
write_buf.resize(length);
|
||||
std::copy(data, data + length, write_buf.begin()); // need to copy as TLM does not guarantee data integrity
|
||||
tlm::tlm_generic_payload gp;
|
||||
@ -518,5 +538,10 @@ bool core_complex::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t*
|
||||
gp.set_streaming_width(length);
|
||||
return dbus->transport_dbg(gp) == length;
|
||||
}
|
||||
|
||||
template class core_complex<scc::LT>;
|
||||
template class core_complex<32>;
|
||||
template class core_complex<64>;
|
||||
|
||||
} /* namespace tgfs */
|
||||
} /* namespace sysc */
|
||||
|
||||
@ -36,14 +36,13 @@
|
||||
#include <scc/tick2time.h>
|
||||
#include <scc/traceable.h>
|
||||
#include <scc/utilities.h>
|
||||
#include <scc/signal_opt_ports.h>
|
||||
#include <tlm/scc/initiator_mixin.h>
|
||||
#include <tlm/scc/scv/tlm_rec_initiator_socket.h>
|
||||
#ifdef CWR_SYSTEMC
|
||||
#include <scmlinc/scml_property.h>
|
||||
#define SOCKET_WIDTH 32
|
||||
#else
|
||||
#include <cci_configuration>
|
||||
#define SOCKET_WIDTH scc::LT
|
||||
#endif
|
||||
#include <memory>
|
||||
#include <tlm>
|
||||
@ -68,12 +67,35 @@ public:
|
||||
namespace tgfs {
|
||||
class core_wrapper;
|
||||
struct core_trace;
|
||||
struct core_complex_if {
|
||||
|
||||
class core_complex : public sc_core::sc_module, public scc::traceable {
|
||||
virtual ~core_complex_if() = default;
|
||||
|
||||
virtual bool read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) =0;
|
||||
|
||||
virtual bool write_mem(uint64_t addr, unsigned length, const uint8_t* const data) =0;
|
||||
|
||||
virtual bool read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) =0;
|
||||
|
||||
virtual bool write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) =0;
|
||||
|
||||
virtual bool disass_output(uint64_t pc, const std::string instr) =0;
|
||||
|
||||
virtual unsigned get_last_bus_cycles() =0;
|
||||
|
||||
virtual void sync(uint64_t) =0;
|
||||
|
||||
virtual char const* hier_name() = 0;
|
||||
|
||||
scc::sc_in_opt<uint64_t> mtime_i{"mtime_i"};
|
||||
};
|
||||
|
||||
template <unsigned int BUSWIDTH = scc::LT>
|
||||
class core_complex : public sc_core::sc_module, public scc::traceable, public core_complex_if {
|
||||
public:
|
||||
tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<SOCKET_WIDTH>> ibus{"ibus"};
|
||||
tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<BUSWIDTH>> ibus{"ibus"};
|
||||
|
||||
tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<SOCKET_WIDTH>> dbus{"dbus"};
|
||||
tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<BUSWIDTH>> dbus{"dbus"};
|
||||
|
||||
sc_core::sc_in<bool> rst_i{"rst_i"};
|
||||
|
||||
@ -88,8 +110,6 @@ public:
|
||||
#ifndef CWR_SYSTEMC
|
||||
sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
|
||||
|
||||
sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o{"mtime_o"};
|
||||
|
||||
cci::cci_param<std::string> elf_file{"elf_file", ""};
|
||||
|
||||
cci::cci_param<bool> enable_disass{"enable_disass", false};
|
||||
@ -115,8 +135,6 @@ public:
|
||||
#else
|
||||
sc_core::sc_in<bool> clk_i{"clk_i"};
|
||||
|
||||
sc_core::sc_in<uint64_t> mtime_i{"mtime_i"};
|
||||
|
||||
scml_property<std::string> elf_file{"elf_file", ""};
|
||||
|
||||
scml_property<bool> enable_disass{"enable_disass", false};
|
||||
@ -159,13 +177,13 @@ public:
|
||||
|
||||
~core_complex();
|
||||
|
||||
inline unsigned get_last_bus_cycles() {
|
||||
unsigned get_last_bus_cycles() override {
|
||||
auto mem_incr = std::max(ibus_inc, dbus_inc);
|
||||
ibus_inc = dbus_inc = 0;
|
||||
return mem_incr > 1 ? mem_incr : 1;
|
||||
}
|
||||
|
||||
inline void sync(uint64_t cycle) {
|
||||
void sync(uint64_t cycle) override {
|
||||
auto core_inc = curr_clk * (cycle - last_sync_cycle);
|
||||
quantum_keeper.inc(core_inc);
|
||||
if(quantum_keeper.need_sync()) {
|
||||
@ -175,20 +193,24 @@ public:
|
||||
last_sync_cycle = cycle;
|
||||
}
|
||||
|
||||
bool read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch);
|
||||
bool read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) override;
|
||||
|
||||
bool write_mem(uint64_t addr, unsigned length, const uint8_t* const data);
|
||||
bool write_mem(uint64_t addr, unsigned length, const uint8_t* const data) override;
|
||||
|
||||
bool read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data);
|
||||
bool read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) override;
|
||||
|
||||
bool write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data);
|
||||
bool write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) override;
|
||||
|
||||
void trace(sc_core::sc_trace_file* trf) const override;
|
||||
|
||||
bool disass_output(uint64_t pc, const std::string instr);
|
||||
bool disass_output(uint64_t pc, const std::string instr) override;
|
||||
|
||||
void set_clock_period(sc_core::sc_time period);
|
||||
|
||||
char const* hier_name() override {
|
||||
return name();
|
||||
}
|
||||
|
||||
protected:
|
||||
void before_end_of_elaboration() override;
|
||||
void start_of_simulation() override;
|
||||
|
||||
@ -21,7 +21,7 @@ public:
|
||||
using reg_t = typename iss::arch::traits<typename PLAT::core>::reg_t;
|
||||
using phys_addr_t = typename iss::arch::traits<typename PLAT::core>::phys_addr_t;
|
||||
using heart_state_t = typename PLAT::hart_state_type;
|
||||
sc_core_adapter(sysc::tgfs::core_complex* owner)
|
||||
sc_core_adapter(sysc::tgfs::core_complex_if* owner)
|
||||
: owner(owner) {}
|
||||
|
||||
iss::arch_if* get_arch_if() override { return this; }
|
||||
@ -54,7 +54,7 @@ public:
|
||||
std::stringstream s;
|
||||
s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0') << std::setw(sizeof(reg_t) * 2)
|
||||
<< (reg_t)this->state.mstatus << std::dec << ";c:" << this->reg.icount + this->cycle_offset << "]";
|
||||
SCCDEBUG(owner->name()) << "disass: "
|
||||
SCCDEBUG(owner->hier_name()) << "disass: "
|
||||
<< "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
|
||||
<< std::setfill(' ') << std::left << instr << s.str();
|
||||
}
|
||||
@ -79,10 +79,10 @@ public:
|
||||
switch(hostvar >> 48) {
|
||||
case 0:
|
||||
if(hostvar != 0x1) {
|
||||
SCCINFO(owner->name())
|
||||
SCCINFO(owner->hier_name())
|
||||
<< "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation";
|
||||
} else {
|
||||
SCCINFO(owner->name())
|
||||
SCCINFO(owner->hier_name())
|
||||
<< "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation";
|
||||
}
|
||||
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
|
||||
@ -112,21 +112,8 @@ public:
|
||||
}
|
||||
|
||||
iss::status read_csr(unsigned addr, reg_t& val) override {
|
||||
#ifndef CWR_SYSTEMC
|
||||
if((addr == iss::arch::time || addr == iss::arch::timeh) && owner->mtime_o.get_interface(0)) {
|
||||
uint64_t time_val;
|
||||
bool ret = owner->mtime_o->nb_peek(time_val);
|
||||
if(addr == iss::arch::time) {
|
||||
val = static_cast<reg_t>(time_val);
|
||||
} else if(addr == iss::arch::timeh) {
|
||||
if(sizeof(reg_t) != 4)
|
||||
return iss::Err;
|
||||
val = static_cast<reg_t>(time_val >> 32);
|
||||
}
|
||||
return ret ? iss::Ok : iss::Err;
|
||||
#else
|
||||
if((addr == iss::arch::time || addr == iss::arch::timeh)) {
|
||||
uint64_t time_val = owner->mtime_i.read();
|
||||
uint64_t time_val = owner->mtime_i.get_interface()? owner->mtime_i.read():0;
|
||||
if(addr == iss::arch::time) {
|
||||
val = static_cast<reg_t>(time_val);
|
||||
} else if(addr == iss::arch::timeh) {
|
||||
@ -135,14 +122,13 @@ public:
|
||||
val = static_cast<reg_t>(time_val >> 32);
|
||||
}
|
||||
return iss::Ok;
|
||||
#endif
|
||||
} else {
|
||||
return PLAT::read_csr(addr, val);
|
||||
}
|
||||
}
|
||||
|
||||
void wait_until(uint64_t flags) override {
|
||||
SCCDEBUG(owner->name()) << "Sleeping until interrupt";
|
||||
SCCDEBUG(owner->hier_name()) << "Sleeping until interrupt";
|
||||
while(this->reg.pending_trap == 0 && (this->csr[iss::arch::mip] & this->csr[iss::arch::mie]) == 0) {
|
||||
sc_core::wait(wfi_evt);
|
||||
}
|
||||
@ -173,11 +159,11 @@ public:
|
||||
this->csr[iss::arch::mip] &= ~mask;
|
||||
this->check_interrupt();
|
||||
if(value)
|
||||
SCCTRACE(owner->name()) << "Triggering interrupt " << id << " Pending trap: " << this->reg.pending_trap;
|
||||
SCCTRACE(owner->hier_name()) << "Triggering interrupt " << id << " Pending trap: " << this->reg.pending_trap;
|
||||
}
|
||||
|
||||
private:
|
||||
sysc::tgfs::core_complex* const owner;
|
||||
sysc::tgfs::core_complex_if* const owner;
|
||||
sc_core::sc_event wfi_evt;
|
||||
uint64_t hostvar{std::numeric_limits<uint64_t>::max()};
|
||||
unsigned to_host_wr_cnt = 0;
|
||||
|
||||
@ -88,7 +88,6 @@ protected:
|
||||
using super::write_reg_to_mem;
|
||||
using super::gen_read_mem;
|
||||
using super::gen_write_mem;
|
||||
using super::gen_wait;
|
||||
using super::gen_leave;
|
||||
using super::gen_sync;
|
||||
|
||||
@ -113,6 +112,7 @@ protected:
|
||||
auto sign_mask = 1ULL<<(W-1);
|
||||
return (from & mask) | ((from & sign_mask) ? ~mask : 0);
|
||||
}
|
||||
|
||||
private:
|
||||
/****************************************************************************
|
||||
* start opcode definitions
|
||||
@ -500,6 +500,7 @@ private:
|
||||
(gen_operation(cc, band, (gen_operation(cc, add, load_reg_from_mem(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))
|
||||
), addr_mask)
|
||||
), 32, true);
|
||||
{
|
||||
auto label_merge = cc.newLabel();
|
||||
cmp(cc, gen_operation(cc, urem, new_pc, static_cast<uint32_t>(traits::INSTR_ALIGNMENT))
|
||||
,0);
|
||||
@ -522,6 +523,7 @@ private:
|
||||
}
|
||||
cc.bind(label_merge);
|
||||
}
|
||||
}
|
||||
auto returnValue = BRANCH;
|
||||
|
||||
gen_sync(jh, POST_SYNC, 3);
|
||||
@ -566,6 +568,7 @@ private:
|
||||
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
}
|
||||
else{
|
||||
{
|
||||
auto label_merge = cc.newLabel();
|
||||
cmp(cc, gen_operation(cc, eq, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
|
||||
,0);
|
||||
@ -584,6 +587,7 @@ private:
|
||||
}
|
||||
cc.bind(label_merge);
|
||||
}
|
||||
}
|
||||
auto returnValue = BRANCH;
|
||||
|
||||
gen_sync(jh, POST_SYNC, 4);
|
||||
@ -628,6 +632,7 @@ private:
|
||||
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
}
|
||||
else{
|
||||
{
|
||||
auto label_merge = cc.newLabel();
|
||||
cmp(cc, gen_operation(cc, ne, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
|
||||
,0);
|
||||
@ -646,6 +651,7 @@ private:
|
||||
}
|
||||
cc.bind(label_merge);
|
||||
}
|
||||
}
|
||||
auto returnValue = BRANCH;
|
||||
|
||||
gen_sync(jh, POST_SYNC, 5);
|
||||
@ -690,6 +696,7 @@ private:
|
||||
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
}
|
||||
else{
|
||||
{
|
||||
auto label_merge = cc.newLabel();
|
||||
cmp(cc, gen_operation(cc, lt, gen_ext(cc,
|
||||
load_reg_from_mem(jh, traits::X0 + rs1), 32, false), gen_ext(cc,
|
||||
@ -710,6 +717,7 @@ private:
|
||||
}
|
||||
cc.bind(label_merge);
|
||||
}
|
||||
}
|
||||
auto returnValue = BRANCH;
|
||||
|
||||
gen_sync(jh, POST_SYNC, 6);
|
||||
@ -754,6 +762,7 @@ private:
|
||||
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
}
|
||||
else{
|
||||
{
|
||||
auto label_merge = cc.newLabel();
|
||||
cmp(cc, gen_operation(cc, gte, gen_ext(cc,
|
||||
load_reg_from_mem(jh, traits::X0 + rs1), 32, false), gen_ext(cc,
|
||||
@ -774,6 +783,7 @@ private:
|
||||
}
|
||||
cc.bind(label_merge);
|
||||
}
|
||||
}
|
||||
auto returnValue = BRANCH;
|
||||
|
||||
gen_sync(jh, POST_SYNC, 7);
|
||||
@ -818,6 +828,7 @@ private:
|
||||
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
}
|
||||
else{
|
||||
{
|
||||
auto label_merge = cc.newLabel();
|
||||
cmp(cc, gen_operation(cc, ltu, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
|
||||
,0);
|
||||
@ -836,6 +847,7 @@ private:
|
||||
}
|
||||
cc.bind(label_merge);
|
||||
}
|
||||
}
|
||||
auto returnValue = BRANCH;
|
||||
|
||||
gen_sync(jh, POST_SYNC, 8);
|
||||
@ -880,6 +892,7 @@ private:
|
||||
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
}
|
||||
else{
|
||||
{
|
||||
auto label_merge = cc.newLabel();
|
||||
cmp(cc, gen_operation(cc, gteu, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
|
||||
,0);
|
||||
@ -898,6 +911,7 @@ private:
|
||||
}
|
||||
cc.bind(label_merge);
|
||||
}
|
||||
}
|
||||
auto returnValue = BRANCH;
|
||||
|
||||
gen_sync(jh, POST_SYNC, 9);
|
||||
@ -2364,7 +2378,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate disass */
|
||||
|
||||
//This disass is not yet implemented
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = "ecall";
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -2401,7 +2415,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate disass */
|
||||
|
||||
//This disass is not yet implemented
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = "ebreak";
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -2438,7 +2452,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate disass */
|
||||
|
||||
//This disass is not yet implemented
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = "mret";
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -2475,7 +2489,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate disass */
|
||||
|
||||
//This disass is not yet implemented
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = "wfi";
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -2497,7 +2511,10 @@ private:
|
||||
gen_instr_prologue(jh);
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
gen_wait(jh, 1);
|
||||
InvokeNode* call_wait;
|
||||
jh.cc.comment("//call_wait");
|
||||
jh.cc.invoke(&call_wait, &wait, FuncSignature::build<void, int32_t>());
|
||||
setArg(call_wait, 0, 1);
|
||||
auto returnValue = CONT;
|
||||
|
||||
gen_sync(jh, POST_SYNC, 41);
|
||||
@ -3116,6 +3133,7 @@ private:
|
||||
auto divisor = gen_ext(cc,
|
||||
load_reg_from_mem(jh, traits::X0 + rs2), 32, true);
|
||||
if(rd!=0){
|
||||
{
|
||||
auto label_merge = cc.newLabel();
|
||||
cmp(cc, gen_operation(cc, ne, divisor, 0)
|
||||
,0);
|
||||
@ -3123,6 +3141,7 @@ private:
|
||||
cc.je(label_else);
|
||||
{
|
||||
auto MMIN = ((uint32_t)1)<<(static_cast<uint32_t>(traits::XLEN)-1);
|
||||
{
|
||||
auto label_merge = cc.newLabel();
|
||||
cmp(cc, gen_operation(cc, land, gen_operation(cc, eq, load_reg_from_mem(jh, traits::X0 + rs1), MMIN)
|
||||
, gen_operation(cc, eq, divisor, - 1)
|
||||
@ -3144,6 +3163,7 @@ private:
|
||||
}
|
||||
cc.bind(label_merge);
|
||||
}
|
||||
}
|
||||
cc.jmp(label_merge);
|
||||
cc.bind(label_else);
|
||||
{
|
||||
@ -3153,6 +3173,7 @@ private:
|
||||
cc.bind(label_merge);
|
||||
}
|
||||
}
|
||||
}
|
||||
auto returnValue = CONT;
|
||||
|
||||
gen_sync(jh, POST_SYNC, 53);
|
||||
@ -3196,6 +3217,7 @@ private:
|
||||
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
}
|
||||
else{
|
||||
{
|
||||
auto label_merge = cc.newLabel();
|
||||
cmp(cc, gen_operation(cc, ne, load_reg_from_mem(jh, traits::X0 + rs2), 0)
|
||||
,0);
|
||||
@ -3218,6 +3240,7 @@ private:
|
||||
}
|
||||
cc.bind(label_merge);
|
||||
}
|
||||
}
|
||||
auto returnValue = CONT;
|
||||
|
||||
gen_sync(jh, POST_SYNC, 54);
|
||||
@ -3261,6 +3284,7 @@ private:
|
||||
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
}
|
||||
else{
|
||||
{
|
||||
auto label_merge = cc.newLabel();
|
||||
cmp(cc, gen_operation(cc, ne, load_reg_from_mem(jh, traits::X0 + rs2), 0)
|
||||
,0);
|
||||
@ -3268,6 +3292,7 @@ private:
|
||||
cc.je(label_else);
|
||||
{
|
||||
auto MMIN = (uint32_t)1<<(static_cast<uint32_t>(traits::XLEN)-1);
|
||||
{
|
||||
auto label_merge = cc.newLabel();
|
||||
cmp(cc, gen_operation(cc, land, gen_operation(cc, eq, load_reg_from_mem(jh, traits::X0 + rs1), MMIN)
|
||||
, gen_operation(cc, eq, gen_ext(cc,
|
||||
@ -3297,6 +3322,7 @@ private:
|
||||
}
|
||||
cc.bind(label_merge);
|
||||
}
|
||||
}
|
||||
cc.jmp(label_merge);
|
||||
cc.bind(label_else);
|
||||
{
|
||||
@ -3307,6 +3333,7 @@ private:
|
||||
}
|
||||
cc.bind(label_merge);
|
||||
}
|
||||
}
|
||||
auto returnValue = CONT;
|
||||
|
||||
gen_sync(jh, POST_SYNC, 55);
|
||||
@ -3350,6 +3377,7 @@ private:
|
||||
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
}
|
||||
else{
|
||||
{
|
||||
auto label_merge = cc.newLabel();
|
||||
cmp(cc, gen_operation(cc, ne, load_reg_from_mem(jh, traits::X0 + rs2), 0)
|
||||
,0);
|
||||
@ -3372,6 +3400,7 @@ private:
|
||||
}
|
||||
cc.bind(label_merge);
|
||||
}
|
||||
}
|
||||
auto returnValue = CONT;
|
||||
|
||||
gen_sync(jh, POST_SYNC, 56);
|
||||
@ -3388,7 +3417,7 @@ private:
|
||||
/* generate disass */
|
||||
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__addi4spn"),
|
||||
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.addi4spn"),
|
||||
fmt::arg("rd", name(8+rd)), fmt::arg("imm", imm));
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -3436,7 +3465,7 @@ private:
|
||||
/* generate disass */
|
||||
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__lw"),
|
||||
"{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.lw"),
|
||||
fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -3482,7 +3511,7 @@ private:
|
||||
/* generate disass */
|
||||
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__sw"),
|
||||
"{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.sw"),
|
||||
fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -3525,7 +3554,7 @@ private:
|
||||
/* generate disass */
|
||||
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__addi"),
|
||||
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.addi"),
|
||||
fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -3572,8 +3601,8 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate disass */
|
||||
|
||||
//This disass is not yet implemented
|
||||
std::string mnemonic = "c__nop";
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = "c.nop";
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
jh.disass_collection.push_back(mnemonic_ptr);
|
||||
@ -3609,7 +3638,7 @@ private:
|
||||
/* generate disass */
|
||||
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__jal"),
|
||||
"{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.jal"),
|
||||
fmt::arg("imm", imm));
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -3653,7 +3682,7 @@ private:
|
||||
/* generate disass */
|
||||
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__li"),
|
||||
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.li"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -3700,7 +3729,7 @@ private:
|
||||
/* generate disass */
|
||||
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__lui"),
|
||||
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.lui"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -3744,7 +3773,7 @@ private:
|
||||
/* generate disass */
|
||||
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c__addi16sp"),
|
||||
"{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c.addi16sp"),
|
||||
fmt::arg("nzimm", nzimm));
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -3789,8 +3818,8 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate disass */
|
||||
|
||||
//This disass is not yet implemented
|
||||
std::string mnemonic = "__reserved_clui";
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = ".reserved_clui";
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
jh.disass_collection.push_back(mnemonic_ptr);
|
||||
@ -3828,7 +3857,7 @@ private:
|
||||
/* generate disass */
|
||||
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srli"),
|
||||
"{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srli"),
|
||||
fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -3869,7 +3898,7 @@ private:
|
||||
/* generate disass */
|
||||
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srai"),
|
||||
"{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srai"),
|
||||
fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -3923,7 +3952,7 @@ private:
|
||||
/* generate disass */
|
||||
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__andi"),
|
||||
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.andi"),
|
||||
fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -3965,7 +3994,7 @@ private:
|
||||
/* generate disass */
|
||||
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__sub"),
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.sub"),
|
||||
fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -4007,7 +4036,7 @@ private:
|
||||
/* generate disass */
|
||||
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__xor"),
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.xor"),
|
||||
fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -4048,7 +4077,7 @@ private:
|
||||
/* generate disass */
|
||||
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__or"),
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.or"),
|
||||
fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -4089,7 +4118,7 @@ private:
|
||||
/* generate disass */
|
||||
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__and"),
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.and"),
|
||||
fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -4129,7 +4158,7 @@ private:
|
||||
/* generate disass */
|
||||
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__j"),
|
||||
"{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.j"),
|
||||
fmt::arg("imm", imm));
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -4171,7 +4200,7 @@ private:
|
||||
/* generate disass */
|
||||
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__beqz"),
|
||||
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.beqz"),
|
||||
fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -4194,6 +4223,7 @@ private:
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
mov(jh.cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(NO_JUMP));
|
||||
{
|
||||
auto label_merge = cc.newLabel();
|
||||
cmp(cc, gen_operation(cc, eq, load_reg_from_mem(jh, traits::X0 + rs1+8), 0)
|
||||
,0);
|
||||
@ -4204,6 +4234,7 @@ private:
|
||||
mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(KNOWN_JUMP));
|
||||
}
|
||||
cc.bind(label_merge);
|
||||
}
|
||||
auto returnValue = BRANCH;
|
||||
|
||||
gen_sync(jh, POST_SYNC, 75);
|
||||
@ -4220,7 +4251,7 @@ private:
|
||||
/* generate disass */
|
||||
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__bnez"),
|
||||
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.bnez"),
|
||||
fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -4243,6 +4274,7 @@ private:
|
||||
cc.comment("//behavior:");
|
||||
/*generate behavior*/
|
||||
mov(jh.cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(NO_JUMP));
|
||||
{
|
||||
auto label_merge = cc.newLabel();
|
||||
cmp(cc, gen_operation(cc, ne, load_reg_from_mem(jh, traits::X0 + rs1+8), 0)
|
||||
,0);
|
||||
@ -4253,6 +4285,7 @@ private:
|
||||
mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(KNOWN_JUMP));
|
||||
}
|
||||
cc.bind(label_merge);
|
||||
}
|
||||
auto returnValue = BRANCH;
|
||||
|
||||
gen_sync(jh, POST_SYNC, 76);
|
||||
@ -4269,7 +4302,7 @@ private:
|
||||
/* generate disass */
|
||||
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c__slli"),
|
||||
"{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c.slli"),
|
||||
fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm));
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -4317,7 +4350,7 @@ private:
|
||||
/* generate disass */
|
||||
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c__lwsp"),
|
||||
"{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c.lwsp"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm));
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -4367,7 +4400,7 @@ private:
|
||||
/* generate disass */
|
||||
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__mv"),
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.mv"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -4413,7 +4446,7 @@ private:
|
||||
/* generate disass */
|
||||
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jr"),
|
||||
"{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jr"),
|
||||
fmt::arg("rs1", name(rs1)));
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -4459,8 +4492,8 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate disass */
|
||||
|
||||
//This disass is not yet implemented
|
||||
std::string mnemonic = "__reserved_cmv";
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = ".reserved_cmv";
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
jh.disass_collection.push_back(mnemonic_ptr);
|
||||
@ -4498,7 +4531,7 @@ private:
|
||||
/* generate disass */
|
||||
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__add"),
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.add"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -4546,7 +4579,7 @@ private:
|
||||
/* generate disass */
|
||||
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jalr"),
|
||||
"{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jalr"),
|
||||
fmt::arg("rs1", name(rs1)));
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -4595,8 +4628,8 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate disass */
|
||||
|
||||
//This disass is not yet implemented
|
||||
std::string mnemonic = "c__ebreak";
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = "c.ebreak";
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
jh.disass_collection.push_back(mnemonic_ptr);
|
||||
@ -4634,7 +4667,7 @@ private:
|
||||
/* generate disass */
|
||||
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c__swsp"),
|
||||
"{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c.swsp"),
|
||||
fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm));
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -4679,7 +4712,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate disass */
|
||||
|
||||
//This disass is not yet implemented
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = "dii";
|
||||
InvokeNode* call_print_disass;
|
||||
char* mnemonic_ptr = strdup(mnemonic.c_str());
|
||||
@ -4735,7 +4768,7 @@ private:
|
||||
gen_raise(jh, 0, 2);
|
||||
gen_sync(jh, POST_SYNC, instr_descr.size());
|
||||
gen_instr_epilogue(jh);
|
||||
return BRANCH;
|
||||
return ILLEGAL_INSTR;
|
||||
}
|
||||
};
|
||||
|
||||
@ -4764,9 +4797,9 @@ continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned
|
||||
paddr = this->core.virt2phys(pc);
|
||||
auto res = this->core.read(paddr, 4, data);
|
||||
if (res != iss::Ok)
|
||||
throw trap_access(TRAP_ID, pc.val);
|
||||
return ILLEGAL_FETCH;
|
||||
if (instr == 0x0000006f || (instr&0xffff)==0xa001)
|
||||
throw simulation_stopped(0); // 'J 0' or 'C.J 0'
|
||||
return JUMP_TO_SELF;
|
||||
++inst_cnt;
|
||||
uint32_t inst_index = instr_decoder.decode_instr(instr);
|
||||
compile_func f = nullptr;
|
||||
|
||||
@ -128,7 +128,6 @@ uint32_t fcmp_s(uint32_t v1, uint32_t v2, uint32_t op) {
|
||||
}
|
||||
|
||||
uint32_t fcvt_s(uint32_t v1, uint32_t op, uint8_t mode) {
|
||||
|
||||
float32_t v1f{v1};
|
||||
softfloat_exceptionFlags = 0;
|
||||
float32_t r;
|
||||
|
||||
@ -343,7 +343,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
uint32_t inst_index = instr_decoder.decode_instr(instr);
|
||||
opcode_e inst_id = arch::traits<ARCH>::opcode_e::MAX_OPCODE;;
|
||||
if(inst_index <instr_descr.size())
|
||||
inst_id = instr_descr.at(instr_decoder.decode_instr(instr)).op;
|
||||
inst_id = instr_descr[inst_index].op;
|
||||
|
||||
// pre execution stuff
|
||||
this->core.reg.last_branch = 0;
|
||||
@ -1458,7 +1458,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
case arch::traits<ARCH>::opcode_e::ECALL: {
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
this->core.disass_output(pc.val, "ecall");
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = "ecall";
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
}
|
||||
// used registers// calculate next pc value
|
||||
*NEXT_PC = *PC + 4;
|
||||
@ -1471,7 +1473,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
case arch::traits<ARCH>::opcode_e::EBREAK: {
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
this->core.disass_output(pc.val, "ebreak");
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = "ebreak";
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
}
|
||||
// used registers// calculate next pc value
|
||||
*NEXT_PC = *PC + 4;
|
||||
@ -1484,7 +1488,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
case arch::traits<ARCH>::opcode_e::MRET: {
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
this->core.disass_output(pc.val, "mret");
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = "mret";
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
}
|
||||
// used registers// calculate next pc value
|
||||
*NEXT_PC = *PC + 4;
|
||||
@ -1497,7 +1503,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
case arch::traits<ARCH>::opcode_e::WFI: {
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
this->core.disass_output(pc.val, "wfi");
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = "wfi";
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
}
|
||||
// used registers// calculate next pc value
|
||||
*NEXT_PC = *PC + 4;
|
||||
@ -1721,7 +1729,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence.i"),
|
||||
"{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"),
|
||||
fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
}
|
||||
@ -2095,7 +2103,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
this->core.disass_output(pc.val, "c.nop");
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = "c.nop";
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
}
|
||||
// used registers// calculate next pc value
|
||||
*NEXT_PC = *PC + 2;
|
||||
@ -2201,7 +2211,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
uint8_t rd = ((bit_sub<7,5>(instr)));
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
this->core.disass_output(pc.val, ".reserved_clui");
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = ".reserved_clui";
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
}
|
||||
// used registers// calculate next pc value
|
||||
*NEXT_PC = *PC + 2;
|
||||
@ -2520,7 +2532,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
case arch::traits<ARCH>::opcode_e::__reserved_cmv: {
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
this->core.disass_output(pc.val, ".reserved_cmv");
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = ".reserved_cmv";
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
}
|
||||
// used registers// calculate next pc value
|
||||
*NEXT_PC = *PC + 2;
|
||||
@ -2586,7 +2600,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
case arch::traits<ARCH>::opcode_e::C__EBREAK: {
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
this->core.disass_output(pc.val, "c.ebreak");
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = "c.ebreak";
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
}
|
||||
// used registers// calculate next pc value
|
||||
*NEXT_PC = *PC + 2;
|
||||
@ -2625,7 +2641,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
case arch::traits<ARCH>::opcode_e::DII: {
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
this->core.disass_output(pc.val, "dii");
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = "dii";
|
||||
this->core.disass_output(pc.val, mnemonic);
|
||||
}
|
||||
// used registers// calculate next pc value
|
||||
*NEXT_PC = *PC + 2;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -98,8 +98,6 @@ protected:
|
||||
|
||||
void gen_leave_trap(tu_builder& tu, unsigned lvl);
|
||||
|
||||
void gen_wait(tu_builder& tu, unsigned type);
|
||||
|
||||
inline void gen_set_tval(tu_builder& tu, uint64_t new_tval);
|
||||
|
||||
inline void gen_set_tval(tu_builder& tu, value new_tval);
|
||||
@ -133,6 +131,7 @@ protected:
|
||||
return (from & mask) | ((from & sign_mask) ? ~mask : 0);
|
||||
}
|
||||
|
||||
|
||||
private:
|
||||
/****************************************************************************
|
||||
* start opcode definitions
|
||||
@ -350,8 +349,7 @@ private:
|
||||
}
|
||||
else{
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.constant((uint32_t)((int32_t)imm),32));
|
||||
tu.store(rd + traits::X0, tu.constant((uint32_t)((int32_t)imm),32));
|
||||
}
|
||||
}
|
||||
auto returnValue = std::make_tuple(CONT);
|
||||
@ -386,8 +384,7 @@ private:
|
||||
}
|
||||
else{
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.constant((uint32_t)(PC+(int32_t)imm),32));
|
||||
tu.store(rd + traits::X0, tu.constant((uint32_t)(PC+(int32_t)imm),32));
|
||||
}
|
||||
}
|
||||
auto returnValue = std::make_tuple(CONT);
|
||||
@ -428,8 +425,7 @@ private:
|
||||
}
|
||||
else{
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.constant((uint32_t)(PC+4),32));
|
||||
tu.store(rd + traits::X0, tu.constant((uint32_t)(PC+4),32));
|
||||
}
|
||||
auto PC_val_v = tu.assignment("PC_val", new_pc,32);
|
||||
tu.store(traits::NEXT_PC, PC_val_v);
|
||||
@ -482,8 +478,7 @@ private:
|
||||
this->gen_raise_trap(tu, 0, 0);
|
||||
tu.open_else();
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.constant((uint32_t)(PC+4),32));
|
||||
tu.store(rd + traits::X0, tu.constant((uint32_t)(PC+4),32));
|
||||
}
|
||||
auto PC_val_v = tu.assignment("PC_val", new_pc,32);
|
||||
tu.store(traits::NEXT_PC, PC_val_v);
|
||||
@ -809,8 +804,7 @@ private:
|
||||
tu.constant((int16_t)sext<12>(imm),16))),32,false),32);
|
||||
auto res = tu.assignment(tu.ext(tu.read_mem(traits::MEM, load_address, 8),8,true),8);
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.ext(res,32,false));
|
||||
tu.store(rd + traits::X0, tu.ext(res,32,false));
|
||||
}
|
||||
}
|
||||
auto returnValue = std::make_tuple(CONT);
|
||||
@ -850,8 +844,7 @@ private:
|
||||
tu.constant((int16_t)sext<12>(imm),16))),32,false),32);
|
||||
auto res = tu.assignment(tu.ext(tu.read_mem(traits::MEM, load_address, 16),16,true),16);
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.ext(res,32,false));
|
||||
tu.store(rd + traits::X0, tu.ext(res,32,false));
|
||||
}
|
||||
}
|
||||
auto returnValue = std::make_tuple(CONT);
|
||||
@ -891,8 +884,7 @@ private:
|
||||
tu.constant((int16_t)sext<12>(imm),16))),32,false),32);
|
||||
auto res = tu.assignment(tu.ext(tu.read_mem(traits::MEM, load_address, 32),32,true),32);
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.ext(res,32,false));
|
||||
tu.store(rd + traits::X0, tu.ext(res,32,false));
|
||||
}
|
||||
}
|
||||
auto returnValue = std::make_tuple(CONT);
|
||||
@ -932,8 +924,7 @@ private:
|
||||
tu.constant((int16_t)sext<12>(imm),16))),32,false),32);
|
||||
auto res = tu.assignment(tu.read_mem(traits::MEM, load_address, 8),8);
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.ext(res,32,false));
|
||||
tu.store(rd + traits::X0, tu.ext(res,32,false));
|
||||
}
|
||||
}
|
||||
auto returnValue = std::make_tuple(CONT);
|
||||
@ -973,8 +964,7 @@ private:
|
||||
tu.constant((int16_t)sext<12>(imm),16))),32,false),32);
|
||||
auto res = tu.assignment(tu.read_mem(traits::MEM, load_address, 16),16);
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.ext(res,32,false));
|
||||
tu.store(rd + traits::X0, tu.ext(res,32,false));
|
||||
}
|
||||
}
|
||||
auto returnValue = std::make_tuple(CONT);
|
||||
@ -1121,8 +1111,7 @@ private:
|
||||
}
|
||||
else{
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.ext((tu.add(
|
||||
tu.store(rd + traits::X0, tu.ext((tu.add(
|
||||
tu.load(rs1 + traits::X0, 0),
|
||||
tu.constant((int16_t)sext<12>(imm),16))),32,false));
|
||||
}
|
||||
@ -1160,8 +1149,7 @@ private:
|
||||
}
|
||||
else{
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.conditionalAssignment((tu.icmp(ICmpInst::ICMP_SLT,
|
||||
tu.store(rd + traits::X0, tu.conditionalAssignment((tu.icmp(ICmpInst::ICMP_SLT,
|
||||
tu.ext(tu.load(rs1 + traits::X0, 0),32,true),
|
||||
tu.constant((int16_t)sext<12>(imm),16))), tu.constant(1,8),tu.constant(0,8)));
|
||||
}
|
||||
@ -1199,8 +1187,7 @@ private:
|
||||
}
|
||||
else{
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.conditionalAssignment((tu.icmp(ICmpInst::ICMP_ULT,
|
||||
tu.store(rd + traits::X0, tu.conditionalAssignment((tu.icmp(ICmpInst::ICMP_ULT,
|
||||
tu.load(rs1 + traits::X0, 0),
|
||||
tu.constant((uint32_t)((int16_t)sext<12>(imm)),32))), tu.constant(1,8),tu.constant(0,8)));
|
||||
}
|
||||
@ -1238,8 +1225,7 @@ private:
|
||||
}
|
||||
else{
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.bitwise_xor(
|
||||
tu.store(rd + traits::X0, tu.bitwise_xor(
|
||||
tu.load(rs1 + traits::X0, 0),
|
||||
tu.constant((uint32_t)((int16_t)sext<12>(imm)),32)));
|
||||
}
|
||||
@ -1277,8 +1263,7 @@ private:
|
||||
}
|
||||
else{
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.bitwise_or(
|
||||
tu.store(rd + traits::X0, tu.bitwise_or(
|
||||
tu.load(rs1 + traits::X0, 0),
|
||||
tu.constant((uint32_t)((int16_t)sext<12>(imm)),32)));
|
||||
}
|
||||
@ -1316,8 +1301,7 @@ private:
|
||||
}
|
||||
else{
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.bitwise_and(
|
||||
tu.store(rd + traits::X0, tu.bitwise_and(
|
||||
tu.load(rs1 + traits::X0, 0),
|
||||
tu.constant((uint32_t)((int16_t)sext<12>(imm)),32)));
|
||||
}
|
||||
@ -1355,8 +1339,7 @@ private:
|
||||
}
|
||||
else{
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.shl(
|
||||
tu.store(rd + traits::X0, tu.shl(
|
||||
tu.load(rs1 + traits::X0, 0),
|
||||
tu.constant(shamt,8)));
|
||||
}
|
||||
@ -1394,8 +1377,7 @@ private:
|
||||
}
|
||||
else{
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.lshr(
|
||||
tu.store(rd + traits::X0, tu.lshr(
|
||||
tu.load(rs1 + traits::X0, 0),
|
||||
tu.constant(shamt,8)));
|
||||
}
|
||||
@ -1433,8 +1415,7 @@ private:
|
||||
}
|
||||
else{
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.ext((tu.ashr(
|
||||
tu.store(rd + traits::X0, tu.ext((tu.ashr(
|
||||
tu.ext(tu.load(rs1 + traits::X0, 0),32,true),
|
||||
tu.constant(shamt,8))),32,false));
|
||||
}
|
||||
@ -1472,8 +1453,7 @@ private:
|
||||
}
|
||||
else{
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.ext((tu.add(
|
||||
tu.store(rd + traits::X0, tu.ext((tu.add(
|
||||
tu.load(rs1 + traits::X0, 0),
|
||||
tu.load(rs2 + traits::X0, 0))),32,false));
|
||||
}
|
||||
@ -1511,8 +1491,7 @@ private:
|
||||
}
|
||||
else{
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.ext((tu.sub(
|
||||
tu.store(rd + traits::X0, tu.ext((tu.sub(
|
||||
tu.load(rs1 + traits::X0, 0),
|
||||
tu.load(rs2 + traits::X0, 0))),32,false));
|
||||
}
|
||||
@ -1550,8 +1529,7 @@ private:
|
||||
}
|
||||
else{
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.shl(
|
||||
tu.store(rd + traits::X0, tu.shl(
|
||||
tu.load(rs1 + traits::X0, 0),
|
||||
(tu.bitwise_and(
|
||||
tu.load(rs2 + traits::X0, 0),
|
||||
@ -1591,8 +1569,7 @@ private:
|
||||
}
|
||||
else{
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.conditionalAssignment(tu.icmp(ICmpInst::ICMP_SLT,
|
||||
tu.store(rd + traits::X0, tu.conditionalAssignment(tu.icmp(ICmpInst::ICMP_SLT,
|
||||
tu.ext(tu.load(rs1 + traits::X0, 0),32,true),
|
||||
tu.ext(tu.load(rs2 + traits::X0, 0),32,true)), tu.constant(1,8),tu.constant(0,8)));
|
||||
}
|
||||
@ -1630,8 +1607,7 @@ private:
|
||||
}
|
||||
else{
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.conditionalAssignment(tu.icmp(ICmpInst::ICMP_ULT,
|
||||
tu.store(rd + traits::X0, tu.conditionalAssignment(tu.icmp(ICmpInst::ICMP_ULT,
|
||||
tu.load(rs1 + traits::X0, 0),
|
||||
tu.load(rs2 + traits::X0, 0)), tu.constant(1,8),tu.constant(0,8)));
|
||||
}
|
||||
@ -1669,8 +1645,7 @@ private:
|
||||
}
|
||||
else{
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.bitwise_xor(
|
||||
tu.store(rd + traits::X0, tu.bitwise_xor(
|
||||
tu.load(rs1 + traits::X0, 0),
|
||||
tu.load(rs2 + traits::X0, 0)));
|
||||
}
|
||||
@ -1708,8 +1683,7 @@ private:
|
||||
}
|
||||
else{
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.lshr(
|
||||
tu.store(rd + traits::X0, tu.lshr(
|
||||
tu.load(rs1 + traits::X0, 0),
|
||||
(tu.bitwise_and(
|
||||
tu.load(rs2 + traits::X0, 0),
|
||||
@ -1749,8 +1723,7 @@ private:
|
||||
}
|
||||
else{
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.ext((tu.ashr(
|
||||
tu.store(rd + traits::X0, tu.ext((tu.ashr(
|
||||
tu.ext(tu.load(rs1 + traits::X0, 0),32,true),
|
||||
(tu.bitwise_and(
|
||||
tu.load(rs2 + traits::X0, 0),
|
||||
@ -1790,8 +1763,7 @@ private:
|
||||
}
|
||||
else{
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.bitwise_or(
|
||||
tu.store(rd + traits::X0, tu.bitwise_or(
|
||||
tu.load(rs1 + traits::X0, 0),
|
||||
tu.load(rs2 + traits::X0, 0)));
|
||||
}
|
||||
@ -1829,8 +1801,7 @@ private:
|
||||
}
|
||||
else{
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.bitwise_and(
|
||||
tu.store(rd + traits::X0, tu.bitwise_and(
|
||||
tu.load(rs1 + traits::X0, 0),
|
||||
tu.load(rs2 + traits::X0, 0)));
|
||||
}
|
||||
@ -1881,7 +1852,9 @@ private:
|
||||
uint64_t PC = pc.val;
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "ecall");
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = "ecall";
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
|
||||
pc=pc+ 4;
|
||||
@ -1905,7 +1878,9 @@ private:
|
||||
uint64_t PC = pc.val;
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "ebreak");
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = "ebreak";
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
|
||||
pc=pc+ 4;
|
||||
@ -1929,7 +1904,9 @@ private:
|
||||
uint64_t PC = pc.val;
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "mret");
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = "mret";
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
|
||||
pc=pc+ 4;
|
||||
@ -1953,14 +1930,16 @@ private:
|
||||
uint64_t PC = pc.val;
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "wfi");
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = "wfi";
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
|
||||
pc=pc+ 4;
|
||||
gen_set_pc(tu, pc, traits::NEXT_PC);
|
||||
tu.open_scope();
|
||||
this->gen_set_tval(tu, instr);
|
||||
this->gen_wait(tu, 1);
|
||||
tu.callf("wait", tu.constant(1,8));
|
||||
auto returnValue = std::make_tuple(CONT);
|
||||
|
||||
tu.close_scope();
|
||||
@ -1996,8 +1975,7 @@ private:
|
||||
auto xrs1 = tu.assignment(tu.load(rs1 + traits::X0, 0),32);
|
||||
if(rd!=0){ auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32);
|
||||
tu.write_mem(traits::CSR, csr, xrs1);
|
||||
tu.store(rd + traits::X0,
|
||||
xrd);
|
||||
tu.store(rd + traits::X0, xrd);
|
||||
}
|
||||
else{
|
||||
tu.write_mem(traits::CSR, csr, xrs1);
|
||||
@ -2043,8 +2021,7 @@ private:
|
||||
xrs1));
|
||||
}
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
xrd);
|
||||
tu.store(rd + traits::X0, xrd);
|
||||
}
|
||||
}
|
||||
auto returnValue = std::make_tuple(CONT);
|
||||
@ -2087,8 +2064,7 @@ private:
|
||||
tu.logical_neg(xrs1)));
|
||||
}
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
xrd);
|
||||
tu.store(rd + traits::X0, xrd);
|
||||
}
|
||||
}
|
||||
auto returnValue = std::make_tuple(CONT);
|
||||
@ -2126,8 +2102,7 @@ private:
|
||||
auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32);
|
||||
tu.write_mem(traits::CSR, csr, tu.constant((uint32_t)zimm,32));
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
xrd);
|
||||
tu.store(rd + traits::X0, xrd);
|
||||
}
|
||||
}
|
||||
auto returnValue = std::make_tuple(CONT);
|
||||
@ -2169,8 +2144,7 @@ private:
|
||||
tu.constant((uint32_t)zimm,32)));
|
||||
}
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
xrd);
|
||||
tu.store(rd + traits::X0, xrd);
|
||||
}
|
||||
}
|
||||
auto returnValue = std::make_tuple(CONT);
|
||||
@ -2212,8 +2186,7 @@ private:
|
||||
tu.constant(~ ((uint32_t)zimm),32)));
|
||||
}
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
xrd);
|
||||
tu.store(rd + traits::X0, xrd);
|
||||
}
|
||||
}
|
||||
auto returnValue = std::make_tuple(CONT);
|
||||
@ -2281,8 +2254,7 @@ private:
|
||||
tu.ext(tu.load(rs1 + traits::X0, 0),32,true),
|
||||
tu.ext(tu.load(rs2 + traits::X0, 0),32,true)),64);
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.ext(res,32,false));
|
||||
tu.store(rd + traits::X0, tu.ext(res,32,false));
|
||||
}
|
||||
}
|
||||
auto returnValue = std::make_tuple(CONT);
|
||||
@ -2321,8 +2293,7 @@ private:
|
||||
tu.ext(tu.load(rs1 + traits::X0, 0),32,true),
|
||||
tu.ext(tu.load(rs2 + traits::X0, 0),32,true)),64);
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.ext((tu.ashr(
|
||||
tu.store(rd + traits::X0, tu.ext((tu.ashr(
|
||||
res,
|
||||
tu.constant(static_cast<uint32_t>(traits:: XLEN),32))),32,false));
|
||||
}
|
||||
@ -2363,8 +2334,7 @@ private:
|
||||
tu.ext(tu.load(rs1 + traits::X0, 0),32,true),
|
||||
tu.load(rs2 + traits::X0, 0)),64);
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.ext((tu.ashr(
|
||||
tu.store(rd + traits::X0, tu.ext((tu.ashr(
|
||||
res,
|
||||
tu.constant(static_cast<uint32_t>(traits:: XLEN),32))),32,false));
|
||||
}
|
||||
@ -2405,8 +2375,7 @@ private:
|
||||
tu.load(rs1 + traits::X0, 0),
|
||||
tu.load(rs2 + traits::X0, 0)),64);
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.ext((tu.lshr(
|
||||
tu.store(rd + traits::X0, tu.ext((tu.lshr(
|
||||
res,
|
||||
tu.constant(static_cast<uint32_t>(traits:: XLEN),32))),32,false));
|
||||
}
|
||||
@ -2456,17 +2425,14 @@ private:
|
||||
tu.icmp(ICmpInst::ICMP_EQ,
|
||||
divisor,
|
||||
tu.constant(- 1,8))));
|
||||
tu.store(rd + traits::X0,
|
||||
tu.constant(MMIN,32));
|
||||
tu.store(rd + traits::X0, tu.constant(MMIN,32));
|
||||
tu.open_else();
|
||||
tu.store(rd + traits::X0,
|
||||
tu.ext((tu.sdiv(
|
||||
tu.store(rd + traits::X0, tu.ext((tu.sdiv(
|
||||
dividend,
|
||||
divisor)),32,false));
|
||||
tu.close_scope();
|
||||
tu.open_else();
|
||||
tu.store(rd + traits::X0,
|
||||
tu.constant((uint32_t)- 1,32));
|
||||
tu.store(rd + traits::X0, tu.constant((uint32_t)- 1,32));
|
||||
tu.close_scope();
|
||||
}
|
||||
}
|
||||
@ -2506,15 +2472,13 @@ private:
|
||||
tu.load(rs2 + traits::X0, 0),
|
||||
tu.constant(0,8)));
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.udiv(
|
||||
tu.store(rd + traits::X0, tu.udiv(
|
||||
tu.load(rs1 + traits::X0, 0),
|
||||
tu.load(rs2 + traits::X0, 0)));
|
||||
}
|
||||
tu.open_else();
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.constant((uint32_t)- 1,32));
|
||||
tu.store(rd + traits::X0, tu.constant((uint32_t)- 1,32));
|
||||
}
|
||||
tu.close_scope();
|
||||
}
|
||||
@ -2562,21 +2526,18 @@ private:
|
||||
tu.ext(tu.load(rs2 + traits::X0, 0),32,true),
|
||||
tu.constant(- 1,8))));
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.constant(0,8));
|
||||
tu.store(rd + traits::X0, tu.constant(0,8));
|
||||
}
|
||||
tu.open_else();
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.ext((tu.srem(
|
||||
tu.store(rd + traits::X0, tu.ext((tu.srem(
|
||||
tu.ext(tu.load(rs1 + traits::X0, 0),32,true),
|
||||
tu.ext(tu.load(rs2 + traits::X0, 0),32,true))),32,false));
|
||||
}
|
||||
tu.close_scope();
|
||||
tu.open_else();
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.load(rs1+ traits::X0, 0));
|
||||
tu.store(rd + traits::X0, tu.load(rs1 + traits::X0, 0));
|
||||
}
|
||||
tu.close_scope();
|
||||
}
|
||||
@ -2616,15 +2577,13 @@ private:
|
||||
tu.load(rs2 + traits::X0, 0),
|
||||
tu.constant(0,8)));
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.urem(
|
||||
tu.store(rd + traits::X0, tu.urem(
|
||||
tu.load(rs1 + traits::X0, 0),
|
||||
tu.load(rs2 + traits::X0, 0)));
|
||||
}
|
||||
tu.open_else();
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.load(rs1+ traits::X0, 0));
|
||||
tu.store(rd + traits::X0, tu.load(rs1 + traits::X0, 0));
|
||||
}
|
||||
tu.close_scope();
|
||||
}
|
||||
@ -2646,7 +2605,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__addi4spn"),
|
||||
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.addi4spn"),
|
||||
fmt::arg("rd", name(8+rd)), fmt::arg("imm", imm));
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
@ -2656,8 +2615,7 @@ private:
|
||||
tu.open_scope();
|
||||
this->gen_set_tval(tu, instr);
|
||||
if(imm) {
|
||||
tu.store(rd+8 + traits::X0,
|
||||
tu.ext((tu.add(
|
||||
tu.store(rd+8 + traits::X0, tu.ext((tu.add(
|
||||
tu.load(2 + traits::X0, 0),
|
||||
tu.constant(imm,16))),32,false));
|
||||
}
|
||||
@ -2683,7 +2641,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__lw"),
|
||||
"{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.lw"),
|
||||
fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
@ -2695,8 +2653,7 @@ private:
|
||||
auto offs = tu.assignment(tu.ext((tu.add(
|
||||
tu.load(rs1+8 + traits::X0, 0),
|
||||
tu.constant(uimm,8))),32,false),32);
|
||||
tu.store(rd+8 + traits::X0,
|
||||
tu.ext(tu.ext(tu.read_mem(traits::MEM, offs, 32),32,true),32,false));
|
||||
tu.store(rd+8 + traits::X0, tu.ext(tu.ext(tu.read_mem(traits::MEM, offs, 32),32,true),32,false));
|
||||
auto returnValue = std::make_tuple(CONT);
|
||||
|
||||
tu.close_scope();
|
||||
@ -2716,7 +2673,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__sw"),
|
||||
"{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.sw"),
|
||||
fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
@ -2747,7 +2704,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__addi"),
|
||||
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.addi"),
|
||||
fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
@ -2761,8 +2718,7 @@ private:
|
||||
}
|
||||
else{
|
||||
if(rs1!=0) {
|
||||
tu.store(rs1 + traits::X0,
|
||||
tu.ext((tu.add(
|
||||
tu.store(rs1 + traits::X0, tu.ext((tu.add(
|
||||
tu.load(rs1 + traits::X0, 0),
|
||||
tu.constant((int8_t)sext<6>(imm),8))),32,false));
|
||||
}
|
||||
@ -2783,7 +2739,9 @@ private:
|
||||
uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "c__nop");
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = "c.nop";
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
|
||||
pc=pc+ 2;
|
||||
@ -2807,7 +2765,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__jal"),
|
||||
"{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.jal"),
|
||||
fmt::arg("imm", imm));
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
@ -2817,8 +2775,7 @@ private:
|
||||
tu.open_scope();
|
||||
this->gen_set_tval(tu, instr);
|
||||
tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(NO_JUMP),32));
|
||||
tu.store(1 + traits::X0,
|
||||
tu.constant((uint32_t)(PC+2),32));
|
||||
tu.store(1 + traits::X0, tu.constant((uint32_t)(PC+2),32));
|
||||
auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<12>(imm)),32);
|
||||
tu.store(traits::NEXT_PC, PC_val_v);
|
||||
tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(KNOWN_JUMP), 2));
|
||||
@ -2840,7 +2797,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__li"),
|
||||
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.li"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
@ -2854,8 +2811,7 @@ private:
|
||||
}
|
||||
else{
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.constant((uint32_t)((int8_t)sext<6>(imm)),32));
|
||||
tu.store(rd + traits::X0, tu.constant((uint32_t)((int8_t)sext<6>(imm)),32));
|
||||
}
|
||||
}
|
||||
auto returnValue = std::make_tuple(CONT);
|
||||
@ -2876,7 +2832,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__lui"),
|
||||
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.lui"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
@ -2889,8 +2845,7 @@ private:
|
||||
this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
}
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.constant((uint32_t)((int32_t)sext<18>(imm)),32));
|
||||
tu.store(rd + traits::X0, tu.constant((uint32_t)((int32_t)sext<18>(imm)),32));
|
||||
}
|
||||
auto returnValue = std::make_tuple(CONT);
|
||||
|
||||
@ -2909,7 +2864,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c__addi16sp"),
|
||||
"{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c.addi16sp"),
|
||||
fmt::arg("nzimm", nzimm));
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
@ -2919,8 +2874,7 @@ private:
|
||||
tu.open_scope();
|
||||
this->gen_set_tval(tu, instr);
|
||||
if(nzimm) {
|
||||
tu.store(2 + traits::X0,
|
||||
tu.ext((tu.add(
|
||||
tu.store(2 + traits::X0, tu.ext((tu.add(
|
||||
tu.load(2 + traits::X0, 0),
|
||||
tu.constant((int16_t)sext<10>(nzimm),16))),32,false));
|
||||
}
|
||||
@ -2943,7 +2897,9 @@ private:
|
||||
uint8_t rd = ((bit_sub<7,5>(instr)));
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "__reserved_clui");
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = ".reserved_clui";
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
|
||||
pc=pc+ 2;
|
||||
@ -2969,7 +2925,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srli"),
|
||||
"{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srli"),
|
||||
fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
@ -2978,8 +2934,7 @@ private:
|
||||
gen_set_pc(tu, pc, traits::NEXT_PC);
|
||||
tu.open_scope();
|
||||
this->gen_set_tval(tu, instr);
|
||||
tu.store(rs1+8 + traits::X0,
|
||||
tu.lshr(
|
||||
tu.store(rs1+8 + traits::X0, tu.lshr(
|
||||
tu.load(rs1+8 + traits::X0, 0),
|
||||
tu.constant(shamt,8)));
|
||||
auto returnValue = std::make_tuple(CONT);
|
||||
@ -3000,7 +2955,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srai"),
|
||||
"{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srai"),
|
||||
fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
@ -3009,14 +2964,12 @@ private:
|
||||
gen_set_pc(tu, pc, traits::NEXT_PC);
|
||||
tu.open_scope();
|
||||
this->gen_set_tval(tu, instr);
|
||||
if(shamt){ tu.store(rs1+8 + traits::X0,
|
||||
tu.ext((tu.ashr(
|
||||
if(shamt){ tu.store(rs1+8 + traits::X0, tu.ext((tu.ashr(
|
||||
(tu.ext(tu.load(rs1+8 + traits::X0, 0),32,true)),
|
||||
tu.constant(shamt,8))),32,false));
|
||||
}
|
||||
else{
|
||||
if(static_cast<uint32_t>(traits:: XLEN)==128){ tu.store(rs1+8 + traits::X0,
|
||||
tu.ext((tu.ashr(
|
||||
if(static_cast<uint32_t>(traits:: XLEN)==128){ tu.store(rs1+8 + traits::X0, tu.ext((tu.ashr(
|
||||
(tu.ext(tu.load(rs1+8 + traits::X0, 0),32,true)),
|
||||
tu.constant(64,8))),32,false));
|
||||
}
|
||||
@ -3039,7 +2992,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__andi"),
|
||||
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.andi"),
|
||||
fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
@ -3048,8 +3001,7 @@ private:
|
||||
gen_set_pc(tu, pc, traits::NEXT_PC);
|
||||
tu.open_scope();
|
||||
this->gen_set_tval(tu, instr);
|
||||
tu.store(rs1+8 + traits::X0,
|
||||
tu.ext((tu.bitwise_and(
|
||||
tu.store(rs1+8 + traits::X0, tu.ext((tu.bitwise_and(
|
||||
tu.load(rs1+8 + traits::X0, 0),
|
||||
tu.constant((int8_t)sext<6>(imm),8))),32,false));
|
||||
auto returnValue = std::make_tuple(CONT);
|
||||
@ -3070,7 +3022,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__sub"),
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.sub"),
|
||||
fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
@ -3079,8 +3031,7 @@ private:
|
||||
gen_set_pc(tu, pc, traits::NEXT_PC);
|
||||
tu.open_scope();
|
||||
this->gen_set_tval(tu, instr);
|
||||
tu.store(rd+8 + traits::X0,
|
||||
tu.ext((tu.sub(
|
||||
tu.store(rd+8 + traits::X0, tu.ext((tu.sub(
|
||||
tu.load(rd+8 + traits::X0, 0),
|
||||
tu.load(rs2+8 + traits::X0, 0))),32,false));
|
||||
auto returnValue = std::make_tuple(CONT);
|
||||
@ -3101,7 +3052,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__xor"),
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.xor"),
|
||||
fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
@ -3110,8 +3061,7 @@ private:
|
||||
gen_set_pc(tu, pc, traits::NEXT_PC);
|
||||
tu.open_scope();
|
||||
this->gen_set_tval(tu, instr);
|
||||
tu.store(rd+8 + traits::X0,
|
||||
tu.bitwise_xor(
|
||||
tu.store(rd+8 + traits::X0, tu.bitwise_xor(
|
||||
tu.load(rd+8 + traits::X0, 0),
|
||||
tu.load(rs2+8 + traits::X0, 0)));
|
||||
auto returnValue = std::make_tuple(CONT);
|
||||
@ -3132,7 +3082,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__or"),
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.or"),
|
||||
fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
@ -3141,8 +3091,7 @@ private:
|
||||
gen_set_pc(tu, pc, traits::NEXT_PC);
|
||||
tu.open_scope();
|
||||
this->gen_set_tval(tu, instr);
|
||||
tu.store(rd+8 + traits::X0,
|
||||
tu.bitwise_or(
|
||||
tu.store(rd+8 + traits::X0, tu.bitwise_or(
|
||||
tu.load(rd+8 + traits::X0, 0),
|
||||
tu.load(rs2+8 + traits::X0, 0)));
|
||||
auto returnValue = std::make_tuple(CONT);
|
||||
@ -3163,7 +3112,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__and"),
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.and"),
|
||||
fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
@ -3172,8 +3121,7 @@ private:
|
||||
gen_set_pc(tu, pc, traits::NEXT_PC);
|
||||
tu.open_scope();
|
||||
this->gen_set_tval(tu, instr);
|
||||
tu.store(rd+8 + traits::X0,
|
||||
tu.bitwise_and(
|
||||
tu.store(rd+8 + traits::X0, tu.bitwise_and(
|
||||
tu.load(rd+8 + traits::X0, 0),
|
||||
tu.load(rs2+8 + traits::X0, 0)));
|
||||
auto returnValue = std::make_tuple(CONT);
|
||||
@ -3193,7 +3141,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__j"),
|
||||
"{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.j"),
|
||||
fmt::arg("imm", imm));
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
@ -3224,7 +3172,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__beqz"),
|
||||
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.beqz"),
|
||||
fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
@ -3259,7 +3207,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__bnez"),
|
||||
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.bnez"),
|
||||
fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
@ -3294,7 +3242,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c__slli"),
|
||||
"{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c.slli"),
|
||||
fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm));
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
@ -3308,8 +3256,7 @@ private:
|
||||
}
|
||||
else{
|
||||
if(rs1!=0) {
|
||||
tu.store(rs1 + traits::X0,
|
||||
tu.shl(
|
||||
tu.store(rs1 + traits::X0, tu.shl(
|
||||
tu.load(rs1 + traits::X0, 0),
|
||||
tu.constant(nzuimm,8)));
|
||||
}
|
||||
@ -3332,7 +3279,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c__lwsp"),
|
||||
"{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c.lwsp"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm));
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
@ -3348,8 +3295,7 @@ private:
|
||||
auto offs = tu.assignment(tu.ext((tu.add(
|
||||
tu.load(2 + traits::X0, 0),
|
||||
tu.constant(uimm,8))),32,false),32);
|
||||
tu.store(rd + traits::X0,
|
||||
tu.ext(tu.ext(tu.read_mem(traits::MEM, offs, 32),32,true),32,false));
|
||||
tu.store(rd + traits::X0, tu.ext(tu.ext(tu.read_mem(traits::MEM, offs, 32),32,true),32,false));
|
||||
}
|
||||
auto returnValue = std::make_tuple(CONT);
|
||||
|
||||
@ -3369,7 +3315,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__mv"),
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.mv"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
@ -3383,8 +3329,7 @@ private:
|
||||
}
|
||||
else{
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.load(rs2+ traits::X0, 0));
|
||||
tu.store(rd + traits::X0, tu.load(rs2 + traits::X0, 0));
|
||||
}
|
||||
}
|
||||
auto returnValue = std::make_tuple(CONT);
|
||||
@ -3404,7 +3349,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jr"),
|
||||
"{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jr"),
|
||||
fmt::arg("rs1", name(rs1)));
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
@ -3439,7 +3384,9 @@ private:
|
||||
uint64_t PC = pc.val;
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "__reserved_cmv");
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = ".reserved_cmv";
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
|
||||
pc=pc+ 2;
|
||||
@ -3465,7 +3412,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__add"),
|
||||
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.add"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
@ -3479,8 +3426,7 @@ private:
|
||||
}
|
||||
else{
|
||||
if(rd!=0) {
|
||||
tu.store(rd + traits::X0,
|
||||
tu.ext((tu.add(
|
||||
tu.store(rd + traits::X0, tu.ext((tu.add(
|
||||
tu.load(rd + traits::X0, 0),
|
||||
tu.load(rs2 + traits::X0, 0))),32,false));
|
||||
}
|
||||
@ -3502,7 +3448,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jalr"),
|
||||
"{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jalr"),
|
||||
fmt::arg("rs1", name(rs1)));
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
@ -3518,8 +3464,7 @@ private:
|
||||
else{
|
||||
auto addr_mask = (uint32_t)- 2;
|
||||
auto new_pc = tu.assignment(tu.load(rs1 + traits::X0, 0),32);
|
||||
tu.store(1 + traits::X0,
|
||||
tu.constant((uint32_t)(PC+2),32));
|
||||
tu.store(1 + traits::X0, tu.constant((uint32_t)(PC+2),32));
|
||||
auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and(
|
||||
new_pc,
|
||||
tu.constant(addr_mask,32)),32);
|
||||
@ -3541,7 +3486,9 @@ private:
|
||||
uint64_t PC = pc.val;
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "c__ebreak");
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = "c.ebreak";
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
|
||||
pc=pc+ 2;
|
||||
@ -3567,7 +3514,7 @@ private:
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c__swsp"),
|
||||
"{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c.swsp"),
|
||||
fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm));
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
@ -3600,7 +3547,9 @@ private:
|
||||
uint64_t PC = pc.val;
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "dii");
|
||||
//No disass specified, using instruction name
|
||||
std::string mnemonic = "dii";
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
|
||||
}
|
||||
auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
|
||||
pc=pc+ 2;
|
||||
@ -3626,11 +3575,11 @@ private:
|
||||
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, std::string("illegal_instruction"));
|
||||
}
|
||||
pc = pc + ((instr & 3) == 3 ? 4 : 2);
|
||||
gen_raise_trap(tu, 0, 2); // illegal instruction trap
|
||||
gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
|
||||
this->gen_set_tval(tu, instr);
|
||||
vm_impl::gen_sync(tu, iss::POST_SYNC, instr_descr.size());
|
||||
vm_impl::gen_trap_check(tu);
|
||||
return BRANCH;
|
||||
return ILLEGAL_INSTR;
|
||||
}
|
||||
};
|
||||
|
||||
@ -3663,19 +3612,11 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
|
||||
phys_addr_t paddr(pc);
|
||||
if(this->core.has_mmu())
|
||||
paddr = this->core.virt2phys(pc);
|
||||
//TODO: re-add page handling
|
||||
// if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
|
||||
// auto res = this->core.read(paddr, 2, data);
|
||||
// if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
|
||||
// if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
|
||||
// res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
|
||||
// }
|
||||
// } else {
|
||||
auto res = this->core.read(paddr, 4, reinterpret_cast<uint8_t*>(&instr));
|
||||
if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
|
||||
// }
|
||||
if (instr == 0x0000006f || (instr&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
|
||||
// curr pc on stack
|
||||
if (res != iss::Ok)
|
||||
return ILLEGAL_FETCH;
|
||||
if (instr == 0x0000006f || (instr&0xffff)==0xa001)
|
||||
return JUMP_TO_SELF;
|
||||
++inst_cnt;
|
||||
uint32_t inst_index = instr_decoder.decode_instr(instr);
|
||||
compile_func f = nullptr;
|
||||
@ -3697,9 +3638,6 @@ template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsi
|
||||
tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(UNKNOWN_JUMP), 32));
|
||||
}
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned type) {
|
||||
}
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_set_tval(tu_builder& tu, uint64_t new_tval) {
|
||||
tu(fmt::format("tval = {};", new_tval));
|
||||
}
|
||||
@ -3715,6 +3653,7 @@ template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
|
||||
tu("return *next_pc;");
|
||||
}
|
||||
|
||||
|
||||
} // namespace tgc5c
|
||||
|
||||
template <>
|
||||
|
||||
Reference in New Issue
Block a user