fixes CSR access rights

src/iss/arch/riscv_hart_m_p.h

@@ -454,11 +454,13 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
         //csr_wr_cb[addr] = &this_class::write_csr_reg;
     }
     // common regs
-    const std::array<unsigned, 8> addrs{{
+    const std::array<unsigned, 4> roaddrs{{misa, mvendorid, marchid, mimpid}};
-    	misa, mvendorid, marchid, mimpid,
+    for(auto addr: roaddrs) {
-    	mepc, mtvec, mscratch, mtval
+        csr_rd_cb[addr] = &this_class::read_csr_reg;
-    }};
+        csr_wr_cb[addr] = &this_class::write_null;
-    for(auto addr: addrs) {
+    }
+    const std::array<unsigned, 4> rwaddrs{{mepc, mtvec, mscratch, mtval}};
+    for(auto addr: rwaddrs) {
         csr_rd_cb[addr] = &this_class::read_csr_reg;
         csr_wr_cb[addr] = &this_class::write_csr_reg;
     }

src/iss/arch/riscv_hart_mu_p.h

@@ -398,12 +398,16 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
         //csr_wr_cb[addr] = &this_class::write_csr_reg;
     }
     // common regs
-    const std::array<unsigned, 12> addrs{{
+    const std::array<unsigned, 4> roaddrs{{misa, mvendorid, marchid, mimpid}};
-        misa, mvendorid, marchid, mimpid,
+    for(auto addr: roaddrs) {
+        csr_rd_cb[addr] = &this_class::read_csr_reg;
+        csr_wr_cb[addr] = &this_class::write_null;
+    }
+    const std::array<unsigned, 8> rwaddrs{{
         mepc, mtvec, mscratch, mtval,
         uepc, utvec, uscratch, utval,
     }};
-    for(auto addr: addrs) {
+    for(auto addr: rwaddrs) {
         csr_rd_cb[addr] = &this_class::read_csr_reg;
         csr_wr_cb[addr] = &this_class::write_csr_reg;
     }