DBT-RISE/DBT-RISE-TGC
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base: DBT-RISE:48370a4555194e26adf8999c69fd503a725b237e
Branches Tags
DBT-RISE:main
DBT-RISE:develop
DBT-RISE:feature/htif
DBT-RISE:feature/iss_factory
DBT-RISE:feature/core_factory
DBT-RISE:Trace_enhancement
DBT-RISE:feature/reduced_output
DBT-RISE:msvc_compat
DBT-RISE:hotfix/latest_scc
DBT-RISE:feature/interpreter
..
compare: DBT-RISE:2fb28364c53ab65af9620c43f93d58a229d42909
Branches Tags
DBT-RISE:main
DBT-RISE:develop
DBT-RISE:feature/htif
DBT-RISE:feature/iss_factory
DBT-RISE:feature/core_factory
DBT-RISE:Trace_enhancement
DBT-RISE:feature/reduced_output
DBT-RISE:msvc_compat
DBT-RISE:hotfix/latest_scc
DBT-RISE:feature/interpreter

No commits in common. "48370a4555194e26adf8999c69fd503a725b237e" and "2fb28364c53ab65af9620c43f93d58a229d42909" have entirely different histories.
48370a4555 ... 2fb28364c5

3 changed files with 104 additions and 93 deletions
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4
gen_input/templates/asmjit/CORENAME.cpp.gtl
View File

@ -363,7 +363,7 @@ volatile std::array<bool, 2> dummy = {
auto vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
if(init_data){
auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t)>*>(init_data);
cpu->set_semihosting_callback(*cb);
}
return {cpu_ptr{cpu}, vm_ptr{vm}};
@ -373,7 +373,7 @@ volatile std::array<bool, 2> dummy = {
auto vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
if(init_data){
auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t)>*>(init_data);
cpu->set_semihosting_callback(*cb);
}
return {cpu_ptr{cpu}, vm_ptr{vm}};

4
gen_input/templates/tcc/CORENAME.cpp.gtl
View File

@ -334,7 +334,7 @@ volatile std::array<bool, 2> dummy = {
auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
if(init_data){
auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t)>*>(init_data);
cpu->set_semihosting_callback(*cb);
}
return {cpu_ptr{cpu}, vm_ptr{vm}};
@ -344,7 +344,7 @@ volatile std::array<bool, 2> dummy = {
auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
if(init_data){
auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t)>*>(init_data);
cpu->set_semihosting_callback(*cb);
}
return {cpu_ptr{cpu}, vm_ptr{vm}};

187
src/vm/asmjit/vm_tgc5c.cpp
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2017-2024 MINRES Technologies GmbH
* Copyright (C) 2017, 2023 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -339,7 +339,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
if(rd!=0){
@ -385,7 +385,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
if(rd!=0){
@ -431,7 +431,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
if(imm%static_cast<uint32_t>(traits::INSTR_ALIGNMENT)){
@ -486,7 +486,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto addr_mask = (uint32_t)- 2;
@ -554,7 +554,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto label_merge = cc.newLabel();
@ -612,7 +612,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto label_merge = cc.newLabel();
@ -670,7 +670,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto label_merge = cc.newLabel();
@ -730,7 +730,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto label_merge = cc.newLabel();
@ -790,7 +790,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto label_merge = cc.newLabel();
@ -848,7 +848,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto label_merge = cc.newLabel();
@ -906,7 +906,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto load_address = gen_ext(jh,
@ -959,7 +959,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto load_address = gen_ext(jh,
@ -1012,7 +1012,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto load_address = gen_ext(jh,
@ -1065,7 +1065,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto load_address = gen_ext(jh,
@ -1117,7 +1117,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto load_address = gen_ext(jh,
@ -1169,7 +1169,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto store_address = gen_ext(jh,
@ -1217,7 +1217,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto store_address = gen_ext(jh,
@ -1265,7 +1265,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto store_address = gen_ext(jh,
@ -1313,7 +1313,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
if(rd!=0){
@ -1362,7 +1362,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
if(rd!=0){
@ -1424,7 +1424,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
if(rd!=0){
@ -1485,7 +1485,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
if(rd!=0){
@ -1533,7 +1533,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
if(rd!=0){
@ -1581,7 +1581,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
if(rd!=0){
@ -1629,7 +1629,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
if(rd!=0){
@ -1677,7 +1677,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
if(rd!=0){
@ -1725,7 +1725,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
if(rd!=0){
@ -1733,7 +1733,7 @@ private:
gen_ext(jh,
(gen_operation(jh, sar, gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs1), 32, true), shamt)
), 32, false));
), 32, true));
}
}
auto returnValue = CONT;
@ -1775,7 +1775,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
if(rd!=0){
@ -1824,7 +1824,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
if(rd!=0){
@ -1873,7 +1873,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
if(rd!=0){
@ -1922,7 +1922,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
if(rd!=0){
@ -1985,7 +1985,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
if(rd!=0){
@ -2046,7 +2046,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
if(rd!=0){
@ -2094,7 +2094,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
if(rd!=0){
@ -2143,7 +2143,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
if(rd!=0){
@ -2194,7 +2194,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
if(rd!=0){
@ -2242,7 +2242,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
if(rd!=0){
@ -2471,7 +2471,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto xrs1 = load_reg_from_mem(jh, traits::X0 + rs1);
@ -2524,7 +2524,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto xrd = gen_read_mem(jh, traits::CSR, csr, 4);
@ -2577,7 +2577,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto xrd = gen_read_mem(jh, traits::CSR, csr, 4);
@ -2630,7 +2630,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto xrd = gen_read_mem(jh, traits::CSR, csr, 4);
@ -2679,7 +2679,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto xrd = gen_read_mem(jh, traits::CSR, csr, 4);
@ -2731,7 +2731,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto xrd = gen_read_mem(jh, traits::CSR, csr, 4);
@ -2822,13 +2822,16 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto res = gen_operation(jh, imul, gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs1), 32, true), gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs2), 32, true))
;
auto res = gen_ext(jh,
(gen_operation(jh, imul, gen_ext(jh,
gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), gen_ext(jh,
gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs2), 32, true), 64, true))
), 64, true);
if(rd!=0){
cc.mov(get_ptr_for(jh, traits::X0+ rd),
gen_ext(jh,
@ -2874,13 +2877,16 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto res = gen_operation(jh, imul, gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs1), 32, true), gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs2), 32, true))
;
auto res = gen_ext(jh,
(gen_operation(jh, imul, gen_ext(jh,
gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), gen_ext(jh,
gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs2), 32, true), 64, true))
), 64, true);
if(rd!=0){
cc.mov(get_ptr_for(jh, traits::X0+ rd),
gen_ext(jh,
@ -2927,12 +2933,15 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto res = gen_operation(jh, imul, gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs1), 32, true), load_reg_from_mem(jh, traits::X0 + rs2))
;
auto res = gen_ext(jh,
(gen_operation(jh, imul, gen_ext(jh,
gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs2), 64, false))
), 64, true);
if(rd!=0){
cc.mov(get_ptr_for(jh, traits::X0+ rd),
gen_ext(jh,
@ -2979,12 +2988,14 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto res = gen_operation(jh, mul,
load_reg_from_mem(jh, traits::X0 + rs1),
load_reg_from_mem(jh, traits::X0 + rs2));
auto res = gen_ext(jh,
(gen_operation(jh, mul, gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs2), 64, false))
), 64, false);
if(rd!=0){
cc.mov(get_ptr_for(jh, traits::X0+ rd),
gen_ext(jh,
@ -3031,13 +3042,13 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto dividend = gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs1), 32, true);
load_reg_from_mem(jh, traits::X0 + rs1), 32, false);
auto divisor = gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs2), 32, true);
load_reg_from_mem(jh, traits::X0 + rs2), 32, false);
if(rd!=0){
auto label_merge = cc.newLabel();
cc.cmp(gen_operation(jh, ne, divisor, 0)
@ -3115,7 +3126,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto label_merge = cc.newLabel();
@ -3126,8 +3137,9 @@ private:
{
if(rd!=0){
cc.mov(get_ptr_for(jh, traits::X0+ rd),
gen_operation(jh, div, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
);
gen_ext(jh,
(gen_operation(jh, div, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
), 32, false));
}
}
cc.jmp(label_merge);
@ -3179,7 +3191,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto label_merge = cc.newLabel();
@ -3211,9 +3223,9 @@ private:
cc.mov(get_ptr_for(jh, traits::X0+ rd),
gen_ext(jh,
(gen_operation(jh, srem, gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs1), 32, true), gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs2), 32, true))
), 32, false));
load_reg_from_mem(jh, traits::X0 + rs1), 32, false), gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs2), 32, false))
), 32, true));
}
}
cc.bind(label_merge);
@ -3267,7 +3279,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto label_merge = cc.newLabel();
@ -3336,7 +3348,7 @@ private:
), 32, false));
}
else{
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
auto returnValue = CONT;
@ -3464,7 +3476,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
if(rs1!=0){
@ -3588,7 +3600,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
if(rd!=0){
@ -3634,7 +3646,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(imm==0||rd>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
if(rd!=0){
cc.mov(get_ptr_for(jh, traits::X0+ rd),
@ -3683,7 +3695,7 @@ private:
), 32, true));
}
else{
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
auto returnValue = CONT;
@ -3720,7 +3732,7 @@ private:
gen_instr_prologue(jh);
cc.comment("//behavior:");
/*generate behavior*/
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
auto returnValue = CONT;
gen_instr_epilogue(jh);
@ -4187,7 +4199,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
if(rs1!=0){
@ -4234,7 +4246,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rd==0){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto offs = gen_ext(jh,
@ -4283,7 +4295,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
if(rd!=0){
@ -4409,7 +4421,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
if(rd!=0){
@ -4456,7 +4468,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto new_pc = load_reg_from_mem(jh, traits::X0 + rs1);
@ -4540,7 +4552,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
}
else{
auto offs = gen_ext(jh,
@ -4583,7 +4595,7 @@ private:
gen_instr_prologue(jh);
cc.comment("//behavior:");
/*generate behavior*/
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise(jh, 0, 2);
auto returnValue = CONT;
gen_instr_epilogue(jh);
@ -4605,7 +4617,6 @@ private:
this->gen_sync(jh, POST_SYNC, instr_descr.size());
return BRANCH;
}
//decoding functionality
void populate_decoding_tree(decoding_tree_node* root){