fixes missing namespaces

.clang-format

@@ -1,3 +1,4 @@
+---
 Language:        Cpp
 # BasedOnStyle:  LLVM
 # should be in line with IndentWidth
@@ -12,8 +13,8 @@ AllowAllParametersOfDeclarationOnNextLine: true
 AllowShortBlocksOnASingleLine: false
 AllowShortCaseLabelsOnASingleLine: false
 AllowShortFunctionsOnASingleLine: All
-AllowShortIfStatementsOnASingleLine: false
+AllowShortIfStatementsOnASingleLine: true
-AllowShortLoopsOnASingleLine: false
+AllowShortLoopsOnASingleLine: true
 AlwaysBreakAfterDefinitionReturnType: None
 AlwaysBreakAfterReturnType: None
 AlwaysBreakBeforeMultilineStrings: false
@@ -38,8 +39,8 @@ BreakBeforeTernaryOperators: true
 BreakConstructorInitializersBeforeComma: true
 BreakAfterJavaFieldAnnotations: false
 BreakStringLiterals: true
-ColumnLimit:     140
+ColumnLimit:     120
-CommentPragmas:  '^( IWYU pragma:| @suppress)'
+CommentPragmas:  '^ IWYU pragma:'
 ConstructorInitializerAllOnOneLineOrOnePerLine: false
 ConstructorInitializerIndentWidth: 0
 ContinuationIndentWidth: 4
@@ -75,13 +76,13 @@ PenaltyBreakFirstLessLess: 120
 PenaltyBreakString: 1000
 PenaltyExcessCharacter: 1000000
 PenaltyReturnTypeOnItsOwnLine: 60
-PointerAlignment: Left
+PointerAlignment: Right
 ReflowComments:  true
 SortIncludes:    true
 SpaceAfterCStyleCast: false
 SpaceAfterTemplateKeyword: true
 SpaceBeforeAssignmentOperators: true
-SpaceBeforeParens: Never
+SpaceBeforeParens: ControlStatements
 SpaceInEmptyParentheses: false
 SpacesBeforeTrailingComments: 1
 SpacesInAngles:  false

.gitignore

@@ -1,6 +1,5 @@
 .DS_Store
 /*.il
-/.settings
 /avr-instr.html
 /blink.S
 /flash.*
@@ -15,6 +14,7 @@
 /*.ods
 /build*/
 /*.logs
+language.settings.xml
 /*.gtkw
 /Debug wo LLVM/
 /*.txdb

.settings/org.eclipse.cdt.codan.core.prefs

@@ -0,0 +1,73 @@
+eclipse.preferences.version=1
+org.eclipse.cdt.codan.checkers.errnoreturn=Warning
+org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return\\")",implicit\=>false}
+org.eclipse.cdt.codan.checkers.errreturnvalue=Error
+org.eclipse.cdt.codan.checkers.errreturnvalue.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused return value\\")"}
+org.eclipse.cdt.codan.checkers.nocommentinside=-Error
+org.eclipse.cdt.codan.checkers.nocommentinside.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Nesting comments\\")"}
+org.eclipse.cdt.codan.checkers.nolinecomment=-Error
+org.eclipse.cdt.codan.checkers.nolinecomment.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Line comments\\")"}
+org.eclipse.cdt.codan.checkers.noreturn=Error
+org.eclipse.cdt.codan.checkers.noreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return value\\")",implicit\=>false}
+org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation=Error
+org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Abstract class cannot be instantiated\\")"}
+org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem=Error
+org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Ambiguous problem\\")"}
+org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment in condition\\")"}
+org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem=Error
+org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment to itself\\")"}
+org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No break at end of case\\")",no_break_comment\=>"no break",last_case_param\=>false,empty_case_param\=>false,enable_fallthrough_quickfix_param\=>false}
+org.eclipse.cdt.codan.internal.checkers.CatchByReference=Warning
+org.eclipse.cdt.codan.internal.checkers.CatchByReference.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Catching by reference is recommended\\")",unknown\=>false,exceptions\=>()}
+org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem=Error
+org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Circular inheritance\\")"}
+org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization=Warning
+org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class members should be properly initialized\\")",skip\=>true}
+org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem=Error
+org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid 'decltype(auto)' specifier\\")"}
+org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Field cannot be resolved\\")"}
+org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Function cannot be resolved\\")"}
+org.eclipse.cdt.codan.internal.checkers.InvalidArguments=Error
+org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid arguments\\")"}
+org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem=Error
+org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid template argument\\")"}
+org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem=Error
+org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Label statement not found\\")"}
+org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem=Error
+org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Member declaration not found\\")"}
+org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Method cannot be resolved\\")"}
+org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker=-Info
+org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Name convention for function\\")",pattern\=>"^[a-z]",macro\=>true,exceptions\=>()}
+org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class has a virtual method and non-virtual destructor\\")"}
+org.eclipse.cdt.codan.internal.checkers.OverloadProblem=Error
+org.eclipse.cdt.codan.internal.checkers.OverloadProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid overload\\")"}
+org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem=Error
+org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redeclaration\\")"}
+org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redefinition\\")"}
+org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem=-Warning
+org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Return with parenthesis\\")"}
+org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem=-Warning
+org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Format String Vulnerability\\")"}
+org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Statement has no effect\\")",macro\=>true,exceptions\=>()}
+org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suggested parenthesis around expression\\")",paramNot\=>false}
+org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suspicious semicolon\\")",else\=>false,afterelse\=>false}
+org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Type cannot be resolved\\")"}
+org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused function declaration\\")",macro\=>true}
+org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused static function\\")",macro\=>true}
+org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused variable declaration in file scope\\")",macro\=>true,exceptions\=>("@(\#)","$Id")}
+org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol is not resolved\\")"}

.settings/org.eclipse.cdt.core.prefs

@@ -0,0 +1,13 @@
+eclipse.preferences.version=1
+environment/project/cdt.managedbuild.config.gnu.exe.debug.1751741082/append=true
+environment/project/cdt.managedbuild.config.gnu.exe.debug.1751741082/appendContributed=true
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/LLVM_HOME/delimiter=\:
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/LLVM_HOME/operation=append
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/LLVM_HOME/value=/usr/lib/llvm-6.0
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/append=true
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/appendContributed=true
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/LLVM_HOME/delimiter=\:
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/LLVM_HOME/operation=append
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/LLVM_HOME/value=/usr/lib/llvm-6.0
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/append=true
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/appendContributed=true

.settings/org.eclipse.cdt.managedbuilder.core.prefs

@@ -0,0 +1,37 @@
+eclipse.preferences.version=1
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/CPATH/delimiter=\:
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/CPATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/CPLUS_INCLUDE_PATH/delimiter=\:
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/CPLUS_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/C_INCLUDE_PATH/delimiter=\:
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/C_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/append=true
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/appendContributed=true
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/CPATH/delimiter=\:
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/CPATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/CPLUS_INCLUDE_PATH/delimiter=\:
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/CPLUS_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/C_INCLUDE_PATH/delimiter=\:
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/C_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/append=true
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/appendContributed=true
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/CPATH/delimiter=\:
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/CPATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/CPLUS_INCLUDE_PATH/delimiter=\:
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/CPLUS_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/C_INCLUDE_PATH/delimiter=\:
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/C_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/append=true
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/appendContributed=true
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.debug.1751741082/LIBRARY_PATH/delimiter=\:
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.debug.1751741082/LIBRARY_PATH/operation=remove
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.debug.1751741082/append=true
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.debug.1751741082/appendContributed=true
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/LIBRARY_PATH/delimiter=\:
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/LIBRARY_PATH/operation=remove
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/append=true
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/appendContributed=true
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171/LIBRARY_PATH/delimiter=\:
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171/LIBRARY_PATH/operation=remove
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171/append=true
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171/appendContributed=true

CMakeLists.txt

@@ -1,74 +1,80 @@
 cmake_minimum_required(VERSION 3.12)
-list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/cmake)
 ###############################################################################
 #
 ###############################################################################
 project(dbt-rise-tgc VERSION 1.0.0)
 
 include(GNUInstallDirs)
-include(flink)
 
 find_package(elfio QUIET)
+find_package(Boost COMPONENTS coroutine)
 find_package(jsoncpp)
-find_package(Boost COMPONENTS coroutine REQUIRED)
+
+if(WITH_LLVM)
+    if(DEFINED ENV{LLVM_HOME})
+        find_path (LLVM_DIR LLVM-Config.cmake $ENV{LLVM_HOME}/lib/cmake/llvm)
+    endif(DEFINED ENV{LLVM_HOME})
+    find_package(LLVM REQUIRED CONFIG)
+    message(STATUS "Found LLVM ${LLVM_PACKAGE_VERSION}")
+    message(STATUS "Using LLVMConfig.cmake in: ${LLVM_DIR}")
+    llvm_map_components_to_libnames(llvm_libs support core mcjit x86codegen x86asmparser)
+endif()
+
+#Mac needed variables (adapt for your needs - http://www.cmake.org/Wiki/CMake_RPATH_handling#Mac_OS_X_and_the_RPATH)
+#set(CMAKE_MACOSX_RPATH ON)
+#set(CMAKE_SKIP_BUILD_RPATH FALSE)
+#set(CMAKE_BUILD_WITH_INSTALL_RPATH FALSE)
+#set(CMAKE_INSTALL_RPATH "${CMAKE_INSTALL_PREFIX}/lib")
+#set(CMAKE_INSTALL_RPATH_USE_LINK_PATH TRUE)
 
 add_subdirectory(softfloat)
 
 set(LIB_SOURCES 
     src/iss/plugin/instruction_count.cpp
-	src/iss/arch/tgc5c.cpp
+	src/iss/arch/tgc_c.cpp
-	src/vm/interp/vm_tgc5c.cpp
+	src/vm/interp/vm_tgc_c.cpp
 	src/vm/fp_functions.cpp
 )
-if(WITH_TCC)
+
-	list(APPEND LIB_SOURCES
-	   src/vm/tcc/vm_tgc5c.cpp
-    )
-endif()
-if(WITH_LLVM)
-	list(APPEND LIB_SOURCES
-		src/vm/llvm/vm_tgc5c.cpp
-		src/vm/llvm/fp_impl.cpp
-	)
-endif()
-if(WITH_ASMJIT)
-	list(APPEND LIB_SOURCES
-	   src/vm/asmjit/vm_tgc5c.cpp
-    )
-endif()
 # library files
+if(TARGET ${CORE_NAME}_cpp)
+    list(APPEND LIB_SOURCES ${${CORE_NAME}_OUTPUT_FILES})
+else()
     FILE(GLOB GEN_ISS_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp)
     FILE(GLOB GEN_VM_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp)
-FILE(GLOB GEN_YAML_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/contrib/instr/*.yaml)
     list(APPEND LIB_SOURCES ${GEN_ISS_SOURCES} ${GEN_VM_SOURCES})
     foreach(FILEPATH ${GEN_ISS_SOURCES})
         get_filename_component(CORE ${FILEPATH} NAME_WE)
         string(TOUPPER ${CORE} CORE)
         list(APPEND LIB_DEFINES CORE_${CORE})
     endforeach()
-message(STATUS "Core defines are ${LIB_DEFINES}")
+    message("Defines are ${LIB_DEFINES}")
+endif()
+
+if(TARGET RapidJSON OR TARGET RapidJSON::RapidJSON)
+    list(APPEND LIB_SOURCES src/iss/plugin/cycle_estimate.cpp src/iss/plugin/pctrace.cpp)
+endif()
 
 if(WITH_LLVM)
-	FILE(GLOB LLVM_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/llvm/vm_*.cpp)
+	FILE(GLOB LLVM_GEN_SOURCES
+	    ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/llvm/vm_*.cpp
+	)
 	list(APPEND LIB_SOURCES ${LLVM_GEN_SOURCES})
 endif()
 
 if(WITH_TCC)
-	FILE(GLOB TCC_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/tcc/vm_*.cpp)
+	FILE(GLOB TCC_GEN_SOURCES
-	list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
+	    ${CMAKE_CURRENT_SOURCE_DIR}/src/vm/tcc/vm_*.cpp
-endif()
-if(WITH_ASMJIT)
-	FILE(GLOB TCC_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/asmjit/vm_*.cpp)
-	list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
-endif()
-if(TARGET yaml-cpp::yaml-cpp)
-    list(APPEND LIB_SOURCES 
-    	src/iss/plugin/cycle_estimate.cpp
-	    src/iss/plugin/instruction_count.cpp
 	)
+	list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
 endif()
+
 # Define the library
-add_library(${PROJECT_NAME} SHARED ${LIB_SOURCES})
+add_library(${PROJECT_NAME} ${LIB_SOURCES})
+# list code gen dependencies
+if(TARGET ${CORE_NAME}_cpp)
+    add_dependencies(${PROJECT_NAME} ${CORE_NAME}_cpp)
+endif()
 
 if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
      target_compile_options(${PROJECT_NAME} PRIVATE -Wno-shift-count-overflow)
@@ -77,30 +83,32 @@ elseif("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC")
 endif()
 target_include_directories(${PROJECT_NAME} PUBLIC src)
 target_include_directories(${PROJECT_NAME} PUBLIC src-gen)
-
+target_link_libraries(${PROJECT_NAME} PUBLIC softfloat scc-util Boost::coroutine)
-target_force_link_libraries(${PROJECT_NAME} PRIVATE dbt-rise-core)
+if(TARGET jsoncpp::jsoncpp)
-# only re-export the include paths
+	target_link_libraries(${PROJECT_NAME} PUBLIC jsoncpp::jsoncpp)
-get_target_property(DBT_CORE_INCL dbt-rise-core INTERFACE_INCLUDE_DIRECTORIES)
+else()
-target_include_directories(${PROJECT_NAME} INTERFACE ${DBT_CORE_INCL})
+	target_link_libraries(${PROJECT_NAME} PUBLIC jsoncpp)
-get_target_property(DBT_CORE_DEFS dbt-rise-core INTERFACE_COMPILE_DEFINITIONS)
+endif()
-if(NOT (DBT_CORE_DEFS STREQUAL DBT_CORE_DEFS-NOTFOUND))
+if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU" AND BUILD_SHARED_LIBS)
-	target_compile_definitions(${PROJECT_NAME} INTERFACE ${DBT_CORE_DEFS})
+    target_link_libraries(${PROJECT_NAME} PUBLIC -Wl,--whole-archive dbt-rise-core -Wl,--no-whole-archive)
+else()
+    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-core)
+endif()
+if(TARGET elfio::elfio)
+    target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio)
+else()
+    message(FATAL_ERROR "No elfio library found, maybe a find_package() call is missing")
+endif()
+if(TARGET lz4::lz4)
+    target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_LZ4)
+    target_link_libraries(${PROJECT_NAME} PUBLIC lz4::lz4)
+endif()
+if(TARGET RapidJSON::RapidJSON)
+    target_link_libraries(${PROJECT_NAME} PUBLIC RapidJSON::RapidJSON)
+elseif(TARGET RapidJSON)
+    target_link_libraries(${PROJECT_NAME} PUBLIC RapidJSON)
 endif()
 
-target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio softfloat scc-util Boost::coroutine)
-if(TARGET yaml-cpp::yaml-cpp)
-	target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_PLUGINS)
-	target_link_libraries(${PROJECT_NAME} PUBLIC yaml-cpp::yaml-cpp)
-endif()
-
-if(WITH_LLVM)
-    find_package(LLVM)
-	target_compile_definitions(${PROJECT_NAME} PUBLIC ${LLVM_DEFINITIONS})
-	target_include_directories(${PROJECT_NAME} PUBLIC ${LLVM_INCLUDE_DIRS})
-	if(BUILD_SHARED_LIBS)
-		target_link_libraries( ${PROJECT_NAME} PUBLIC ${LLVM_LIBRARIES})
-	endif()
-endif()
 
 set_target_properties(${PROJECT_NAME} PROPERTIES
   VERSION ${PROJECT_VERSION}
@@ -120,11 +128,9 @@ install(DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss COMPONENT ${PROJECT_NAME}
         FILES_MATCHING # install only matched files
         PATTERN "*.h" # select header files
         )
-install(FILES ${GEN_YAML_SOURCES} DESTINATION share/tgc-vp)
 ###############################################################################
 #
 ###############################################################################
-set(CMAKE_INSTALL_RPATH $ORIGIN/../${CMAKE_INSTALL_LIBDIR})
 project(tgc-sim)
 find_package(Boost COMPONENTS program_options thread REQUIRED)
 
@@ -147,16 +153,15 @@ foreach(F IN LISTS TGC_SOURCES)
     endif()
 endforeach()
 
-#if(WITH_LLVM)
+if(WITH_LLVM)
-#    target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_LLVM)
+    target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_LLVM)
-#    #target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
+    target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
-#endif()
+endif()
-#if(WITH_TCC)
+if(WITH_TCC)
-#    target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_TCC)
+    target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_TCC)
-#endif()
+endif()
-
+# Links the target exe against the libraries
-target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc fmt::fmt)
+target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc)
-
 if(TARGET Boost::program_options)
     target_link_libraries(${PROJECT_NAME} PUBLIC Boost::program_options)
 else()
@@ -176,36 +181,15 @@ install(TARGETS tgc-sim
   PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME}  # headers for mac (note the different component -> different package)
   INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}             # headers
 )
-
-if(BUILD_TESTING)
-  	# ... CMake code to create tests ...
-	add_test(NAME tgc-sim-interp
-	         COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend interp)
-	if(WITH_TCC)
-	add_test(NAME tgc-sim-tcc
-	         COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend tcc)
-	endif()
-	if(WITH_LLVM)
-	add_test(NAME tgc-sim-llvm
-	         COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend llvm)
-	endif()
-    if(WITH_ASMJIT)
-	add_test(NAME tgc-sim-asmjit
-	         COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend asmjit)
-	endif()
-endif()
 ###############################################################################
 #
 ###############################################################################
 if(TARGET scc-sysc)
 	project(dbt-rise-tgc_sc VERSION 1.0.0)
-	set(LIB_SOURCES 
+    add_library(${PROJECT_NAME} 
     	src/sysc/core_complex.cpp
     	src/sysc/register_tgc_c.cpp
     )
-	FILE(GLOB GEN_SC_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/sysc/register_*.cpp)
-	list(APPEND LIB_SOURCES ${GEN_SC_SOURCES})
-    add_library(${PROJECT_NAME} ${LIB_SOURCES})
     target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_SYSTEMC)
     target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
     foreach(F IN LISTS TGC_SOURCES)
@@ -216,9 +200,9 @@ if(TARGET scc-sysc)
         endif()
     endforeach()
     target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc-sysc)
-#    if(WITH_LLVM)
+    if(WITH_LLVM)
-#        target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
+        target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
-#    endif()
+    endif()
     
 	set(LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/src/sysc/core_complex.h)
     set_target_properties(${PROJECT_NAME} PROPERTIES

TGC_C_instr.yaml

@@ -1,348 +1,307 @@
 
-RVI: 
+RV32I: 
-  LUI:
+  - LUI:
-    index: 0
     encoding: 0b00000000000000000000000000110111
     mask: 0b00000000000000000000000001111111
     size:   32
     branch:   false
     delay:   1
-  AUIPC:
+  - AUIPC:
-    index: 1
     encoding: 0b00000000000000000000000000010111
     mask: 0b00000000000000000000000001111111
     size:   32
     branch:   false
     delay:   1
-  JAL:
+  - JAL:
-    index: 2
     encoding: 0b00000000000000000000000001101111
     mask: 0b00000000000000000000000001111111
+    attributes: [[name:no_cont]]
     size:   32
     branch:   true
     delay:   1
-  JALR:
+  - JALR:
-    index: 3
     encoding: 0b00000000000000000000000001100111
     mask: 0b00000000000000000111000001111111
+    attributes: [[name:no_cont]]
     size:   32
     branch:   true
-    delay:   [1,1]
+    delay:   1
-  BEQ:
+  - BEQ:
-    index: 4
     encoding: 0b00000000000000000000000001100011
     mask: 0b00000000000000000111000001111111
+    attributes: [[name:no_cont], [name:cond]]
     size:   32
     branch:   true
     delay:   [1,1]
-  BNE:
+  - BNE:
-    index: 5
     encoding: 0b00000000000000000001000001100011
     mask: 0b00000000000000000111000001111111
+    attributes: [[name:no_cont], [name:cond]]
     size:   32
     branch:   true
     delay:   [1,1]
-  BLT:
+  - BLT:
-    index: 6
     encoding: 0b00000000000000000100000001100011
     mask: 0b00000000000000000111000001111111
+    attributes: [[name:no_cont], [name:cond]]
     size:   32
     branch:   true
     delay:   [1,1]
-  BGE:
+  - BGE:
-    index: 7
     encoding: 0b00000000000000000101000001100011
     mask: 0b00000000000000000111000001111111
+    attributes: [[name:no_cont], [name:cond]]
     size:   32
     branch:   true
     delay:   [1,1]
-  BLTU:
+  - BLTU:
-    index: 8
     encoding: 0b00000000000000000110000001100011
     mask: 0b00000000000000000111000001111111
+    attributes: [[name:no_cont], [name:cond]]
     size:   32
     branch:   true
     delay:   [1,1]
-  BGEU:
+  - BGEU:
-    index: 9
     encoding: 0b00000000000000000111000001100011
     mask: 0b00000000000000000111000001111111
+    attributes: [[name:no_cont], [name:cond]]
     size:   32
     branch:   true
     delay:   [1,1]
-  LB:
+  - LB:
-    index: 10
     encoding: 0b00000000000000000000000000000011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  LH:
+  - LH:
-    index: 11
     encoding: 0b00000000000000000001000000000011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  LW:
+  - LW:
-    index: 12
     encoding: 0b00000000000000000010000000000011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  LBU:
+  - LBU:
-    index: 13
     encoding: 0b00000000000000000100000000000011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  LHU:
+  - LHU:
-    index: 14
     encoding: 0b00000000000000000101000000000011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  SB:
+  - SB:
-    index: 15
     encoding: 0b00000000000000000000000000100011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  SH:
+  - SH:
-    index: 16
     encoding: 0b00000000000000000001000000100011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  SW:
+  - SW:
-    index: 17
     encoding: 0b00000000000000000010000000100011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  ADDI:
+  - ADDI:
-    index: 18
     encoding: 0b00000000000000000000000000010011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  SLTI:
+  - SLTI:
-    index: 19
     encoding: 0b00000000000000000010000000010011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  SLTIU:
+  - SLTIU:
-    index: 20
     encoding: 0b00000000000000000011000000010011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  XORI:
+  - XORI:
-    index: 21
     encoding: 0b00000000000000000100000000010011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  ORI:
+  - ORI:
-    index: 22
     encoding: 0b00000000000000000110000000010011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  ANDI:
+  - ANDI:
-    index: 23
     encoding: 0b00000000000000000111000000010011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  SLLI:
+  - SLLI:
-    index: 24
     encoding: 0b00000000000000000001000000010011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  SRLI:
+  - SRLI:
-    index: 25
     encoding: 0b00000000000000000101000000010011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  SRAI:
+  - SRAI:
-    index: 26
     encoding: 0b01000000000000000101000000010011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  ADD:
+  - ADD:
-    index: 27
     encoding: 0b00000000000000000000000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  SUB:
+  - SUB:
-    index: 28
     encoding: 0b01000000000000000000000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  SLL:
+  - SLL:
-    index: 29
     encoding: 0b00000000000000000001000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  SLT:
+  - SLT:
-    index: 30
     encoding: 0b00000000000000000010000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  SLTU:
+  - SLTU:
-    index: 31
     encoding: 0b00000000000000000011000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  XOR:
+  - XOR:
-    index: 32
     encoding: 0b00000000000000000100000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  SRL:
+  - SRL:
-    index: 33
     encoding: 0b00000000000000000101000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  SRA:
+  - SRA:
-    index: 34
     encoding: 0b01000000000000000101000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  OR:
+  - OR:
-    index: 35
     encoding: 0b00000000000000000110000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  AND:
+  - AND:
-    index: 36
     encoding: 0b00000000000000000111000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  FENCE:
+  - FENCE:
-    index: 37
     encoding: 0b00000000000000000000000000001111
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  ECALL:
+  - ECALL:
-    index: 38
     encoding: 0b00000000000000000000000001110011
     mask: 0b11111111111111111111111111111111
     attributes: [[name:no_cont]]
     size:   32
     branch:   false
     delay:   1
-  EBREAK:
+  - EBREAK:
-    index: 39
     encoding: 0b00000000000100000000000001110011
     mask: 0b11111111111111111111111111111111
     attributes: [[name:no_cont]]
     size:   32
     branch:   false
     delay:   1
-  MRET:
+  - MRET:
-    index: 40
     encoding: 0b00110000001000000000000001110011
     mask: 0b11111111111111111111111111111111
     attributes: [[name:no_cont]]
     size:   32
     branch:   false
     delay:   1
-  WFI:
+  - WFI:
-    index: 41
     encoding: 0b00010000010100000000000001110011
     mask: 0b11111111111111111111111111111111
     size:   32
     branch:   false
     delay:   1
 Zicsr: 
-  CSRRW:
+  - CSRRW:
-    index: 42
     encoding: 0b00000000000000000001000001110011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  CSRRS:
+  - CSRRS:
-    index: 43
     encoding: 0b00000000000000000010000001110011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  CSRRC:
+  - CSRRC:
-    index: 44
     encoding: 0b00000000000000000011000001110011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  CSRRWI:
+  - CSRRWI:
-    index: 45
     encoding: 0b00000000000000000101000001110011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  CSRRSI:
+  - CSRRSI:
-    index: 46
     encoding: 0b00000000000000000110000001110011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  CSRRCI:
+  - CSRRCI:
-    index: 47
     encoding: 0b00000000000000000111000001110011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
     delay:   1
 Zifencei: 
-  FENCE_I:
+  - FENCE_I:
-    index: 48
     encoding: 0b00000000000000000001000000001111
     mask: 0b00000000000000000111000001111111
     attributes: [[name:flush]]
@@ -350,274 +309,228 @@ Zifencei:
     branch:   false
     delay:   1
 RV32M: 
-  MUL:
+  - MUL:
-    index: 49
     encoding: 0b00000010000000000000000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  MULH:
+  - MULH:
-    index: 50
     encoding: 0b00000010000000000001000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  MULHSU:
+  - MULHSU:
-    index: 51
     encoding: 0b00000010000000000010000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  MULHU:
+  - MULHU:
-    index: 52
     encoding: 0b00000010000000000011000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  DIV:
+  - DIV:
-    index: 53
     encoding: 0b00000010000000000100000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  DIVU:
+  - DIVU:
-    index: 54
     encoding: 0b00000010000000000101000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  REM:
+  - REM:
-    index: 55
     encoding: 0b00000010000000000110000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-  REMU:
+  - REMU:
-    index: 56
     encoding: 0b00000010000000000111000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
     delay:   1
-Zca: 
+RV32IC: 
-  C__ADDI4SPN:
+  - CADDI4SPN:
-    index: 57
     encoding: 0b0000000000000000
     mask: 0b1110000000000011
     size:   16
     branch:   false
     delay:   1
-  C__LW:
+  - CLW:
-    index: 58
     encoding: 0b0100000000000000
     mask: 0b1110000000000011
     size:   16
     branch:   false
     delay:   1
-  C__SW:
+  - CSW:
-    index: 59
     encoding: 0b1100000000000000
     mask: 0b1110000000000011
     size:   16
     branch:   false
     delay:   1
-  C__ADDI:
+  - CADDI:
-    index: 60
     encoding: 0b0000000000000001
     mask: 0b1110000000000011
     size:   16
     branch:   false
     delay:   1
-  C__NOP:
+  - CNOP:
-    index: 61
     encoding: 0b0000000000000001
     mask: 0b1110111110000011
     size:   16
     branch:   false
     delay:   1
-  C__JAL:
+  - CJAL:
-    index: 62
     encoding: 0b0010000000000001
     mask: 0b1110000000000011
-    attributes: [[name:enable, value:1]]
+    attributes: [[name:no_cont]]
     size:   16
     branch:   true
     delay:   1
-  C__LI:
+  - CLI:
-    index: 63
     encoding: 0b0100000000000001
     mask: 0b1110000000000011
     size:   16
     branch:   false
     delay:   1
-  C__LUI:
+  - CLUI:
-    index: 64
     encoding: 0b0110000000000001
     mask: 0b1110000000000011
     size:   16
     branch:   false
     delay:   1
-  C__ADDI16SP:
+  - CADDI16SP:
-    index: 65
     encoding: 0b0110000100000001
     mask: 0b1110111110000011
     size:   16
     branch:   false
     delay:   1
-  __reserved_clui:
+  - CSRLI:
-    index: 66
-    encoding: 0b0110000000000001
-    mask: 0b1111000001111111
-    size:   16
-    branch:   false
-    delay:   1
-  C__SRLI:
-    index: 67
     encoding: 0b1000000000000001
     mask: 0b1111110000000011
-    attributes: [[name:enable, value:1]]
     size:   16
     branch:   false
     delay:   1
-  C__SRAI:
+  - CSRAI:
-    index: 68
     encoding: 0b1000010000000001
     mask: 0b1111110000000011
-    attributes: [[name:enable, value:1]]
     size:   16
     branch:   false
     delay:   1
-  C__ANDI:
+  - CANDI:
-    index: 69
     encoding: 0b1000100000000001
     mask: 0b1110110000000011
     size:   16
     branch:   false
     delay:   1
-  C__SUB:
+  - CSUB:
-    index: 70
     encoding: 0b1000110000000001
     mask: 0b1111110001100011
     size:   16
     branch:   false
     delay:   1
-  C__XOR:
+  - CXOR:
-    index: 71
     encoding: 0b1000110000100001
     mask: 0b1111110001100011
     size:   16
     branch:   false
     delay:   1
-  C__OR:
+  - COR:
-    index: 72
     encoding: 0b1000110001000001
     mask: 0b1111110001100011
     size:   16
     branch:   false
     delay:   1
-  C__AND:
+  - CAND:
-    index: 73
     encoding: 0b1000110001100001
     mask: 0b1111110001100011
     size:   16
     branch:   false
     delay:   1
-  C__J:
+  - CJ:
-    index: 74
     encoding: 0b1010000000000001
     mask: 0b1110000000000011
+    attributes: [[name:no_cont]]
     size:   16
     branch:   true
     delay:   1
-  C__BEQZ:
+  - CBEQZ:
-    index: 75
     encoding: 0b1100000000000001
     mask: 0b1110000000000011
+    attributes: [[name:no_cont], [name:cond]]
     size:   16
     branch:   true
     delay:   [1,1]
-  C__BNEZ:
+  - CBNEZ:
-    index: 76
     encoding: 0b1110000000000001
     mask: 0b1110000000000011
+    attributes: [[name:no_cont], [name:cond]]
     size:   16
     branch:   true
     delay:   [1,1]
-  C__SLLI:
+  - CSLLI:
-    index: 77
     encoding: 0b0000000000000010
     mask: 0b1111000000000011
-    attributes: [[name:enable, value:1]]
     size:   16
     branch:   false
     delay:   1
-  C__LWSP:
+  - CLWSP:
-    index: 78
     encoding: 0b0100000000000010
     mask: 0b1110000000000011
     size:   16
     branch:   false
     delay:   1
-  C__MV:
+  - CMV:
-    index: 79
     encoding: 0b1000000000000010
     mask: 0b1111000000000011
     size:   16
     branch:   false
     delay:   1
-  C__JR:
+  - CJR:
-    index: 80
     encoding: 0b1000000000000010
     mask: 0b1111000001111111
+    attributes: [[name:no_cont]]
     size:   16
     branch:   true
     delay:   1
-  __reserved_cmv:
+  - CADD:
-    index: 81
-    encoding: 0b1000000000000010
-    mask: 0b1111111111111111
-    size:   16
-    branch:   false
-    delay:   1
-  C__ADD:
-    index: 82
     encoding: 0b1001000000000010
     mask: 0b1111000000000011
     size:   16
     branch:   false
     delay:   1
-  C__JALR:
+  - CJALR:
-    index: 83
     encoding: 0b1001000000000010
     mask: 0b1111000001111111
+    attributes: [[name:no_cont]]
     size:   16
     branch:   true
     delay:   1
-  C__EBREAK:
+  - CEBREAK:
-    index: 84
     encoding: 0b1001000000000010
     mask: 0b1111111111111111
+    attributes: [[name:no_cont]]
     size:   16
     branch:   false
     delay:   1
-  C__SWSP:
+  - CSWSP:
-    index: 85
     encoding: 0b1100000000000010
     mask: 0b1110000000000011
     size:   16
     branch:   false
     delay:   1
-  DII:
+  - DII:
-    index: 86
     encoding: 0b0000000000000000
     mask: 0b1111111111111111
+    attributes: [[name:no_cont]]
     size:   16
     branch:   false
     delay:   1

cmake/flink.cmake

@@ -1,35 +0,0 @@
-# according to https://github.com/horance-liu/flink.cmake/tree/master
-# SPDX-License-Identifier: Apache-2.0
-
-include(CMakeParseArguments)
-
-function(target_do_force_link_libraries target visibility lib)
-  if(MSVC)
-    target_link_libraries(${target} ${visibility} "/WHOLEARCHIVE:${lib}")
-  elseif(APPLE)
-    target_link_libraries(${target} ${visibility} -Wl,-force_load ${lib})
-  else()
-    target_link_libraries(${target} ${visibility} -Wl,--whole-archive ${lib} -Wl,--no-whole-archive)
-  endif()
-endfunction()
-
-function(target_force_link_libraries target)
-  cmake_parse_arguments(FLINK
-    ""
-    ""
-    "PUBLIC;INTERFACE;PRIVATE"
-    ${ARGN}
-  )
-  
-  foreach(lib IN LISTS FLINK_PUBLIC)
-    target_do_force_link_libraries(${target} PUBLIC ${lib})
-  endforeach()
-
-  foreach(lib IN LISTS FLINK_INTERFACE)
-    target_do_force_link_libraries(${target} INTERFACE ${lib})
-  endforeach()
-  
-  foreach(lib IN LISTS FLINK_PRIVATE)
-    target_do_force_link_libraries(${target} PRIVATE ${lib})
-  endforeach()
-endfunction()

contrib/README.md

@@ -19,7 +19,7 @@ setenv CXX $COWAREHOME/SLS/linux/common/bin/g++
 cmake -S . -B build/PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON \
     -DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=${TGFS_INSTALL_ROOT}
 cmake --build build/PA --target install -j16
-cd dbt-rise-tgc/contrib/pa
+cd dbt-rise-tgc/contrib
 # import the TGC core itself
 pct tgc_import_tb.tcl
 ```
@@ -37,7 +37,7 @@ export CXX=$COWAREHOME/SLS/linux/common/bin/g++
 cmake -S . -B build/PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON \
     -DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=${TGFS_INSTALL_ROOT}
 cmake --build build/PA --target install -j16
-cd dbt-rise-tgc/contrib/pa
+cd dbt-rise-tgc/contrib
 # import the TGC core itself
 pct tgc_import_tb.tcl
 ```

contrib/instr/.gitignore

@@ -1 +0,0 @@
-/*.yaml

contrib/instr/TGC5C_slow.yaml

@@ -1,650 +0,0 @@
-RV32I:
-  ADD:
-    branch: false
-    delay: 1
-    encoding: 51
-    index: 27
-    mask: 4261441663
-    size: 32
-  ADDI:
-    branch: false
-    delay: 1
-    encoding: 19
-    index: 18
-    mask: 28799
-    size: 32
-  AND:
-    branch: false
-    delay: 1
-    encoding: 28723
-    index: 36
-    mask: 4261441663
-    size: 32
-  ANDI:
-    branch: false
-    delay: 1
-    encoding: 28691
-    index: 23
-    mask: 28799
-    size: 32
-  AUIPC:
-    branch: false
-    delay: 1
-    encoding: 23
-    index: 1
-    mask: 127
-    size: 32
-  BEQ:
-    branch: true
-    delay:
-    - 1
-    - 2
-    encoding: 99
-    index: 4
-    mask: 28799
-    size: 32
-  BGE:
-    branch: true
-    delay:
-    - 1
-    - 2
-    encoding: 20579
-    index: 7
-    mask: 28799
-    size: 32
-  BGEU:
-    branch: true
-    delay:
-    - 1
-    - 2
-    encoding: 28771
-    index: 9
-    mask: 28799
-    size: 32
-  BLT:
-    branch: true
-    delay:
-    - 1
-    - 2
-    encoding: 16483
-    index: 6
-    mask: 28799
-    size: 32
-  BLTU:
-    branch: true
-    delay:
-    - 1
-    - 2
-    encoding: 24675
-    index: 8
-    mask: 28799
-    size: 32
-  BNE:
-    branch: true
-    delay:
-    - 1
-    - 2
-    encoding: 4195
-    index: 5
-    mask: 28799
-    size: 32
-  EBREAK:
-    attributes:
-    - - name:no_cont
-    branch: false
-    delay: 3
-    encoding: 1048691
-    index: 39
-    mask: 4294967295
-    size: 32
-  ECALL:
-    attributes:
-    - - name:no_cont
-    branch: false
-    delay: 1
-    encoding: 115
-    index: 38
-    mask: 4294967295
-    size: 32
-  FENCE:
-    branch: false
-    delay: 1
-    encoding: 15
-    index: 37
-    mask: 28799
-    size: 32
-  JAL:
-    branch: true
-    delay: 2
-    encoding: 111
-    index: 2
-    mask: 127
-    size: 32
-  JALR:
-    branch: true
-    delay: 2
-    encoding: 103
-    index: 3
-    mask: 28799
-    size: 32
-  LB:
-    branch: false
-    delay: 2
-    encoding: 3
-    index: 10
-    mask: 28799
-    size: 32
-  LBU:
-    branch: false
-    delay: 2
-    encoding: 16387
-    index: 13
-    mask: 28799
-    size: 32
-  LH:
-    branch: false
-    delay: 2
-    encoding: 4099
-    index: 11
-    mask: 28799
-    size: 32
-  LHU:
-    branch: false
-    delay: 2
-    encoding: 20483
-    index: 14
-    mask: 28799
-    size: 32
-  LUI:
-    branch: false
-    delay: 1
-    encoding: 55
-    index: 0
-    mask: 127
-    size: 32
-  LW:
-    branch: false
-    delay: 2
-    encoding: 8195
-    index: 12
-    mask: 28799
-    size: 32
-  MRET:
-    attributes:
-    - - name:no_cont
-    branch: false
-    delay: 2
-    encoding: 807403635
-    index: 40
-    mask: 4294967295
-    size: 32
-  OR:
-    branch: false
-    delay: 1
-    encoding: 24627
-    index: 35
-    mask: 4261441663
-    size: 32
-  ORI:
-    branch: false
-    delay: 1
-    encoding: 24595
-    index: 22
-    mask: 28799
-    size: 32
-  SB:
-    branch: false
-    delay: 1
-    encoding: 35
-    index: 15
-    mask: 28799
-    size: 32
-  SH:
-    branch: false
-    delay: 1
-    encoding: 4131
-    index: 16
-    mask: 28799
-    size: 32
-  SLL:
-    branch: false
-    delay: X_24:20
-    encoding: 4147
-    index: 29
-    mask: 4261441663
-    size: 32
-  SLLI:
-    branch: false
-    delay: u_24:20
-    encoding: 4115
-    index: 24
-    mask: 4261441663
-    size: 32
-  SLT:
-    branch: false
-    delay: 1
-    encoding: 8243
-    index: 30
-    mask: 4261441663
-    size: 32
-  SLTI:
-    branch: false
-    delay: 1
-    encoding: 8211
-    index: 19
-    mask: 28799
-    size: 32
-  SLTIU:
-    branch: false
-    delay: 1
-    encoding: 12307
-    index: 20
-    mask: 28799
-    size: 32
-  SLTU:
-    branch: false
-    delay: 1
-    encoding: 12339
-    index: 31
-    mask: 4261441663
-    size: 32
-  SRA:
-    branch: false
-    delay: X_24:20
-    encoding: 1073762355
-    index: 34
-    mask: 4261441663
-    size: 32
-  SRAI:
-    branch: false
-    delay: u_24:20
-    encoding: 1073762323
-    index: 26
-    mask: 4261441663
-    size: 32
-  SRL:
-    branch: false
-    delay: X_24:20
-    encoding: 20531
-    index: 33
-    mask: 4261441663
-    size: 32
-  SRLI:
-    branch: false
-    delay: u_24:20
-    encoding: 20499
-    index: 25
-    mask: 4261441663
-    size: 32
-  SUB:
-    branch: false
-    delay: 1
-    encoding: 1073741875
-    index: 28
-    mask: 4261441663
-    size: 32
-  SW:
-    branch: false
-    delay: 1
-    encoding: 8227
-    index: 17
-    mask: 28799
-    size: 32
-  WFI:
-    branch: false
-    delay: 1
-    encoding: 273678451
-    index: 41
-    mask: 4294967295
-    size: 32
-  XOR:
-    branch: false
-    delay: 1
-    encoding: 16435
-    index: 32
-    mask: 4261441663
-    size: 32
-  XORI:
-    branch: false
-    delay: 1
-    encoding: 16403
-    index: 21
-    mask: 28799
-    size: 32
-RV32M:
-  DIV:
-    branch: false
-    delay: 33
-    encoding: 33570867
-    index: 53
-    mask: 4261441663
-    size: 32
-  DIVU:
-    branch: false
-    delay: 33
-    encoding: 33574963
-    index: 54
-    mask: 4261441663
-    size: 32
-  MUL:
-    branch: false
-    delay: 32
-    encoding: 33554483
-    index: 49
-    mask: 4261441663
-    size: 32
-  MULH:
-    branch: false
-    delay: 32
-    encoding: 33558579
-    index: 50
-    mask: 4261441663
-    size: 32
-  MULHSU:
-    branch: false
-    delay: 32
-    encoding: 33562675
-    index: 51
-    mask: 4261441663
-    size: 32
-  MULHU:
-    branch: false
-    delay: 32
-    encoding: 33566771
-    index: 52
-    mask: 4261441663
-    size: 32
-  REM:
-    branch: false
-    delay: 33
-    encoding: 33579059
-    index: 55
-    mask: 4261441663
-    size: 32
-  REMU:
-    branch: false
-    delay: 33
-    encoding: 33583155
-    index: 56
-    mask: 4261441663
-    size: 32
-Zca:
-  C__ADD:
-    branch: false
-    delay: 1
-    encoding: 36866
-    index: 82
-    mask: 61443
-    size: 16
-  C__ADDI:
-    branch: false
-    delay: 1
-    encoding: 1
-    index: 60
-    mask: 57347
-    size: 16
-  C__ADDI16SP:
-    branch: false
-    delay: 1
-    encoding: 24833
-    index: 65
-    mask: 61315
-    size: 16
-  C__ADDI4SPN:
-    branch: false
-    delay: 1
-    encoding: 0
-    index: 57
-    mask: 57347
-    size: 16
-  C__AND:
-    branch: false
-    delay: 1
-    encoding: 35937
-    index: 73
-    mask: 64611
-    size: 16
-  C__ANDI:
-    branch: false
-    delay: 1
-    encoding: 34817
-    index: 69
-    mask: 60419
-    size: 16
-  C__BEQZ:
-    branch: true
-    delay:
-    - 1
-    - 2
-    encoding: 49153
-    index: 75
-    mask: 57347
-    size: 16
-  C__BNEZ:
-    branch: true
-    delay:
-    - 1
-    - 2
-    encoding: 57345
-    index: 76
-    mask: 57347
-    size: 16
-  C__EBREAK:
-    branch: false
-    delay: 3
-    encoding: 36866
-    index: 84
-    mask: 65535
-    size: 16
-  C__J:
-    branch: true
-    delay: 1
-    encoding: 40961
-    index: 74
-    mask: 57347
-    size: 16
-  C__JAL:
-    attributes:
-    - - name:enable
-      - value:1
-    branch: true
-    delay: 1
-    encoding: 8193
-    index: 62
-    mask: 57347
-    size: 16
-  C__JALR:
-    branch: true
-    delay: 1
-    encoding: 36866
-    index: 83
-    mask: 61567
-    size: 16
-  C__JR:
-    branch: true
-    delay: 1
-    encoding: 32770
-    index: 80
-    mask: 61567
-    size: 16
-  C__LI:
-    branch: false
-    delay: 1
-    encoding: 16385
-    index: 63
-    mask: 57347
-    size: 16
-  C__LUI:
-    branch: false
-    delay: 1
-    encoding: 24577
-    index: 64
-    mask: 57347
-    size: 16
-  C__LW:
-    branch: false
-    delay: 2
-    encoding: 16384
-    index: 58
-    mask: 57347
-    size: 16
-  C__LWSP:
-    branch: false
-    delay: 2
-    encoding: 16386
-    index: 78
-    mask: 57347
-    size: 16
-  C__MV:
-    branch: false
-    delay: 1
-    encoding: 32770
-    index: 79
-    mask: 61443
-    size: 16
-  C__NOP:
-    branch: false
-    delay: 1
-    encoding: 1
-    index: 61
-    mask: 61315
-    size: 16
-  C__OR:
-    branch: false
-    delay: 1
-    encoding: 35905
-    index: 72
-    mask: 64611
-    size: 16
-  C__SLLI:
-    attributes:
-    - - name:enable
-      - value:1
-    branch: false
-    delay: u_12:12*16+u_6:2
-    encoding: 2
-    index: 77
-    mask: 61443
-    size: 16
-  C__SRAI:
-    attributes:
-    - - name:enable
-      - value:1
-    branch: false
-    delay: u_12:12*16+u_6:2
-    encoding: 33793
-    index: 68
-    mask: 64515
-    size: 16
-  C__SRLI:
-    attributes:
-    - - name:enable
-      - value:1
-    branch: false
-    delay: u_12:12*16+u_6:2
-    encoding: 32769
-    index: 67
-    mask: 64515
-    size: 16
-  C__SUB:
-    branch: false
-    delay: 1
-    encoding: 35841
-    index: 70
-    mask: 64611
-    size: 16
-  C__SW:
-    branch: false
-    delay: 1
-    encoding: 49152
-    index: 59
-    mask: 57347
-    size: 16
-  C__SWSP:
-    branch: false
-    delay: 1
-    encoding: 49154
-    index: 85
-    mask: 57347
-    size: 16
-  C__XOR:
-    branch: false
-    delay: 1
-    encoding: 35873
-    index: 71
-    mask: 64611
-    size: 16
-  DII:
-    branch: false
-    delay: 1
-    encoding: 0
-    index: 86
-    mask: 65535
-    size: 16
-  __reserved_clui:
-    branch: false
-    delay: 1
-    encoding: 24577
-    index: 66
-    mask: 61567
-    size: 16
-  __reserved_cmv:
-    branch: false
-    delay: 1
-    encoding: 32770
-    index: 81
-    mask: 65535
-    size: 16
-Zicsr:
-  CSRRC:
-    branch: false
-    delay: 1
-    encoding: 12403
-    index: 44
-    mask: 28799
-    size: 32
-  CSRRCI:
-    branch: false
-    delay: 1
-    encoding: 28787
-    index: 47
-    mask: 28799
-    size: 32
-  CSRRS:
-    branch: false
-    delay: 1
-    encoding: 8307
-    index: 43
-    mask: 28799
-    size: 32
-  CSRRSI:
-    branch: false
-    delay: 1
-    encoding: 24691
-    index: 46
-    mask: 28799
-    size: 32
-  CSRRW:
-    branch: false
-    delay: 1
-    encoding: 4211
-    index: 42
-    mask: 28799
-    size: 32
-  CSRRWI:
-    branch: false
-    delay: 1
-    encoding: 20595
-    index: 45
-    mask: 28799
-    size: 32
-Zifencei:
-  FENCE_I:
-    attributes:
-    - - name:flush
-    branch: false
-    delay: 1
-    encoding: 4111
-    index: 48
-    mask: 28799
-    size: 32

gen_input/TGC_C.core_desc

@@ -1,8 +1,8 @@
-import "ISA/RVI.core_desc"
+import "ISA/RV32I.core_desc"
 import "ISA/RVM.core_desc"
 import "ISA/RVC.core_desc"
 
-Core TGC5C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
+Core TGC_C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
     architectural_state {
         XLEN=32;
         // definitions for the architecture wrapper

gen_input/templates/CORENAME.cpp.gtl

@@ -37,7 +37,6 @@ def getRegisterSizes(){
     return regs
 }
 %>
-// clang-format off
 #include "${coreDef.name.toLowerCase()}.h"
 #include "util/ities.h"
 #include <util/logging.h>
@@ -71,7 +70,7 @@ uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
 	return reinterpret_cast<uint8_t*>(&reg);
 }
 
-${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &addr) {
+${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
-    return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
+    return phys_addr_t(pc); // change logical address to physical address
 }
-// clang-format on
+

gen_input/templates/CORENAME.h.gtl

@@ -55,12 +55,12 @@ def byteSize(int size){
     return 128;
 }
 def getCString(def val){
-    return val.toString()+'ULL'
+    return val.toString()
 }
 %>
 #ifndef _${coreDef.name.toUpperCase()}_H_
 #define _${coreDef.name.toUpperCase()}_H_
-// clang-format off
+
 #include <array>
 #include <iss/arch/traits.h>
 #include <iss/arch_if.h>
@@ -76,10 +76,10 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
     constexpr static char const* const core_type = "${coreDef.name}";
     
     static constexpr std::array<const char*, ${registers.size}> reg_names{
-        {"${registers.collect{it.name.toLowerCase()}.join('", "')}"}};
+        {"${registers.collect{it.name}.join('", "')}"}};
  
     static constexpr std::array<const char*, ${registers.size}> reg_aliases{
-        {"${registers.collect{it.alias.toLowerCase()}.join('", "')}"}};
+        {"${registers.collect{it.alias}.join('", "')}"}};
 
     enum constants {${constants.collect{c -> c.name+"="+getCString(c.value)}.join(', ')}};
 
@@ -137,6 +137,14 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
 
     inline uint64_t stop_code() { return interrupt_sim; }
 
+    inline phys_addr_t v2p(const iss::addr_t& addr){
+        if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
+                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
+            return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
+        } else
+            return virt2phys(addr);
+    }
+
     virtual phys_addr_t virt2phys(const iss::addr_t& addr);
 
     virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
@@ -174,4 +182,3 @@ if(fcsr != null) {%>
 }
 }            
 #endif /* _${coreDef.name.toUpperCase()}_H_ */
-// clang-format on

gen_input/templates/CORENAME_decoder.cpp.gtl

@@ -0,0 +1,86 @@
+#include "${coreDef.name.toLowerCase()}.h"
+#include <vector>
+#include <array>
+#include <cstdlib>
+#include <algorithm>
+
+namespace iss {
+namespace arch {
+namespace {
+// according to
+// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
+#ifdef __GCC__
+constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); }
+#elif __cplusplus < 201402L
+constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); }
+constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; }
+#else
+constexpr size_t bit_count(uint32_t u) {
+    size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111);
+    return ((uCount + (uCount >> 3)) & 030707070707) % 63;
+}
+#endif
+
+using opcode_e = traits<${coreDef.name.toLowerCase()}>::opcode_e;
+
+/****************************************************************************
+ * start opcode definitions
+ ****************************************************************************/
+struct instruction_desriptor {
+    size_t length;
+    uint32_t value;
+    uint32_t mask;
+    opcode_e op;
+};
+
+const std::array<instruction_desriptor, ${instructions.size}> instr_descr = {{
+     /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
+    {${instr.length}, ${instr.encoding}, ${instr.mask}, opcode_e::${instr.instruction.name}},<%}%>
+}};
+
+}
+
+template<>
+struct instruction_decoder<${coreDef.name.toLowerCase()}> {
+    using opcode_e = traits<${coreDef.name.toLowerCase()}>::opcode_e;
+    using code_word_t=traits<${coreDef.name.toLowerCase()}>::code_word_t;
+
+    struct instruction_pattern {
+        uint32_t value;
+        uint32_t mask;
+        opcode_e id;
+    };
+
+    std::array<std::vector<instruction_pattern>, 4> qlut;
+
+    template<typename T>
+    unsigned decode_instruction(T);
+
+    instruction_decoder() {
+        for (auto instr : instr_descr) {
+            auto quadrant = instr.value & 0x3;
+            qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
+        }
+        for(auto& lut: qlut){
+            std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
+                return bit_count(a.mask) < bit_count(b.mask);
+            });
+        }
+    }
+};
+
+template<>
+unsigned instruction_decoder<${coreDef.name.toLowerCase()}>::decode_instruction<traits<${coreDef.name.toLowerCase()}>::code_word_t>(traits<${coreDef.name.toLowerCase()}>::code_word_t instr){
+    auto res = std::find_if(std::begin(qlut[instr&0x3]), std::end(qlut[instr&0x3]), [instr](instruction_pattern const& e){
+        return !((instr&e.mask) ^ e.value );
+    });
+    return static_cast<unsigned>(res!=std::end(qlut[instr&0x3])? res->id : opcode_e::MAX_OPCODE);
+}
+
+
+std::unique_ptr<instruction_decoder<${coreDef.name.toLowerCase()}>> traits<${coreDef.name.toLowerCase()}>::get_decoder(){
+    return std::make_unique<instruction_decoder<${coreDef.name.toLowerCase()}>>();
+}
+
+}
+}

gen_input/templates/CORENAME_instr.yaml.gtl

@@ -8,10 +8,9 @@
         instrGroups[groupName]+=it;
     }
     instrGroups
-}%><%int index = 0; getInstructionGroups().each{name, instrList -> %>
+}%><%getInstructionGroups().each{name, instrList -> %>
-${name}: <% instrList.each { %>
+${name}: <% instrList.findAll{!it.instruction.name.startsWith("__")}.each { %>
-  ${it.instruction.name}:
+  - ${it.instruction.name}:
-    index: ${index++}
     encoding: ${it.encoding}
     mask: ${it.mask}<%if(it.attributes.size) {%>
     attributes: ${it.attributes}<%}%>

gen_input/templates/CORENAME_sysc.cpp.gtl

@@ -1,131 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2023 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-// clang-format off
-#include <sysc/iss_factory.h>
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_mu_p.h>
-#include <sysc/sc_core_adapter.h>
-#include <sysc/core_complex.h>
-#include <array>
-<%
-def array_count = coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e"? 3 : 2;
-%>
-namespace iss {
-namespace interp {
-using namespace sysc;
-volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        }),
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        })<%}%>
-};
-}
-#if defined(WITH_LLVM)
-namespace llvm {
-using namespace sysc;
-volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        }),
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        })<%}%>
-};
-}
-#endif
-#if defined(WITH_TCC)
-namespace tcc {
-using namespace sysc;
-volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        }),
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        })<%}%>
-};
-}
-#endif
-#if defined(WITH_ASMJIT)
-namespace asmjit {
-using namespace sysc;
-volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        }),
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        })<%}%>
-};
-}
-#endif
-}
-// clang-format on

gen_input/templates/asmjit/CORENAME.cpp.gtl

@@ -1,281 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017, 2023 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-// clang-format off
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <iss/debugger/gdb_session.h>
-#include <iss/debugger/server.h>
-#include <iss/iss.h>
-#include <iss/asmjit/vm_base.h>
-#include <asmjit/asmjit.h>
-#include <util/logging.h>
-
-#ifndef FMT_HEADER_ONLY
-#define FMT_HEADER_ONLY
-#endif
-#include <fmt/format.h>
-
-#include <array>
-#include <iss/debugger/riscv_target_adapter.h>
-
-namespace iss {
-namespace asmjit {
-
-
-namespace ${coreDef.name.toLowerCase()} {
-using namespace ::asmjit;
-using namespace iss::arch;
-using namespace iss::debugger;
-
-template <typename ARCH> class vm_impl : public iss::asmjit::vm_base<ARCH> {
-public:
-    using traits = arch::traits<ARCH>;
-    using super = typename iss::asmjit::vm_base<ARCH>;
-    using virt_addr_t = typename super::virt_addr_t;
-    using phys_addr_t = typename super::phys_addr_t;
-    using code_word_t = typename super::code_word_t;
-    using mem_type_e = typename super::mem_type_e;
-    using addr_t = typename super::addr_t;
-
-    vm_impl();
-
-    vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
-
-    void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
-
-    target_adapter_if *accquire_target_adapter(server_if *srv) override {
-        debugger_if::dbg_enabled = true;
-        if (vm_base<ARCH>::tgt_adapter == nullptr)
-            vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
-        return vm_base<ARCH>::tgt_adapter;
-    }
-
-protected:
-    using vm_base<ARCH>::get_reg_ptr;
-    using this_class = vm_impl<ARCH>;
-    using compile_func = continuation_e (this_class::*)(virt_addr_t&, code_word_t, jit_holder&);
-
-    continuation_e gen_single_inst_behavior(virt_addr_t&, unsigned int &, jit_holder&) override;
-    inline const char *name(size_t index){return traits::reg_aliases.at(index);}
-
-    template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
-    inline S sext(U from) {
-        auto mask = (1ULL<<W) - 1;
-        auto sign_mask = 1ULL<<(W-1);
-        return (from & mask) | ((from & sign_mask) ? ~mask : 0);
-    } 
-#include <vm/asmjit/helper_func.h>
-
-private:
-    /****************************************************************************
-     * start opcode definitions
-     ****************************************************************************/
-    struct instruction_descriptor {
-        size_t length;
-        uint32_t value;
-        uint32_t mask;
-        compile_func op;
-    };
-    struct decoding_tree_node{
-        std::vector<instruction_descriptor> instrs;
-        std::vector<decoding_tree_node*> children;
-        uint32_t submask = std::numeric_limits<uint32_t>::max();
-        uint32_t value;
-        decoding_tree_node(uint32_t value) : value(value){}
-    };
-
-    decoding_tree_node* root {nullptr};
-
-    const std::array<instruction_descriptor, ${instructions.size}> instr_descr = {{
-         /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
-        /* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
-        {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
-    }};
- 
-    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
-    /* instruction ${idx}: ${instr.name} */
-    continuation_e __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, jit_holder& jh){
-        uint64_t PC = pc.val;
-        <%instr.fields.eachLine{%>${it}
-        <%}%>if(this->disass_enabled){
-            /* generate disass */
-        }
-        x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\\n${instr.name}_{:#x}:",pc.val).c_str());
-        this->gen_sync(jh, PRE_SYNC, ${idx});
-        pc=pc+ ${instr.length/8};
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\\n//behavior:");
-        /*generate behavior*/
-        <%instr.behavior.eachLine{%>${it}
-        <%}%>
-        gen_instr_epilogue(jh);
-        this->gen_sync(jh, POST_SYNC, ${idx});
-    	return returnValue;        
-    }
-    <%}%>
-    /****************************************************************************
-     * end opcode definitions
-     ****************************************************************************/
-    continuation_e illegal_intruction(virt_addr_t &pc, code_word_t instr, jit_holder& jh ) {
-
-        return BRANCH;
-    }    
-    //decoding functionality
-
-    void populate_decoding_tree(decoding_tree_node* root){
-        //create submask
-        for(auto instr: root->instrs){
-            root->submask &= instr.mask;
-        }
-        //put each instr according to submask&encoding into children
-        for(auto instr: root->instrs){
-            bool foundMatch = false;
-            for(auto child: root->children){
-                //use value as identifying trait
-                if(child->value == (instr.value&root->submask)){
-                    child->instrs.push_back(instr);
-                    foundMatch = true;
-                }
-            }
-            if(!foundMatch){
-                decoding_tree_node* child = new decoding_tree_node(instr.value&root->submask);
-                child->instrs.push_back(instr);
-                root->children.push_back(child);
-            }
-        }
-        root->instrs.clear();
-        //call populate_decoding_tree for all children
-        if(root->children.size() >1)
-            for(auto child: root->children){
-                populate_decoding_tree(child);      
-            }
-        else{
-            //sort instrs by value of the mask, this works bc we want to have the least restrictive one last
-            std::sort(root->children[0]->instrs.begin(), root->children[0]->instrs.end(), [](const instruction_descriptor& instr1, const instruction_descriptor& instr2) {
-            return instr1.mask > instr2.mask;
-            }); 
-        }
-    }
-    compile_func decode_instr(decoding_tree_node* node, code_word_t word){
-        if(!node->children.size()){
-            if(node->instrs.size() == 1) return node->instrs[0].op;
-            for(auto instr : node->instrs){
-                if((instr.mask&word) == instr.value) return instr.op;
-            }
-        }
-        else{
-            for(auto child : node->children){
-                if (child->value == (node->submask&word)){
-                    return decode_instr(child, word);
-                }  
-            }  
-        }
-        return nullptr;
-    }
-};
-
-template <typename CODE_WORD> void debug_fn(CODE_WORD instr) {
-    volatile CODE_WORD x = instr;
-    instr = 2 * x;
-}
-
-template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
-
-template <typename ARCH>
-vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
-: vm_base<ARCH>(core, core_id, cluster_id) {
-    root = new decoding_tree_node(std::numeric_limits<uint32_t>::max());
-    for(auto instr: instr_descr){
-        root->instrs.push_back(instr);
-    }
-    populate_decoding_tree(root);
-}
-
-template <typename ARCH>
-continuation_e
-vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, jit_holder& jh) {
-    enum {TRAP_ID=1<<16};
-    code_word_t instr = 0;
-    phys_addr_t paddr(pc);
-    auto *const data = (uint8_t *)&instr;
-    if(this->core.has_mmu())
-        paddr = this->core.virt2phys(pc);
-    auto res = this->core.read(paddr, 4, data);
-    if (res != iss::Ok)
-        throw trap_access(TRAP_ID, pc.val);
-    if (instr == 0x0000006f || (instr&0xffff)==0xa001)
-        throw simulation_stopped(0); // 'J 0' or 'C.J 0'
-    ++inst_cnt;
-    auto f = decode_instr(root, instr);
-    if (f == nullptr) 
-        f = &this_class::illegal_intruction;
-    return (this->*f)(pc, instr, jh);
-}
-
-
-
-} // namespace ${coreDef.name.toLowerCase()}
-
-template <>
-std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
-    auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
-    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
-    return std::unique_ptr<vm_if>(ret);
-}
-} // namespace asmjit
-} // namespace iss
-
-#include <iss/factory.h>
-#include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_mu_p.h>
-namespace iss {
-namespace {
-volatile std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|asmjit", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
-            auto* vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
-            if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            return {cpu_ptr{cpu}, vm_ptr{vm}};
-        }),
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|asmjit", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
-            auto* vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
-            if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            return {cpu_ptr{cpu}, vm_ptr{vm}};
-        })
-};
-}
-}
-// clang-format on

gen_input/templates/interp/CORENAME.cpp.gtl

@@ -34,19 +34,15 @@ def nativeTypeSize(int size){
     if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
 }
 %>
-// clang-format off
 #include <iss/arch/${coreDef.name.toLowerCase()}.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
 #include <iss/iss.h>
 #include <iss/interp/vm_base.h>
-#include <vm/fp_functions.h>
 #include <util/logging.h>
+#include <sstream>
 #include <boost/coroutine2/all.hpp>
 #include <functional>
-#include <exception>
-#include <vector>
-#include <sstream>
 
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
@@ -63,10 +59,6 @@ using namespace iss::arch;
 using namespace iss::debugger;
 using namespace std::placeholders;
 
-struct memory_access_exception : public std::exception{
-    memory_access_exception(){}
-};
-
 template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
 public:
     using traits = arch::traits<ARCH>;
@@ -99,9 +91,30 @@ protected:
 
     inline const char *name(size_t index){return index<traits::reg_aliases.size()?traits::reg_aliases[index]:"illegal";}
 
+    typename arch::traits<ARCH>::opcode_e decode_inst_id(code_word_t instr);
     virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;
 
     // some compile time constants
+    // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
+    enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
+    enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
+    enum {
+        LUT_SIZE = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK32)),
+        LUT_SIZE_C = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK16))
+    };
+
+    std::array<compile_func, LUT_SIZE> lut;
+
+    std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
+    std::array<compile_func, LUT_SIZE> lut_11;
+
+    struct instruction_pattern {
+        uint32_t value;
+        uint32_t mask;
+        typename arch::traits<ARCH>::opcode_e id;
+    };
+
+    std::array<std::vector<instruction_pattern>, 4> qlut;
 
     inline void raise(uint16_t trap_id, uint16_t cause){
         auto trap_val =  0x80ULL << 24 | (cause << 16) | trap_id;
@@ -145,96 +158,30 @@ private:
     /****************************************************************************
      * start opcode definitions
      ****************************************************************************/
-    struct instruction_descriptor {
+    struct InstructionDesriptor {
         size_t length;
         uint32_t value;
         uint32_t mask;
         typename arch::traits<ARCH>::opcode_e op;
     };
-    struct decoding_tree_node{
-        std::vector<instruction_descriptor> instrs;
-        std::vector<decoding_tree_node*> children;
-        uint32_t submask = std::numeric_limits<uint32_t>::max();
-        uint32_t value;
-        decoding_tree_node(uint32_t value) : value(value){}
-    };
 
-    decoding_tree_node* root {nullptr};
+    const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
-    const std::array<instruction_descriptor, ${instructions.size}> instr_descr = {{
          /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
         {${instr.length}, ${instr.encoding}, ${instr.mask}, arch::traits<ARCH>::opcode_e::${instr.instruction.name}},<%}%>
     }};
 
+    //static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK;
     iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
-        if(this->core.has_mmu()) {
+        auto phys_pc = this->core.v2p(pc);
-            auto phys_pc = this->core.virt2phys(pc);
         //if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
         //    if (this->core.read(phys_pc, 2, data) != iss::Ok) return iss::Err;
         //    if ((data[0] & 0x3) == 0x3) // this is a 32bit instruction
-//                    if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok)
+        //        if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok) return iss::Err;
-//                        return iss::Err;
         //} else {
-                if (this->core.read(phys_pc, 4, data) != iss::Ok)
+            if (this->core.read(phys_pc, 4, data) != iss::Ok)  return iss::Err;
-                    return iss::Err;
         //}
-        } else {
-            if (this->core.read(phys_addr_t(pc.access, pc.space, pc.val), 4, data) != iss::Ok)
-                return iss::Err;
-
-        }
         return iss::Ok;
     }
-    
-    void populate_decoding_tree(decoding_tree_node* root){
-        //create submask
-        for(auto instr: root->instrs){
-            root->submask &= instr.mask;
-        }
-        //put each instr according to submask&encoding into children
-        for(auto instr: root->instrs){
-            bool foundMatch = false;
-            for(auto child: root->children){
-                //use value as identifying trait
-                if(child->value == (instr.value&root->submask)){
-                    child->instrs.push_back(instr);
-                    foundMatch = true;
-                }
-            }
-            if(!foundMatch){
-                decoding_tree_node* child = new decoding_tree_node(instr.value&root->submask);
-                child->instrs.push_back(instr);
-                root->children.push_back(child);
-            }
-        }
-        root->instrs.clear();
-        //call populate_decoding_tree for all children
-        if(root->children.size() >1)
-            for(auto child: root->children){
-                populate_decoding_tree(child);      
-            }
-        else{
-            //sort instrs by value of the mask, this works bc we want to have the least restrictive one last
-            std::sort(root->children[0]->instrs.begin(), root->children[0]->instrs.end(), [](const instruction_descriptor& instr1, const instruction_descriptor& instr2) {
-            return instr1.mask > instr2.mask;
-            }); 
-        }
-    }
-    typename arch::traits<ARCH>::opcode_e  decode_instr(decoding_tree_node* node, code_word_t word){
-        if(!node->children.size()){
-            if(node->instrs.size() == 1) return node->instrs[0].op;
-            for(auto instr : node->instrs){
-                if((instr.mask&word) == instr.value) return instr.op;
-            }
-        }
-        else{
-            for(auto child : node->children){
-                if (child->value == (node->submask&word)){
-                    return decode_instr(child, word);
-                }  
-            }  
-        }
-        return arch::traits<ARCH>::opcode_e::MAX_OPCODE;
-    }
 };
 
 template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
@@ -261,11 +208,16 @@ constexpr size_t bit_count(uint32_t u) {
 template <typename ARCH>
 vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
 : vm_base<ARCH>(core, core_id, cluster_id) {
-    root = new decoding_tree_node(std::numeric_limits<uint32_t>::max());
+    unsigned id=0;
     for (auto instr : instr_descr) {
-        root->instrs.push_back(instr);
+        auto quadrant = instr.value & 0x3;
+        qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
+    }
+    for(auto& lut: qlut){
+        std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
+            return bit_count(a.mask) > bit_count(b.mask);
+        });
     }
-    populate_decoding_tree(root);
 }
 
 inline bool is_count_limit_enabled(finish_cond_e cond){
@@ -276,6 +228,14 @@ inline bool is_jump_to_self_enabled(finish_cond_e cond){
     return (cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF;
 }
 
+template <typename ARCH>
+typename arch::traits<ARCH>::opcode_e vm_impl<ARCH>::decode_inst_id(code_word_t instr){
+    for(auto& e: qlut[instr&0x3]){
+        if(!((instr&e.mask) ^ e.value )) return e.id;
+    }
+    return arch::traits<ARCH>::opcode_e::MAX_OPCODE;
+}
+
 template <typename ARCH>
 typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
     auto pc=start;
@@ -297,11 +257,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
         } else {
             if (is_jump_to_self_enabled(cond) &&
                     (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
-            auto inst_id = decode_instr(root, instr);
+            auto inst_id = decode_inst_id(instr);
             // pre execution stuff
              this->core.reg.last_branch = 0;
             if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
-            try{
             switch(inst_id){<%instructions.eachWithIndex{instr, idx -> %>
             case arch::traits<ARCH>::opcode_e::${instr.name}: {
                 <%instr.fields.eachLine{%>${it}
@@ -317,14 +276,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 *NEXT_PC = *PC + ${instr.length/8};
                 // execute instruction<%instr.behavior.eachLine{%>
                 ${it}<%}%>
-                    break;
+                TRAP_${instr.name}:break;
             }// @suppress("No break at end of case")<%}%>
             default: {
                 *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
                 raise(0,  2);
             }
             }
-            }catch(memory_access_exception& e){}
             // post execution stuff
             process_spawn_blocks();
             if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
@@ -346,7 +304,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
     return pc;
 }
 
-} // namespace ${coreDef.name.toLowerCase()}
+}
 
 template <>
 std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
@@ -362,7 +320,7 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
 #include <iss/arch/riscv_hart_mu_p.h>
 namespace iss {
 namespace {
-volatile std::array<bool, 2> dummy = {
+std::array<bool, 2> dummy = {
         core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
             auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
 		    auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
@@ -378,4 +336,8 @@ volatile std::array<bool, 2> dummy = {
 };
 }
 }
-// clang-format on
+extern "C" {
+	bool* get_${coreDef.name.toLowerCase()}_interp_creators() {
+		return iss::dummy.data();
+	}
+}

gen_input/templates/llvm/CORENAME_cyles.txt.gtl

@@ -0,0 +1,9 @@
+{ 
+	"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
+		{
+			"name"  : "${instr.name}",
+			"size"  : ${instr.length},
+			"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
+		}<%}%>
+	]
+}

gen_input/templates/llvm/incl-CORENAME.h.gtl

@@ -0,0 +1,223 @@
+/*******************************************************************************
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+<% 
+import com.minres.coredsl.coreDsl.Register
+import com.minres.coredsl.coreDsl.RegisterFile
+import com.minres.coredsl.coreDsl.RegisterAlias
+def getTypeSize(size){
+	if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
+}
+def getOriginalName(reg){
+    if( reg.original instanceof RegisterFile) {
+    	if( reg.index != null ) {
+        	return reg.original.name+generator.generateHostCode(reg.index)
+        } else {
+        	return reg.original.name
+        }
+    } else if(reg.original instanceof Register){
+        return reg.original.name
+    }
+}
+def getRegisterNames(){
+	def regNames = []
+ 	allRegs.each { reg -> 
+		if( reg instanceof RegisterFile) {
+			(reg.range.right..reg.range.left).each{
+    			regNames+=reg.name.toLowerCase()+it
+            }
+        } else if(reg instanceof Register){
+    		regNames+=reg.name.toLowerCase()
+        }
+    }
+    return regNames
+}
+def getRegisterAliasNames(){
+	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
+ 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
+		if( reg instanceof RegisterFile) {
+			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
+        } else if(reg instanceof Register){
+    		regMap[reg.name]?:reg.name.toLowerCase()
+        }
+ 	}.flatten()
+}
+%>
+#ifndef _${coreDef.name.toUpperCase()}_H_
+#define _${coreDef.name.toUpperCase()}_H_
+
+#include <array>
+#include <iss/arch/traits.h>
+#include <iss/arch_if.h>
+#include <iss/vm_if.h>
+
+namespace iss {
+namespace arch {
+
+struct ${coreDef.name.toLowerCase()};
+
+template <> struct traits<${coreDef.name.toLowerCase()}> {
+
+	constexpr static char const* const core_type = "${coreDef.name}";
+    
+  	static constexpr std::array<const char*, ${getRegisterNames().size}> reg_names{
+ 		{"${getRegisterNames().join("\", \"")}"}};
+ 
+  	static constexpr std::array<const char*, ${getRegisterAliasNames().size}> reg_aliases{
+ 		{"${getRegisterAliasNames().join("\", \"")}"}};
+
+    enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
+
+    constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
+
+    enum reg_e {<%
+     	allRegs.each { reg -> 
+    		if( reg instanceof RegisterFile) {
+    			(reg.range.right..reg.range.left).each{%>
+        ${reg.name}${it},<%
+                }
+            } else if(reg instanceof Register){ %>
+        ${reg.name},<%  
+            }
+        }%>
+        NUM_REGS,
+        NEXT_${pc.name}=NUM_REGS,
+        TRAP_STATE,
+        PENDING_TRAP,
+        MACHINE_STATE,
+        LAST_BRANCH,
+        ICOUNT<% 
+     	allRegs.each { reg -> 
+    		if(reg instanceof RegisterAlias){ def aliasname=getOriginalName(reg)%>,
+        ${reg.name} = ${aliasname}<%
+            }
+        }%>
+    };
+
+    using reg_t = uint${regDataWidth}_t;
+
+    using addr_t = uint${addrDataWidth}_t;
+
+    using code_word_t = uint${addrDataWidth}_t; //TODO: check removal
+
+    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
+
+    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
+
+ 	static constexpr std::array<const uint32_t, ${regSizes.size}> reg_bit_widths{
+ 		{${regSizes.join(",")}}};
+
+    static constexpr std::array<const uint32_t, ${regOffsets.size}> reg_byte_offsets{
+    	{${regOffsets.join(",")}}};
+
+    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
+
+    enum sreg_flag_e { FLAGS };
+
+    enum mem_type_e { ${allSpaces.collect{s -> s.name}.join(', ')} };
+};
+
+struct ${coreDef.name.toLowerCase()}: public arch_if {
+
+    using virt_addr_t = typename traits<${coreDef.name.toLowerCase()}>::virt_addr_t;
+    using phys_addr_t = typename traits<${coreDef.name.toLowerCase()}>::phys_addr_t;
+    using reg_t =  typename traits<${coreDef.name.toLowerCase()}>::reg_t;
+    using addr_t = typename traits<${coreDef.name.toLowerCase()}>::addr_t;
+
+    ${coreDef.name.toLowerCase()}();
+    ~${coreDef.name.toLowerCase()}();
+
+    void reset(uint64_t address=0) override;
+
+    uint8_t* get_regs_base_ptr() override;
+    /// deprecated
+    void get_reg(short idx, std::vector<uint8_t>& value) override {}
+    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
+    /// deprecated
+    bool get_flag(int flag) override {return false;}
+    void set_flag(int, bool value) override {};
+    /// deprecated
+    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
+
+    inline uint64_t get_icount() { return reg.icount; }
+
+    inline bool should_stop() { return interrupt_sim; }
+
+    inline uint64_t stop_code() { return interrupt_sim; }
+
+    inline phys_addr_t v2p(const iss::addr_t& addr){
+        if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
+                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
+            return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
+        } else
+            return virt2phys(addr);
+    }
+
+    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
+
+    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
+
+    inline uint32_t get_last_branch() { return reg.last_branch; }
+
+protected:
+    struct ${coreDef.name}_regs {<%
+     	allRegs.each { reg -> 
+    		if( reg instanceof RegisterFile) {
+    			(reg.range.right..reg.range.left).each{%>
+        uint${generator.getSize(reg)}_t ${reg.name}${it} = 0;<%
+                }
+            } else if(reg instanceof Register){ %>
+        uint${generator.getSize(reg)}_t ${reg.name} = 0;<%
+            }
+        }%>
+        uint${generator.getSize(pc)}_t NEXT_${pc.name} = 0;
+        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
+        uint64_t icount = 0;
+    } reg;
+
+    std::array<address_type, 4> addr_mode;
+    
+    uint64_t interrupt_sim=0;
+<%
+def fcsr = allRegs.find {it.name=='FCSR'}
+if(fcsr != null) {%>
+	uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
+	void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}		
+<%} else { %>
+	uint32_t get_fcsr(){return 0;}
+	void set_fcsr(uint32_t val){}
+<%}%>
+};
+
+}
+}            
+#endif /* _${coreDef.name.toUpperCase()}_H_ */

gen_input/templates/llvm/src-CORENAME.cpp.gtl

@@ -0,0 +1,107 @@
+/*******************************************************************************
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+ <% 
+import com.minres.coredsl.coreDsl.Register
+import com.minres.coredsl.coreDsl.RegisterFile
+import com.minres.coredsl.coreDsl.RegisterAlias
+def getOriginalName(reg){
+    if( reg.original instanceof RegisterFile) {
+    	if( reg.index != null ) {
+        	return reg.original.name+generator.generateHostCode(reg.index)
+        } else {
+        	return reg.original.name
+        }
+    } else if(reg.original instanceof Register){
+        return reg.original.name
+    }
+}
+def getRegisterNames(){
+	def regNames = []
+ 	allRegs.each { reg -> 
+		if( reg instanceof RegisterFile) {
+			(reg.range.right..reg.range.left).each{
+    			regNames+=reg.name.toLowerCase()+it
+            }
+        } else if(reg instanceof Register){
+    		regNames+=reg.name.toLowerCase()
+        }
+    }
+    return regNames
+}
+def getRegisterAliasNames(){
+	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
+ 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
+		if( reg instanceof RegisterFile) {
+			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
+        } else if(reg instanceof Register){
+    		regMap[reg.name]?:reg.name.toLowerCase()
+        }
+ 	}.flatten()
+}
+%>
+#include "util/ities.h"
+#include <util/logging.h>
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <cstdio>
+#include <cstring>
+#include <fstream>
+
+using namespace iss::arch;
+
+constexpr std::array<const char*, ${getRegisterNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
+constexpr std::array<const char*, ${getRegisterAliasNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
+constexpr std::array<const uint32_t, ${regSizes.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
+constexpr std::array<const uint32_t, ${regOffsets.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
+
+${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
+    reg.icount = 0;
+}
+
+${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
+
+void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
+    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
+    reg.PC=address;
+    reg.NEXT_PC=reg.PC;
+    reg.trap_state=0;
+    reg.machine_state=0x3;
+    reg.icount=0;
+}
+
+uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
+	return reinterpret_cast<uint8_t*>(&reg);
+}
+
+${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
+    return phys_addr_t(pc); // change logical address to physical address
+}
+

gen_input/templates/llvm/vm-vm_CORENAME.cpp.gtl

@@ -29,10 +29,11 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
-// clang-format off
+
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <iss/arch/riscv_hart_m_p.h>
 #include <iss/iss.h>
 #include <iss/llvm/vm_base.h>
 #include <util/logging.h>
@@ -58,7 +59,6 @@ using namespace iss::debugger;
 
 template <typename ARCH> class vm_impl : public iss::llvm::vm_base<ARCH> {
 public:
-    using traits = arch::traits<ARCH>;
     using super = typename iss::llvm::vm_base<ARCH>;
     using virt_addr_t = typename super::virt_addr_t;
     using phys_addr_t = typename super::phys_addr_t;
@@ -81,7 +81,7 @@ public:
 protected:
     using vm_base<ARCH>::get_reg_ptr;
 
-    inline const char *name(size_t index){return traits::reg_aliases.at(index);}
+    inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
 
     template <typename T> inline ConstantInt *size(T type) {
         return ConstantInt::get(getContext(), APInt(32, type->getType()->getScalarSizeInBits()));
@@ -89,7 +89,7 @@ protected:
 
     void setup_module(Module* m) override {
         super::setup_module(m);
-        iss::llvm::fp_impl::add_fp_functions_2_module(m, traits::FP_REGS_SIZE, traits::XLEN);
+        iss::llvm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE, traits<ARCH>::XLEN);
     }
 
     inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) {
@@ -111,150 +111,116 @@ protected:
     void gen_trap_check(BasicBlock *bb);
 
     inline Value *gen_reg_load(unsigned i, unsigned level = 0) {
-        return this->builder.CreateLoad(this->get_typeptr(i), get_reg_ptr(i), false);
+        return this->builder.CreateLoad(get_reg_ptr(i), false);
     }
 
     inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
-        Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits::XLEN, pc.val),
+        Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits<ARCH>::XLEN, pc.val),
-                                                           this->get_type(traits::XLEN));
+                                                           this->get_type(traits<ARCH>::XLEN));
         this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
     }
 
     // some compile time constants
+    // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
+    enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
+    enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
+    enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
 
     using this_class = vm_impl<ARCH>;
     using compile_func = std::tuple<continuation_e, BasicBlock *> (this_class::*)(virt_addr_t &pc,
                                                                                   code_word_t instr,
                                                                                   BasicBlock *bb);
-    template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
+    std::array<compile_func, LUT_SIZE> lut;
-    inline S sext(U from) {
+
-        auto mask = (1ULL<<W) - 1;
+    std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
-        auto sign_mask = 1ULL<<(W-1);
+    std::array<compile_func, LUT_SIZE> lut_11;
-        return (from & mask) | ((from & sign_mask) ? ~mask : 0);
+
+	std::array<compile_func *, 4> qlut;
+
+	std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
+
+    void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
+                         compile_func f) {
+        if (pos < 0) {
+            lut[idx] = f;
+        } else {
+            auto bitmask = 1UL << pos;
+            if ((mask & bitmask) == 0) {
+                expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
+            } else {
+                if ((valid & bitmask) == 0) {
+                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
+                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
+                } else {
+                    auto new_val = idx << 1;
+                    if ((value & bitmask) != 0) new_val++;
+                    expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
+                }
+            }
+        }
+    }
+
+    inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
+
+    uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
+        if (pos >= 0) {
+            auto bitmask = 1UL << pos;
+            if ((mask & bitmask) == 0) {
+                lut_val = extract_fields(pos - 1, val, mask, lut_val);
+            } else {
+                auto new_val = lut_val << 1;
+                if ((val & bitmask) != 0) new_val++;
+                lut_val = extract_fields(pos - 1, val, mask, new_val);
+            }
+        }
+        return lut_val;
     }
 
 private:
     /****************************************************************************
      * start opcode definitions
      ****************************************************************************/
-    struct instruction_descriptor {
+    struct InstructionDesriptor {
         size_t length;
         uint32_t value;
         uint32_t mask;
         compile_func op;
     };
-    struct decoding_tree_node{
-        std::vector<instruction_descriptor> instrs;
-        std::vector<decoding_tree_node*> children;
-        uint32_t submask = std::numeric_limits<uint32_t>::max();
-        uint32_t value;
-        decoding_tree_node(uint32_t value) : value(value){}
-    };
 
-    decoding_tree_node* root {nullptr};
+    const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
-
-    const std::array<instruction_descriptor, ${instructions.size}> instr_descr = {{
          /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
-        /* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
+        /* instruction ${instr.instruction.name} */
-        {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
+        {${instr.length}, ${instr.value}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
     }};
  
     /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
     /* instruction ${idx}: ${instr.name} */
-    std::tuple<continuation_e, BasicBlock*> __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+    std::tuple<continuation_e, BasicBlock*> __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){<%instr.code.eachLine{%>
-        bb->setName(fmt::format("${instr.name}_0x{:X}",pc.val));
-        this->gen_sync(PRE_SYNC,${idx});
-        uint64_t PC = pc.val;
-        <%instr.fields.eachLine{%>${it}
-        <%}%>if(this->disass_enabled){
-            /* generate console output when executing the command */<%instr.disass.eachLine{%>
     	${it}<%}%>
     }
-        auto cur_pc_val = this->gen_const(32,pc.val);
-        pc=pc+ ${instr.length/8};
-        this->gen_set_pc(pc, traits::NEXT_PC);
-        <%instr.behavior.eachLine{%>${it}
-        <%}%>
-        this->gen_trap_check(bb);
-    	this->gen_sync(POST_SYNC, ${idx});
-        this->builder.CreateBr(bb);
-    	return returnValue;        
-    }
     <%}%>
     /****************************************************************************
      * end opcode definitions
      ****************************************************************************/
     std::tuple<continuation_e, BasicBlock *> illegal_intruction(virt_addr_t &pc, code_word_t instr, BasicBlock *bb) {
 		this->gen_sync(iss::PRE_SYNC, instr_descr.size());
-        this->builder.CreateStore(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), true),
+        this->builder.CreateStore(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), true),
-                                   get_reg_ptr(traits::PC), true);
+                                   get_reg_ptr(traits<ARCH>::PC), true);
         this->builder.CreateStore(
-            this->builder.CreateAdd(this->builder.CreateLoad(this->get_typeptr(traits::ICOUNT), get_reg_ptr(traits::ICOUNT), true),
+            this->builder.CreateAdd(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::ICOUNT), true),
                                      this->gen_const(64U, 1)),
-            get_reg_ptr(traits::ICOUNT), true);
+            get_reg_ptr(traits<ARCH>::ICOUNT), true);
         pc = pc + ((instr & 3) == 3 ? 4 : 2);
         this->gen_raise_trap(0, 2);     // illegal instruction trap
 		this->gen_sync(iss::POST_SYNC, instr_descr.size());
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(BRANCH, nullptr);
     }
-    //decoding functionality
-
-    void populate_decoding_tree(decoding_tree_node* root){
-        //create submask
-        for(auto instr: root->instrs){
-            root->submask &= instr.mask;
-        }
-        //put each instr according to submask&encoding into children
-        for(auto instr: root->instrs){
-            bool foundMatch = false;
-            for(auto child: root->children){
-                //use value as identifying trait
-                if(child->value == (instr.value&root->submask)){
-                    child->instrs.push_back(instr);
-                    foundMatch = true;
-                }
-            }
-            if(!foundMatch){
-                decoding_tree_node* child = new decoding_tree_node(instr.value&root->submask);
-                child->instrs.push_back(instr);
-                root->children.push_back(child);
-            }
-        }
-        root->instrs.clear();
-        //call populate_decoding_tree for all children
-        if(root->children.size() >1)
-            for(auto child: root->children){
-                populate_decoding_tree(child);      
-            }
-        else{
-            //sort instrs by value of the mask, this works bc we want to have the least restrictive one last
-            std::sort(root->children[0]->instrs.begin(), root->children[0]->instrs.end(), [](const instruction_descriptor& instr1, const instruction_descriptor& instr2) {
-            return instr1.mask > instr2.mask;
-            }); 
-        }
-    }
-    compile_func decode_instr(decoding_tree_node* node, code_word_t word){
-        if(!node->children.size()){
-            if(node->instrs.size() == 1) return node->instrs[0].op;
-            for(auto instr : node->instrs){
-                if((instr.mask&word) == instr.value) return instr.op;
-            }
-        }
-        else{
-            for(auto child : node->children){
-                if (child->value == (node->submask&word)){
-                    return decode_instr(child, word);
-                }  
-            }  
-        }
-        return nullptr;
-    }
 };
 
-template <typename CODE_WORD> void debug_fn(CODE_WORD instr) {
+template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
-    volatile CODE_WORD x = instr;
+    volatile CODE_WORD x = insn;
-    instr = 2 * x;
+    insn = 2 * x;
 }
 
 template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
@@ -262,11 +228,14 @@ template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
 template <typename ARCH>
 vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
 : vm_base<ARCH>(core, core_id, cluster_id) {
-    root = new decoding_tree_node(std::numeric_limits<uint32_t>::max());
+    qlut[0] = lut_00.data();
+    qlut[1] = lut_01.data();
+    qlut[2] = lut_10.data();
+    qlut[3] = lut_11.data();
     for (auto instr : instr_descr) {
-        root->instrs.push_back(instr);
+        auto quantrant = instr.value & 0x3;
+        expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
     }
-    populate_decoding_tree(root);
 }
 
 template <typename ARCH>
@@ -274,50 +243,49 @@ std::tuple<continuation_e, BasicBlock *>
 vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, BasicBlock *this_block) {
     // we fetch at max 4 byte, alignment is 2
     enum {TRAP_ID=1<<16};
-    code_word_t instr = 0;
+    code_word_t insn = 0;
-    // const typename traits::addr_t upper_bits = ~traits::PGMASK;
+    const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
     phys_addr_t paddr(pc);
-    auto *const data = (uint8_t *)&instr;
+    auto *const data = (uint8_t *)&insn;
-    if(this->core.has_mmu())
+    paddr = this->core.v2p(pc);
-        paddr = this->core.virt2phys(pc);
+    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
-    //TODO: re-add page handling
+        auto res = this->core.read(paddr, 2, data);
-//    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
+        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-//        auto res = this->core.read(paddr, 2, data);
+        if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
-//        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
-//        if ((instr & 0x3) == 0x3) { // this is a 32bit instruction
+        }
-//            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
+    } else {
-//        }
-//    } else {
         auto res = this->core.read(paddr, 4, data);
         if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-//    }
+    }
-    if (instr == 0x0000006f || (instr&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+    if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
     // curr pc on stack
     ++inst_cnt;
-    auto f = decode_instr(root, instr);
+    auto lut_val = extract_fields(insn);
+    auto f = qlut[insn & 0x3][lut_val];
     if (f == nullptr) {
         f = &this_class::illegal_intruction;
     }
-    return (this->*f)(pc, instr, this_block);
+    return (this->*f)(pc, insn, this_block);
 }
 
 template <typename ARCH> void vm_impl<ARCH>::gen_leave_behavior(BasicBlock *leave_blk) {
     this->builder.SetInsertPoint(leave_blk);
-    this->builder.CreateRet(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC),get_reg_ptr(traits::NEXT_PC), false));
+    this->builder.CreateRet(this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::NEXT_PC), false));
 }
 
 template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
     auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
-    this->builder.CreateStore(TRAP_val, get_reg_ptr(traits::TRAP_STATE), true);
+    this->builder.CreateStore(TRAP_val, get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
-    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits::LAST_BRANCH), false);
+    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
 }
 
 template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
     std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)) };
     this->builder.CreateCall(this->mod->getFunction("leave_trap"), args);
-    auto *PC_val = this->gen_read_mem(traits::CSR, (lvl << 8) + 0x41, traits::XLEN / 8);
+    auto *PC_val = this->gen_read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN / 8);
-    this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false);
+    this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
-    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits::LAST_BRANCH), false);
+    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
 }
 
 template <typename ARCH> void vm_impl<ARCH>::gen_wait(unsigned type) {
@@ -327,25 +295,22 @@ template <typename ARCH> void vm_impl<ARCH>::gen_wait(unsigned type) {
 
 template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(BasicBlock *trap_blk) {
     this->builder.SetInsertPoint(trap_blk);
-    this->gen_sync(POST_SYNC, -1); //TODO get right InstrId
+    auto *trap_state_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
-    auto *trap_state_val = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true);
     this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
-                              get_reg_ptr(traits::LAST_BRANCH), false);
+                              get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
     std::vector<Value *> args{this->core_ptr, this->adj_to64(trap_state_val),
-                              this->adj_to64(this->builder.CreateLoad(this->get_typeptr(traits::PC), get_reg_ptr(traits::PC), false))};
+                              this->adj_to64(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::PC), false))};
     this->builder.CreateCall(this->mod->getFunction("enter_trap"), args);
-    auto *trap_addr_val = this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), false);
+    auto *trap_addr_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), false);
     this->builder.CreateRet(trap_addr_val);
 }
 
 template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(BasicBlock *bb) {
-    auto* target_bb = BasicBlock::Create(this->mod->getContext(), "", this->func, bb);
+    auto *v = this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), true);
-    auto *v = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true);
     this->gen_cond_branch(this->builder.CreateICmp(
                               ICmpInst::ICMP_EQ, v,
                               ConstantInt::get(getContext(), APInt(v->getType()->getIntegerBitWidth(), 0))),
-                          target_bb, this->trap_blk, 1);
+                          bb, this->trap_blk, 1);
-    this->builder.SetInsertPoint(target_bb);
 }
 
 } // namespace ${coreDef.name.toLowerCase()}
@@ -358,26 +323,3 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
 }
 } // namespace llvm
 } // namespace iss
-
-#include <iss/factory.h>
-#include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_mu_p.h>
-namespace iss {
-namespace {
-volatile std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|llvm", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
-            auto* vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
-            if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            return {cpu_ptr{cpu}, vm_ptr{vm}};
-        }),
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|llvm", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
-            auto* vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
-            if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            return {cpu_ptr{cpu}, vm_ptr{vm}};
-        })
-};
-}
-}
-// clang-format on

gen_input/templates/tcc/CORENAME.cpp.gtl

@@ -29,7 +29,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
-// clang-format off
+
 #include <iss/arch/${coreDef.name.toLowerCase()}.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
@@ -120,7 +120,57 @@ protected:
         }
     }
 
+    // some compile time constants
+    // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
+    enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
+    enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
+    enum { LUT_SIZE = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK32)), LUT_SIZE_C = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK16)) };
 
+    std::array<compile_func, LUT_SIZE> lut;
+
+    std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
+    std::array<compile_func, LUT_SIZE> lut_11;
+
+    std::array<compile_func *, 4> qlut;
+
+    std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
+
+    void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
+                         compile_func f) {
+        if (pos < 0) {
+            lut[idx] = f;
+        } else {
+            auto bitmask = 1UL << pos;
+            if ((mask & bitmask) == 0) {
+                expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
+            } else {
+                if ((valid & bitmask) == 0) {
+                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
+                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
+                } else {
+                    auto new_val = idx << 1;
+                    if ((value & bitmask) != 0) new_val++;
+                    expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
+                }
+            }
+        }
+    }
+
+    inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
+
+    uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
+        if (pos >= 0) {
+            auto bitmask = 1UL << pos;
+            if ((mask & bitmask) == 0) {
+                lut_val = extract_fields(pos - 1, val, mask, lut_val);
+            } else {
+                auto new_val = lut_val << 1;
+                if ((val & bitmask) != 0) new_val++;
+                lut_val = extract_fields(pos - 1, val, mask, new_val);
+            }
+        }
+        return lut_val;
+    }
     template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
     inline S sext(U from) {
         auto mask = (1ULL<<W) - 1;
@@ -132,23 +182,14 @@ private:
     /****************************************************************************
      * start opcode definitions
      ****************************************************************************/
-    struct instruction_descriptor {
+    struct InstructionDesriptor {
         size_t length;
         uint32_t value;
         uint32_t mask;
         compile_func op;
     };
-    struct decoding_tree_node{
-        std::vector<instruction_descriptor> instrs;
-        std::vector<decoding_tree_node*> children;
-        uint32_t submask = std::numeric_limits<uint32_t>::max();
-        uint32_t value;
-        decoding_tree_node(uint32_t value) : value(value){}
-    };
 
-    decoding_tree_node* root {nullptr};
+    const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
-
-    const std::array<instruction_descriptor, ${instructions.size}> instr_descr = {{
          /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
         /* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
         {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
@@ -159,7 +200,6 @@ private:
     compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("${instr.name}_{:#010x}:", pc.val);
         vm_base<ARCH>::gen_sync(tu, PRE_SYNC,${idx});
-        uint64_t PC = pc.val;
         <%instr.fields.eachLine{%>${it}
         <%}%>if(this->disass_enabled){
             /* generate console output when executing the command */<%instr.disass.eachLine{%>
@@ -168,12 +208,11 @@ private:
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
         pc=pc+ ${instr.length/8};
         gen_set_pc(tu, pc, traits::NEXT_PC);
-        tu.open_scope();
+        tu.open_scope();<%instr.behavior.eachLine{%>
-        <%instr.behavior.eachLine{%>${it}
+        ${it}<%}%>
-        <%}%>
         tu.close_scope();
-        gen_trap_check(tu);        
         vm_base<ARCH>::gen_sync(tu, POST_SYNC,${idx});
+        gen_trap_check(tu);
         return returnValue;
     }
     <%}%>
@@ -188,64 +227,11 @@ private:
         vm_impl::gen_trap_check(tu);
         return BRANCH;
     }
-    
-    //decoding functionality
-
-    void populate_decoding_tree(decoding_tree_node* root){
-        //create submask
-        for(auto instr: root->instrs){
-            root->submask &= instr.mask;
-        }
-        //put each instr according to submask&encoding into children
-        for(auto instr: root->instrs){
-            bool foundMatch = false;
-            for(auto child: root->children){
-                //use value as identifying trait
-                if(child->value == (instr.value&root->submask)){
-                    child->instrs.push_back(instr);
-                    foundMatch = true;
-                }
-            }
-            if(!foundMatch){
-                decoding_tree_node* child = new decoding_tree_node(instr.value&root->submask);
-                child->instrs.push_back(instr);
-                root->children.push_back(child);
-            }
-        }
-        root->instrs.clear();
-        //call populate_decoding_tree for all children
-        if(root->children.size() >1)
-            for(auto child: root->children){
-                populate_decoding_tree(child);      
-            }
-        else{
-            //sort instrs by value of the mask, this works bc we want to have the least restrictive one last
-            std::sort(root->children[0]->instrs.begin(), root->children[0]->instrs.end(), [](const instruction_descriptor& instr1, const instruction_descriptor& instr2) {
-            return instr1.mask > instr2.mask;
-            }); 
-        }
-    }
-    compile_func decode_instr(decoding_tree_node* node, code_word_t word){
-        if(!node->children.size()){
-            if(node->instrs.size() == 1) return node->instrs[0].op;
-            for(auto instr : node->instrs){
-                if((instr.mask&word) == instr.value) return instr.op;
-            }
-        }
-        else{
-            for(auto child : node->children){
-                if (child->value == (node->submask&word)){
-                    return decode_instr(child, word);
-                }  
-            }  
-        }
-        return nullptr;
-    }
 };
 
-template <typename CODE_WORD> void debug_fn(CODE_WORD instr) {
+template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
-    volatile CODE_WORD x = instr;
+    volatile CODE_WORD x = insn;
-    instr = 2 * x;
+    insn = 2 * x;
 }
 
 template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
@@ -253,11 +239,14 @@ template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
 template <typename ARCH>
 vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
 : vm_base<ARCH>(core, core_id, cluster_id) {
-    root = new decoding_tree_node(std::numeric_limits<uint32_t>::max());
+    qlut[0] = lut_00.data();
+    qlut[1] = lut_01.data();
+    qlut[2] = lut_10.data();
+    qlut[3] = lut_11.data();
     for (auto instr : instr_descr) {
-        root->instrs.push_back(instr);
+        auto quantrant = instr.value & 0x3;
+        expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
     }
-    populate_decoding_tree(root);
 }
 
 template <typename ARCH>
@@ -265,11 +254,11 @@ std::tuple<continuation_e>
 vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, tu_builder& tu) {
     // we fetch at max 4 byte, alignment is 2
     enum {TRAP_ID=1<<16};
-    code_word_t instr = 0;
+    code_word_t insn = 0;
+    // const typename traits::addr_t upper_bits = ~traits::PGMASK;
     phys_addr_t paddr(pc);
-    if(this->core.has_mmu())
+    auto *const data = (uint8_t *)&insn;
-        paddr = this->core.virt2phys(pc);
+    paddr = this->core.v2p(pc);
-    //TODO: re-add page handling
 //    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
 //        auto res = this->core.read(paddr, 2, data);
 //        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
@@ -277,17 +266,18 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
 //            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
 //        }
 //    } else {
-        auto res = this->core.read(paddr, 4, reinterpret_cast<uint8_t*>(&instr));
+        auto res = this->core.read(paddr, 4, data);
         if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
 //    }
-    if (instr == 0x0000006f || (instr&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+    if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
     // curr pc on stack
     ++inst_cnt;
-    auto f = decode_instr(root, instr);
+    auto lut_val = extract_fields(insn);
+    auto f = qlut[insn & 0x3][lut_val];
     if (f == nullptr) {
         f = &this_class::illegal_intruction;
     }
-    return (this->*f)(pc, instr, tu);
+    return (this->*f)(pc, insn, tu);
 }
 
 template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) {
@@ -306,13 +296,12 @@ template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned t
 
 template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
     tu("trap_entry:");
-    this->gen_sync(tu, POST_SYNC, -1);    
     tu("enter_trap(core_ptr, *trap_state, *pc, 0);");
     tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits<uint32_t>::max(),32));
     tu("return *next_pc;");
 }
 
-} // namespace ${coreDef.name.toLowerCase()}
+} // namespace mnrv32
 
 template <>
 std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
@@ -328,7 +317,7 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
 #include <iss/arch/riscv_hart_mu_p.h>
 namespace iss {
 namespace {
-volatile std::array<bool, 2> dummy = {
+std::array<bool, 2> dummy = {
         core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
             auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
 		    auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
@@ -344,4 +333,8 @@ volatile std::array<bool, 2> dummy = {
 };
 }
 }
-// clang-format on
+extern "C" {
+	bool* get_${coreDef.name.toLowerCase()}_tcc_creators() {
+		return iss::dummy.data();
+	}
+}

softfloat/build/Linux-386-GCC/platform.h

@@ -50,3 +50,4 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *----------------------------------------------------------------------------*/
 #define SOFTFLOAT_BUILTIN_CLZ 1
 #include "opts-GCC.h"
+

softfloat/build/Linux-386-SSE2-GCC/platform.h

@@ -50,3 +50,4 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *----------------------------------------------------------------------------*/
 #define SOFTFLOAT_BUILTIN_CLZ 1
 #include "opts-GCC.h"
+

softfloat/build/Linux-ARM-VFPv2-GCC/platform.h

@@ -50,3 +50,4 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *----------------------------------------------------------------------------*/
 #define SOFTFLOAT_BUILTIN_CLZ 1
 #include "opts-GCC.h"
+

softfloat/build/Linux-x86_64-GCC/platform.h

@@ -54,3 +54,4 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #define SOFTFLOAT_INTRINSIC_INT128 1
 #endif
 #include "opts-GCC.h"
+

softfloat/build/Win32-MinGW/platform.h

@@ -50,3 +50,4 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *----------------------------------------------------------------------------*/
 #define SOFTFLOAT_BUILTIN_CLZ 1
 #include "opts-GCC.h"
+

softfloat/build/Win32-SSE2-MinGW/platform.h

@@ -50,3 +50,4 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *----------------------------------------------------------------------------*/
 #define SOFTFLOAT_BUILTIN_CLZ 1
 #include "opts-GCC.h"
+

softfloat/build/Win64-MinGW-w64/platform.h

@@ -51,3 +51,4 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #define SOFTFLOAT_BUILTIN_CLZ 1
 #define SOFTFLOAT_INTRINSIC_INT128 1
 #include "opts-GCC.h"
+

softfloat/build/template-FAST_INT64/platform.h

@@ -47,3 +47,4 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 /*----------------------------------------------------------------------------
 *----------------------------------------------------------------------------*/
 ==> #define THREAD_LOCAL _Thread_local
+

softfloat/build/template-not-FAST_INT64/platform.h

@@ -47,3 +47,4 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 /*----------------------------------------------------------------------------
 *----------------------------------------------------------------------------*/
 ==> #define THREAD_LOCAL _Thread_local
+

softfloat/source/8086-SSE/specialize.h

@@ -37,10 +37,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifndef specialize_h
 #define specialize_h 1
 
-#include "primitiveTypes.h"
-#include "softfloat.h"
 #include <stdbool.h>
 #include <stdint.h>
+#include "primitiveTypes.h"
+#include "softfloat.h"
 
 /*----------------------------------------------------------------------------
 | Default value for 'softfloat_detectTininess'.
@@ -114,7 +114,8 @@ uint_fast16_t softfloat_commonNaNToF16UI(const struct commonNaN* aPtr);
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB);
+uint_fast16_t
+ softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 32-bit floating-point NaN.
@@ -148,7 +149,8 @@ uint_fast32_t softfloat_commonNaNToF32UI(const struct commonNaN* aPtr);
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
+uint_fast32_t
+ softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 64-bit floating-point NaN.
@@ -160,8 +162,7 @@ uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
 | 64-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF64UI(uiA)                                                                                                       \
+#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF )))
-    ((((uiA)&UINT64_C(0x7FF8000000000000)) == UINT64_C(0x7FF0000000000000)) && ((uiA)&UINT64_C(0x0007FFFFFFFFFFFF)))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts
@@ -183,7 +184,8 @@ uint_fast64_t softfloat_commonNaNToF64UI(const struct commonNaN* aPtr);
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
+uint_fast64_t
+ softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 80-bit extended floating-point NaN.
@@ -197,8 +199,7 @@ uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
 | floating-point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNExtF80UI(uiA64, uiA0)                                                                                            \
+#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF )))
-    ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF)))
 
 #ifdef SOFTFLOAT_FAST_INT64
 
@@ -214,7 +215,9 @@ uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_extF80UIToCommonNaN(uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
+void
+ softfloat_extF80UIToCommonNaN(
+     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
@@ -232,7 +235,13 @@ struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr);
 | result.  If either original floating-point value is a signaling NaN, the
 | invalid exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0);
+struct uint128
+ softfloat_propagateNaNExtF80UI(
+     uint_fast16_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast16_t uiB64,
+     uint_fast64_t uiB0
+ );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -246,8 +255,7 @@ struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t
 | point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF128UI(uiA64, uiA0)                                                                                              \
+#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF ))))
-    ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF))))
 
 /*----------------------------------------------------------------------------
 | Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
@@ -256,7 +264,9 @@ struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t
 | pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid exception
 | is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_f128UIToCommonNaN(uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
+void
+ softfloat_f128UIToCommonNaN(
+     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -273,7 +283,13 @@ struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN*);
 | If either original floating-point value is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0);
+struct uint128
+ softfloat_propagateNaNF128UI(
+     uint_fast64_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast64_t uiB64,
+     uint_fast64_t uiB0
+ );
 
 #else
 
@@ -288,14 +304,18 @@ struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t u
 | common NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling
 | NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_extF80MToCommonNaN(const struct extFloat80M* aSPtr, struct commonNaN* zPtr);
+void
+ softfloat_extF80MToCommonNaN(
+     const struct extFloat80M *aSPtr, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
 | floating-point NaN, and stores this NaN at the location pointed to by
 | 'zSPtr'.
 *----------------------------------------------------------------------------*/
-void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr);
+void
+ softfloat_commonNaNToExtF80M(
+     const struct commonNaN *aPtr, struct extFloat80M *zSPtr );
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 80-bit extended floating-point values
@@ -303,7 +323,12 @@ void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat8
 | at the location pointed to by 'zSPtr'.  If either original floating-point
 | value is a signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr);
+void
+ softfloat_propagateNaNExtF80M(
+     const struct extFloat80M *aSPtr,
+     const struct extFloat80M *bSPtr,
+     struct extFloat80M *zSPtr
+ );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -321,7 +346,8 @@ void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct
 | four 32-bit elements that concatenate in the platform's normal endian order
 | to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void softfloat_f128MToCommonNaN(const uint32_t* aWPtr, struct commonNaN* zPtr);
+void
+ softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -329,7 +355,8 @@ void softfloat_f128MToCommonNaN(const uint32_t* aWPtr, struct commonNaN* zPtr);
 | 'zWPtr' points to an array of four 32-bit elements that concatenate in the
 | platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
+void
+ softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr );
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 128-bit floating-point values pointed to by
@@ -339,8 +366,11 @@ void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
 | and 'zWPtr' points to an array of four 32-bit elements that concatenate in
 | the platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr);
+void
+ softfloat_propagateNaNF128M(
+     const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr );
 
 #endif
 
 #endif
+

softfloat/source/8086/specialize.h

@@ -37,10 +37,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifndef specialize_h
 #define specialize_h 1
 
-#include "primitiveTypes.h"
-#include "softfloat.h"
 #include <stdbool.h>
 #include <stdint.h>
+#include "primitiveTypes.h"
+#include "softfloat.h"
 
 /*----------------------------------------------------------------------------
 | Default value for 'softfloat_detectTininess'.
@@ -114,7 +114,8 @@ uint_fast16_t softfloat_commonNaNToF16UI(const struct commonNaN* aPtr);
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB);
+uint_fast16_t
+ softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 32-bit floating-point NaN.
@@ -148,7 +149,8 @@ uint_fast32_t softfloat_commonNaNToF32UI(const struct commonNaN* aPtr);
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
+uint_fast32_t
+ softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 64-bit floating-point NaN.
@@ -160,8 +162,7 @@ uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
 | 64-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF64UI(uiA)                                                                                                       \
+#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF )))
-    ((((uiA)&UINT64_C(0x7FF8000000000000)) == UINT64_C(0x7FF0000000000000)) && ((uiA)&UINT64_C(0x0007FFFFFFFFFFFF)))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts
@@ -183,7 +184,8 @@ uint_fast64_t softfloat_commonNaNToF64UI(const struct commonNaN* aPtr);
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
+uint_fast64_t
+ softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 80-bit extended floating-point NaN.
@@ -197,8 +199,7 @@ uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
 | floating-point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNExtF80UI(uiA64, uiA0)                                                                                            \
+#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF )))
-    ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF)))
 
 #ifdef SOFTFLOAT_FAST_INT64
 
@@ -214,7 +215,9 @@ uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_extF80UIToCommonNaN(uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
+void
+ softfloat_extF80UIToCommonNaN(
+     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
@@ -232,7 +235,13 @@ struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr);
 | result.  If either original floating-point value is a signaling NaN, the
 | invalid exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0);
+struct uint128
+ softfloat_propagateNaNExtF80UI(
+     uint_fast16_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast16_t uiB64,
+     uint_fast64_t uiB0
+ );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -246,8 +255,7 @@ struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t
 | point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF128UI(uiA64, uiA0)                                                                                              \
+#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF ))))
-    ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF))))
 
 /*----------------------------------------------------------------------------
 | Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
@@ -256,7 +264,9 @@ struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t
 | pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid exception
 | is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_f128UIToCommonNaN(uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
+void
+ softfloat_f128UIToCommonNaN(
+     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -273,7 +283,13 @@ struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN*);
 | If either original floating-point value is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0);
+struct uint128
+ softfloat_propagateNaNF128UI(
+     uint_fast64_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast64_t uiB64,
+     uint_fast64_t uiB0
+ );
 
 #else
 
@@ -288,14 +304,18 @@ struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t u
 | common NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling
 | NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_extF80MToCommonNaN(const struct extFloat80M* aSPtr, struct commonNaN* zPtr);
+void
+ softfloat_extF80MToCommonNaN(
+     const struct extFloat80M *aSPtr, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
 | floating-point NaN, and stores this NaN at the location pointed to by
 | 'zSPtr'.
 *----------------------------------------------------------------------------*/
-void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr);
+void
+ softfloat_commonNaNToExtF80M(
+     const struct commonNaN *aPtr, struct extFloat80M *zSPtr );
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 80-bit extended floating-point values
@@ -303,7 +323,12 @@ void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat8
 | at the location pointed to by 'zSPtr'.  If either original floating-point
 | value is a signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr);
+void
+ softfloat_propagateNaNExtF80M(
+     const struct extFloat80M *aSPtr,
+     const struct extFloat80M *bSPtr,
+     struct extFloat80M *zSPtr
+ );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -321,7 +346,8 @@ void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct
 | four 32-bit elements that concatenate in the platform's normal endian order
 | to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void softfloat_f128MToCommonNaN(const uint32_t* aWPtr, struct commonNaN* zPtr);
+void
+ softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -329,7 +355,8 @@ void softfloat_f128MToCommonNaN(const uint32_t* aWPtr, struct commonNaN* zPtr);
 | 'zWPtr' points to an array of four 32-bit elements that concatenate in the
 | platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
+void
+ softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr );
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 128-bit floating-point values pointed to by
@@ -339,8 +366,11 @@ void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
 | and 'zWPtr' points to an array of four 32-bit elements that concatenate in
 | the platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr);
+void
+ softfloat_propagateNaNF128M(
+     const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr );
 
 #endif
 
 #endif
+

softfloat/source/ARM-VFPv2-defaultNaN/specialize.h

@@ -37,10 +37,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifndef specialize_h
 #define specialize_h 1
 
-#include "primitiveTypes.h"
-#include "softfloat.h"
 #include <stdbool.h>
 #include <stdint.h>
+#include "primitiveTypes.h"
+#include "softfloat.h"
 
 /*----------------------------------------------------------------------------
 | Default value for 'softfloat_detectTininess'.
@@ -73,9 +73,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | "Common NaN" structure, used to transfer NaN representations from one format
 | to another.
 *----------------------------------------------------------------------------*/
-struct commonNaN {
+struct commonNaN { char _unused; };
-    char _unused;
-};
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 16-bit floating-point NaN.
@@ -95,9 +93,7 @@ struct commonNaN {
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_f16UIToCommonNaN(uiA, zPtr)                                                                                              \
+#define softfloat_f16UIToCommonNaN( uiA, zPtr ) if ( ! ((uiA) & 0x0200) ) softfloat_raiseFlags( softfloat_flag_invalid )
-    if(!((uiA)&0x0200))                                                                                                                    \
-    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point
@@ -111,7 +107,8 @@ struct commonNaN {
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB);
+uint_fast16_t
+ softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 32-bit floating-point NaN.
@@ -131,9 +128,7 @@ uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB);
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_f32UIToCommonNaN(uiA, zPtr)                                                                                              \
+#define softfloat_f32UIToCommonNaN( uiA, zPtr ) if ( ! ((uiA) & 0x00400000) ) softfloat_raiseFlags( softfloat_flag_invalid )
-    if(!((uiA)&0x00400000))                                                                                                                \
-    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point
@@ -147,7 +142,8 @@ uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB);
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
+uint_fast32_t
+ softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 64-bit floating-point NaN.
@@ -159,8 +155,7 @@ uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
 | 64-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF64UI(uiA)                                                                                                       \
+#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF )))
-    ((((uiA)&UINT64_C(0x7FF8000000000000)) == UINT64_C(0x7FF0000000000000)) && ((uiA)&UINT64_C(0x0007FFFFFFFFFFFF)))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts
@@ -168,9 +163,7 @@ uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_f64UIToCommonNaN(uiA, zPtr)                                                                                              \
+#define softfloat_f64UIToCommonNaN( uiA, zPtr ) if ( ! ((uiA) & UINT64_C( 0x0008000000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
-    if(!((uiA)&UINT64_C(0x0008000000000000)))                                                                                              \
-    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point
@@ -184,7 +177,8 @@ uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
+uint_fast64_t
+ softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 80-bit extended floating-point NaN.
@@ -198,8 +192,7 @@ uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
 | floating-point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNExtF80UI(uiA64, uiA0)                                                                                            \
+#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF )))
-    ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF)))
 
 #ifdef SOFTFLOAT_FAST_INT64
 
@@ -215,9 +208,7 @@ uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_extF80UIToCommonNaN(uiA64, uiA0, zPtr)                                                                                   \
+#define softfloat_extF80UIToCommonNaN( uiA64, uiA0, zPtr ) if ( ! ((uiA0) & UINT64_C( 0x4000000000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
-    if(!((uiA0)&UINT64_C(0x4000000000000000)))                                                                                             \
-    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
@@ -226,7 +217,8 @@ uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
 *----------------------------------------------------------------------------*/
 #if defined INLINE && ! defined softfloat_commonNaNToExtF80UI
 INLINE
-struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr) {
+struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr )
+{
     struct uint128 uiZ;
     uiZ.v64 = defaultNaNExtF80UI64;
     uiZ.v0  = defaultNaNExtF80UI0;
@@ -245,7 +237,13 @@ struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr);
 | result.  If either original floating-point value is a signaling NaN, the
 | invalid exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0);
+struct uint128
+ softfloat_propagateNaNExtF80UI(
+     uint_fast16_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast16_t uiB64,
+     uint_fast64_t uiB0
+ );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -259,8 +257,7 @@ struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t
 | point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF128UI(uiA64, uiA0)                                                                                              \
+#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF ))))
-    ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF))))
 
 /*----------------------------------------------------------------------------
 | Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
@@ -269,9 +266,7 @@ struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t
 | pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid exception
 | is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_f128UIToCommonNaN(uiA64, uiA0, zPtr)                                                                                     \
+#define softfloat_f128UIToCommonNaN( uiA64, uiA0, zPtr ) if ( ! ((uiA64) & UINT64_C( 0x0000800000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
-    if(!((uiA64)&UINT64_C(0x0000800000000000)))                                                                                            \
-    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -279,7 +274,8 @@ struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t
 *----------------------------------------------------------------------------*/
 #if defined INLINE && ! defined softfloat_commonNaNToF128UI
 INLINE
-struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN* aPtr) {
+struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN *aPtr )
+{
     struct uint128 uiZ;
     uiZ.v64 = defaultNaNF128UI64;
     uiZ.v0  = defaultNaNF128UI0;
@@ -298,7 +294,13 @@ struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN*);
 | If either original floating-point value is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0);
+struct uint128
+ softfloat_propagateNaNF128UI(
+     uint_fast64_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast64_t uiB64,
+     uint_fast64_t uiB0
+ );
 
 #else
 
@@ -313,9 +315,7 @@ struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t u
 | common NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling
 | NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_extF80MToCommonNaN(aSPtr, zPtr)                                                                                          \
+#define softfloat_extF80MToCommonNaN( aSPtr, zPtr ) if ( ! ((aSPtr)->signif & UINT64_C( 0x4000000000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
-    if(!((aSPtr)->signif & UINT64_C(0x4000000000000000)))                                                                                  \
-    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
@@ -324,12 +324,17 @@ struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t u
 *----------------------------------------------------------------------------*/
 #if defined INLINE && ! defined softfloat_commonNaNToExtF80M
 INLINE
-void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr) {
+void
+ softfloat_commonNaNToExtF80M(
+     const struct commonNaN *aPtr, struct extFloat80M *zSPtr )
+{
     zSPtr->signExp = defaultNaNExtF80UI64;
     zSPtr->signif  = defaultNaNExtF80UI0;
 }
 #else
-void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr);
+void
+ softfloat_commonNaNToExtF80M(
+     const struct commonNaN *aPtr, struct extFloat80M *zSPtr );
 #endif
 
 /*----------------------------------------------------------------------------
@@ -338,7 +343,12 @@ void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat8
 | at the location pointed to by 'zSPtr'.  If either original floating-point
 | value is a signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr);
+void
+ softfloat_propagateNaNExtF80M(
+     const struct extFloat80M *aSPtr,
+     const struct extFloat80M *bSPtr,
+     struct extFloat80M *zSPtr
+ );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -356,9 +366,7 @@ void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct
 | four 32-bit elements that concatenate in the platform's normal endian order
 | to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-#define softfloat_f128MToCommonNaN(aWPtr, zPtr)                                                                                            \
+#define softfloat_f128MToCommonNaN( aWPtr, zPtr ) if ( ! ((aWPtr)[indexWordHi( 4 )] & UINT64_C( 0x0000800000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
-    if(!((aWPtr)[indexWordHi(4)] & UINT64_C(0x0000800000000000)))                                                                          \
-    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -368,14 +376,17 @@ void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct
 *----------------------------------------------------------------------------*/
 #if defined INLINE && ! defined softfloat_commonNaNToF128M
 INLINE
-void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr) {
+void
+ softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr )
+{
     zWPtr[indexWord( 4, 3 )] = defaultNaNF128UI96;
     zWPtr[indexWord( 4, 2 )] = defaultNaNF128UI64;
     zWPtr[indexWord( 4, 1 )] = defaultNaNF128UI32;
     zWPtr[indexWord( 4, 0 )] = defaultNaNF128UI0;
 }
 #else
-void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
+void
+ softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr );
 #endif
 
 /*----------------------------------------------------------------------------
@@ -386,8 +397,11 @@ void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
 | and 'zWPtr' points to an array of four 32-bit elements that concatenate in
 | the platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr);
+void
+ softfloat_propagateNaNF128M(
+     const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr );
 
 #endif
 
 #endif
+

softfloat/source/ARM-VFPv2/specialize.h

@@ -37,10 +37,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifndef specialize_h
 #define specialize_h 1
 
-#include "primitiveTypes.h"
-#include "softfloat.h"
 #include <stdbool.h>
 #include <stdint.h>
+#include "primitiveTypes.h"
+#include "softfloat.h"
 
 /*----------------------------------------------------------------------------
 | Default value for 'softfloat_detectTininess'.
@@ -114,7 +114,8 @@ uint_fast16_t softfloat_commonNaNToF16UI(const struct commonNaN* aPtr);
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB);
+uint_fast16_t
+ softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 32-bit floating-point NaN.
@@ -148,7 +149,8 @@ uint_fast32_t softfloat_commonNaNToF32UI(const struct commonNaN* aPtr);
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
+uint_fast32_t
+ softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 64-bit floating-point NaN.
@@ -160,8 +162,7 @@ uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
 | 64-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF64UI(uiA)                                                                                                       \
+#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF )))
-    ((((uiA)&UINT64_C(0x7FF8000000000000)) == UINT64_C(0x7FF0000000000000)) && ((uiA)&UINT64_C(0x0007FFFFFFFFFFFF)))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts
@@ -183,7 +184,8 @@ uint_fast64_t softfloat_commonNaNToF64UI(const struct commonNaN* aPtr);
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
+uint_fast64_t
+ softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 80-bit extended floating-point NaN.
@@ -197,8 +199,7 @@ uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
 | floating-point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNExtF80UI(uiA64, uiA0)                                                                                            \
+#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF )))
-    ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF)))
 
 #ifdef SOFTFLOAT_FAST_INT64
 
@@ -214,7 +215,9 @@ uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_extF80UIToCommonNaN(uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
+void
+ softfloat_extF80UIToCommonNaN(
+     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
@@ -232,7 +235,13 @@ struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr);
 | result.  If either original floating-point value is a signaling NaN, the
 | invalid exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0);
+struct uint128
+ softfloat_propagateNaNExtF80UI(
+     uint_fast16_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast16_t uiB64,
+     uint_fast64_t uiB0
+ );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -246,8 +255,7 @@ struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t
 | point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF128UI(uiA64, uiA0)                                                                                              \
+#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF ))))
-    ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF))))
 
 /*----------------------------------------------------------------------------
 | Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
@@ -256,7 +264,9 @@ struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t
 | pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid exception
 | is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_f128UIToCommonNaN(uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
+void
+ softfloat_f128UIToCommonNaN(
+     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -273,7 +283,13 @@ struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN*);
 | If either original floating-point value is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0);
+struct uint128
+ softfloat_propagateNaNF128UI(
+     uint_fast64_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast64_t uiB64,
+     uint_fast64_t uiB0
+ );
 
 #else
 
@@ -288,14 +304,18 @@ struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t u
 | common NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling
 | NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_extF80MToCommonNaN(const struct extFloat80M* aSPtr, struct commonNaN* zPtr);
+void
+ softfloat_extF80MToCommonNaN(
+     const struct extFloat80M *aSPtr, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
 | floating-point NaN, and stores this NaN at the location pointed to by
 | 'zSPtr'.
 *----------------------------------------------------------------------------*/
-void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr);
+void
+ softfloat_commonNaNToExtF80M(
+     const struct commonNaN *aPtr, struct extFloat80M *zSPtr );
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 80-bit extended floating-point values
@@ -303,7 +323,12 @@ void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat8
 | at the location pointed to by 'zSPtr'.  If either original floating-point
 | value is a signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr);
+void
+ softfloat_propagateNaNExtF80M(
+     const struct extFloat80M *aSPtr,
+     const struct extFloat80M *bSPtr,
+     struct extFloat80M *zSPtr
+ );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -321,7 +346,8 @@ void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct
 | four 32-bit elements that concatenate in the platform's normal endian order
 | to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void softfloat_f128MToCommonNaN(const uint32_t* aWPtr, struct commonNaN* zPtr);
+void
+ softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -329,7 +355,8 @@ void softfloat_f128MToCommonNaN(const uint32_t* aWPtr, struct commonNaN* zPtr);
 | 'zWPtr' points to an array of four 32-bit elements that concatenate in the
 | platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
+void
+ softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr );
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 128-bit floating-point values pointed to by
@@ -339,8 +366,11 @@ void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
 | and 'zWPtr' points to an array of four 32-bit elements that concatenate in
 | the platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr);
+void
+ softfloat_propagateNaNF128M(
+     const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr );
 
 #endif
 
 #endif
+

softfloat/source/RISCV/specialize.h

@@ -37,10 +37,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifndef specialize_h
 #define specialize_h 1
 
-#include "primitiveTypes.h"
-#include "softfloat.h"
 #include <stdbool.h>
 #include <stdint.h>
+#include "primitiveTypes.h"
+#include "softfloat.h"
 
 /*----------------------------------------------------------------------------
 | Default value for 'softfloat_detectTininess'.
@@ -114,7 +114,8 @@ uint_fast16_t softfloat_commonNaNToF16UI(const struct commonNaN* aPtr);
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB);
+uint_fast16_t
+ softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 32-bit floating-point NaN.
@@ -148,7 +149,8 @@ uint_fast32_t softfloat_commonNaNToF32UI(const struct commonNaN* aPtr);
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
+uint_fast32_t
+ softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 64-bit floating-point NaN.
@@ -160,8 +162,7 @@ uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
 | 64-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF64UI(uiA)                                                                                                       \
+#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF )))
-    ((((uiA)&UINT64_C(0x7FF8000000000000)) == UINT64_C(0x7FF0000000000000)) && ((uiA)&UINT64_C(0x0007FFFFFFFFFFFF)))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts
@@ -183,7 +184,8 @@ uint_fast64_t softfloat_commonNaNToF64UI(const struct commonNaN* aPtr);
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
+uint_fast64_t
+ softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 80-bit extended floating-point NaN.
@@ -197,8 +199,7 @@ uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
 | floating-point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNExtF80UI(uiA64, uiA0)                                                                                            \
+#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF )))
-    ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF)))
 
 #ifdef SOFTFLOAT_FAST_INT64
 
@@ -214,7 +215,9 @@ uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_extF80UIToCommonNaN(uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
+void
+ softfloat_extF80UIToCommonNaN(
+     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
@@ -232,7 +235,13 @@ struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr);
 | result.  If either original floating-point value is a signaling NaN, the
 | invalid exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0);
+struct uint128
+ softfloat_propagateNaNExtF80UI(
+     uint_fast16_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast16_t uiB64,
+     uint_fast64_t uiB0
+ );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -246,8 +255,7 @@ struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t
 | point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF128UI(uiA64, uiA0)                                                                                              \
+#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF ))))
-    ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF))))
 
 /*----------------------------------------------------------------------------
 | Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
@@ -256,7 +264,9 @@ struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t
 | pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid exception
 | is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_f128UIToCommonNaN(uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
+void
+ softfloat_f128UIToCommonNaN(
+     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -273,7 +283,13 @@ struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN*);
 | If either original floating-point value is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0);
+struct uint128
+ softfloat_propagateNaNF128UI(
+     uint_fast64_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast64_t uiB64,
+     uint_fast64_t uiB0
+ );
 
 #else
 
@@ -288,14 +304,18 @@ struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t u
 | common NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling
 | NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_extF80MToCommonNaN(const struct extFloat80M* aSPtr, struct commonNaN* zPtr);
+void
+ softfloat_extF80MToCommonNaN(
+     const struct extFloat80M *aSPtr, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
 | floating-point NaN, and stores this NaN at the location pointed to by
 | 'zSPtr'.
 *----------------------------------------------------------------------------*/
-void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr);
+void
+ softfloat_commonNaNToExtF80M(
+     const struct commonNaN *aPtr, struct extFloat80M *zSPtr );
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 80-bit extended floating-point values
@@ -303,7 +323,12 @@ void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat8
 | at the location pointed to by 'zSPtr'.  If either original floating-point
 | value is a signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr);
+void
+ softfloat_propagateNaNExtF80M(
+     const struct extFloat80M *aSPtr,
+     const struct extFloat80M *bSPtr,
+     struct extFloat80M *zSPtr
+ );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -321,7 +346,8 @@ void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct
 | four 32-bit elements that concatenate in the platform's normal endian order
 | to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void softfloat_f128MToCommonNaN(const uint32_t* aWPtr, struct commonNaN* zPtr);
+void
+ softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -329,7 +355,8 @@ void softfloat_f128MToCommonNaN(const uint32_t* aWPtr, struct commonNaN* zPtr);
 | 'zWPtr' points to an array of four 32-bit elements that concatenate in the
 | platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
+void
+ softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr );
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 128-bit floating-point values pointed to by
@@ -339,8 +366,11 @@ void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
 | and 'zWPtr' points to an array of four 32-bit elements that concatenate in
 | the platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr);
+void
+ softfloat_propagateNaNF128M(
+     const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr );
 
 #endif
 
 #endif
+

softfloat/source/include/internals.h

@@ -37,43 +37,33 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifndef internals_h
 #define internals_h 1
 
-#include "primitives.h"
-#include "softfloat_types.h"
 #include <stdbool.h>
 #include <stdint.h>
+#include "primitives.h"
+#include "softfloat_types.h"
 
-union ui16_f16 {
+union ui16_f16 { uint16_t ui; float16_t f; };
-    uint16_t ui;
+union ui32_f32 { uint32_t ui; float32_t f; };
-    float16_t f;
+union ui64_f64 { uint64_t ui; float64_t f; };
-};
-union ui32_f32 {
-    uint32_t ui;
-    float32_t f;
-};
-union ui64_f64 {
-    uint64_t ui;
-    float64_t f;
-};
 
 #ifdef SOFTFLOAT_FAST_INT64
-union extF80M_extF80 {
+union extF80M_extF80 { struct extFloat80M fM; extFloat80_t f; };
-    struct extFloat80M fM;
+union ui128_f128 { struct uint128 ui; float128_t f; };
-    extFloat80_t f;
-};
-union ui128_f128 {
-    struct uint128 ui;
-    float128_t f;
-};
 #endif
 
-enum { softfloat_mulAdd_subC = 1, softfloat_mulAdd_subProd = 2 };
+enum {
+    softfloat_mulAdd_subC    = 1,
+    softfloat_mulAdd_subProd = 2
+};
 
 /*----------------------------------------------------------------------------
 *----------------------------------------------------------------------------*/
 uint_fast32_t softfloat_roundToUI32( bool, uint_fast64_t, uint_fast8_t, bool );
 
 #ifdef SOFTFLOAT_FAST_INT64
-uint_fast64_t softfloat_roundToUI64(bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool);
+uint_fast64_t
+ softfloat_roundToUI64(
+     bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool );
 #else
 uint_fast64_t softfloat_roundMToUI64( bool, uint32_t *, uint_fast8_t, bool );
 #endif
@@ -81,7 +71,9 @@ uint_fast64_t softfloat_roundMToUI64(bool, uint32_t*, uint_fast8_t, bool);
 int_fast32_t softfloat_roundToI32( bool, uint_fast64_t, uint_fast8_t, bool );
 
 #ifdef SOFTFLOAT_FAST_INT64
-int_fast64_t softfloat_roundToI64(bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool);
+int_fast64_t
+ softfloat_roundToI64(
+     bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool );
 #else
 int_fast64_t softfloat_roundMToI64( bool, uint32_t *, uint_fast8_t, bool );
 #endif
@@ -95,10 +87,7 @@ int_fast64_t softfloat_roundMToI64(bool, uint32_t*, uint_fast8_t, bool);
 
 #define isNaNF16UI( a ) (((~(a) & 0x7C00) == 0) && ((a) & 0x03FF))
 
-struct exp8_sig16 {
+struct exp8_sig16 { int_fast8_t exp; uint_fast16_t sig; };
-    int_fast8_t exp;
-    uint_fast16_t sig;
-};
 struct exp8_sig16 softfloat_normSubnormalF16Sig( uint_fast16_t );
 
 float16_t softfloat_roundPackToF16( bool, int_fast16_t, uint_fast16_t );
@@ -106,7 +95,9 @@ float16_t softfloat_normRoundPackToF16(bool, int_fast16_t, uint_fast16_t);
 
 float16_t softfloat_addMagsF16( uint_fast16_t, uint_fast16_t );
 float16_t softfloat_subMagsF16( uint_fast16_t, uint_fast16_t );
-float16_t softfloat_mulAddF16(uint_fast16_t, uint_fast16_t, uint_fast16_t, uint_fast8_t);
+float16_t
+ softfloat_mulAddF16(
+     uint_fast16_t, uint_fast16_t, uint_fast16_t, uint_fast8_t );
 
 /*----------------------------------------------------------------------------
 *----------------------------------------------------------------------------*/
@@ -117,10 +108,7 @@ float16_t softfloat_mulAddF16(uint_fast16_t, uint_fast16_t, uint_fast16_t, uint_
 
 #define isNaNF32UI( a ) (((~(a) & 0x7F800000) == 0) && ((a) & 0x007FFFFF))
 
-struct exp16_sig32 {
+struct exp16_sig32 { int_fast16_t exp; uint_fast32_t sig; };
-    int_fast16_t exp;
-    uint_fast32_t sig;
-};
 struct exp16_sig32 softfloat_normSubnormalF32Sig( uint_fast32_t );
 
 float32_t softfloat_roundPackToF32( bool, int_fast16_t, uint_fast32_t );
@@ -128,7 +116,9 @@ float32_t softfloat_normRoundPackToF32(bool, int_fast16_t, uint_fast32_t);
 
 float32_t softfloat_addMagsF32( uint_fast32_t, uint_fast32_t );
 float32_t softfloat_subMagsF32( uint_fast32_t, uint_fast32_t );
-float32_t softfloat_mulAddF32(uint_fast32_t, uint_fast32_t, uint_fast32_t, uint_fast8_t);
+float32_t
+ softfloat_mulAddF32(
+     uint_fast32_t, uint_fast32_t, uint_fast32_t, uint_fast8_t );
 
 /*----------------------------------------------------------------------------
 *----------------------------------------------------------------------------*/
@@ -139,10 +129,7 @@ float32_t softfloat_mulAddF32(uint_fast32_t, uint_fast32_t, uint_fast32_t, uint_
 
 #define isNaNF64UI( a ) (((~(a) & UINT64_C( 0x7FF0000000000000 )) == 0) && ((a) & UINT64_C( 0x000FFFFFFFFFFFFF )))
 
-struct exp16_sig64 {
+struct exp16_sig64 { int_fast16_t exp; uint_fast64_t sig; };
-    int_fast16_t exp;
-    uint_fast64_t sig;
-};
 struct exp16_sig64 softfloat_normSubnormalF64Sig( uint_fast64_t );
 
 float64_t softfloat_roundPackToF64( bool, int_fast16_t, uint_fast64_t );
@@ -150,7 +137,9 @@ float64_t softfloat_normRoundPackToF64(bool, int_fast16_t, uint_fast64_t);
 
 float64_t softfloat_addMagsF64( uint_fast64_t, uint_fast64_t, bool );
 float64_t softfloat_subMagsF64( uint_fast64_t, uint_fast64_t, bool );
-float64_t softfloat_mulAddF64(uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast8_t);
+float64_t
+ softfloat_mulAddF64(
+     uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast8_t );
 
 /*----------------------------------------------------------------------------
 *----------------------------------------------------------------------------*/
@@ -165,17 +154,22 @@ float64_t softfloat_mulAddF64(uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_
 /*----------------------------------------------------------------------------
 *----------------------------------------------------------------------------*/
 
-struct exp32_sig64 {
+struct exp32_sig64 { int_fast32_t exp; uint64_t sig; };
-    int_fast32_t exp;
-    uint64_t sig;
-};
 struct exp32_sig64 softfloat_normSubnormalExtF80Sig( uint_fast64_t );
 
-extFloat80_t softfloat_roundPackToExtF80(bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t);
+extFloat80_t
-extFloat80_t softfloat_normRoundPackToExtF80(bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t);
+ softfloat_roundPackToExtF80(
+     bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t );
+extFloat80_t
+ softfloat_normRoundPackToExtF80(
+     bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t );
 
-extFloat80_t softfloat_addMagsExtF80(uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool);
+extFloat80_t
-extFloat80_t softfloat_subMagsExtF80(uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool);
+ softfloat_addMagsExtF80(
+     uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );
+extFloat80_t
+ softfloat_subMagsExtF80(
+     uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );
 
 /*----------------------------------------------------------------------------
 *----------------------------------------------------------------------------*/
@@ -186,35 +180,67 @@ extFloat80_t softfloat_subMagsExtF80(uint_fast16_t, uint_fast64_t, uint_fast16_t
 
 #define isNaNF128UI( a64, a0 ) (((~(a64) & UINT64_C( 0x7FFF000000000000 )) == 0) && (a0 || ((a64) & UINT64_C( 0x0000FFFFFFFFFFFF ))))
 
-struct exp32_sig128 {
+struct exp32_sig128 { int_fast32_t exp; struct uint128 sig; };
-    int_fast32_t exp;
+struct exp32_sig128
-    struct uint128 sig;
+ softfloat_normSubnormalF128Sig( uint_fast64_t, uint_fast64_t );
-};
-struct exp32_sig128 softfloat_normSubnormalF128Sig(uint_fast64_t, uint_fast64_t);
 
-float128_t softfloat_roundPackToF128(bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast64_t);
+float128_t
-float128_t softfloat_normRoundPackToF128(bool, int_fast32_t, uint_fast64_t, uint_fast64_t);
+ softfloat_roundPackToF128(
+     bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast64_t );
+float128_t
+ softfloat_normRoundPackToF128(
+     bool, int_fast32_t, uint_fast64_t, uint_fast64_t );
 
-float128_t softfloat_addMagsF128(uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool);
+float128_t
-float128_t softfloat_subMagsF128(uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool);
+ softfloat_addMagsF128(
-float128_t softfloat_mulAddF128(uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast8_t);
+     uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool );
+float128_t
+ softfloat_subMagsF128(
+     uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool );
+float128_t
+ softfloat_mulAddF128(
+     uint_fast64_t,
+     uint_fast64_t,
+     uint_fast64_t,
+     uint_fast64_t,
+     uint_fast64_t,
+     uint_fast64_t,
+     uint_fast8_t
+ );
 
 #else
 
 /*----------------------------------------------------------------------------
 *----------------------------------------------------------------------------*/
 
-bool softfloat_tryPropagateNaNExtF80M(const struct extFloat80M*, const struct extFloat80M*, struct extFloat80M*);
+bool
+ softfloat_tryPropagateNaNExtF80M(
+     const struct extFloat80M *,
+     const struct extFloat80M *,
+     struct extFloat80M *
+ );
 void softfloat_invalidExtF80M( struct extFloat80M * );
 
 int softfloat_normExtF80SigM( uint64_t * );
 
-void softfloat_roundPackMToExtF80M(bool, int32_t, uint32_t*, uint_fast8_t, struct extFloat80M*);
+void
-void softfloat_normRoundPackMToExtF80M(bool, int32_t, uint32_t*, uint_fast8_t, struct extFloat80M*);
+ softfloat_roundPackMToExtF80M(
+     bool, int32_t, uint32_t *, uint_fast8_t, struct extFloat80M * );
+void
+ softfloat_normRoundPackMToExtF80M(
+     bool, int32_t, uint32_t *, uint_fast8_t, struct extFloat80M * );
 
-void softfloat_addExtF80M(const struct extFloat80M*, const struct extFloat80M*, struct extFloat80M*, bool);
+void
+ softfloat_addExtF80M(
+     const struct extFloat80M *,
+     const struct extFloat80M *,
+     struct extFloat80M *,
+     bool
+ );
 
-int softfloat_compareNonnormExtF80M(const struct extFloat80M*, const struct extFloat80M*);
+int
+ softfloat_compareNonnormExtF80M(
+     const struct extFloat80M *, const struct extFloat80M * );
 
 /*----------------------------------------------------------------------------
 *----------------------------------------------------------------------------*/
@@ -225,7 +251,9 @@ int softfloat_compareNonnormExtF80M(const struct extFloat80M*, const struct extF
 
 bool softfloat_isNaNF128M( const uint32_t * );
 
-bool softfloat_tryPropagateNaNF128M(const uint32_t*, const uint32_t*, uint32_t*);
+bool
+ softfloat_tryPropagateNaNF128M(
+     const uint32_t *, const uint32_t *, uint32_t * );
 void softfloat_invalidF128M( uint32_t * );
 
 int softfloat_shiftNormSigF128M( const uint32_t *, uint_fast8_t, uint32_t * );
@@ -233,9 +261,18 @@ int softfloat_shiftNormSigF128M(const uint32_t*, uint_fast8_t, uint32_t*);
 void softfloat_roundPackMToF128M( bool, int32_t, uint32_t *, uint32_t * );
 void softfloat_normRoundPackMToF128M( bool, int32_t, uint32_t *, uint32_t * );
 
-void softfloat_addF128M(const uint32_t*, const uint32_t*, uint32_t*, bool);
+void
-void softfloat_mulAddF128M(const uint32_t*, const uint32_t*, const uint32_t*, uint32_t*, uint_fast8_t);
+ softfloat_addF128M( const uint32_t *, const uint32_t *, uint32_t *, bool );
+void
+ softfloat_mulAddF128M(
+     const uint32_t *,
+     const uint32_t *,
+     const uint32_t *,
+     uint32_t *,
+     uint_fast8_t
+ );
 
 #endif
 
 #endif
+

softfloat/source/include/opts-GCC.h

@@ -39,57 +39,57 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 #ifdef INLINE
 
-#include "primitiveTypes.h"
 #include <stdint.h>
+#include "primitiveTypes.h"
 
 #ifdef SOFTFLOAT_BUILTIN_CLZ
 
-INLINE uint_fast8_t softfloat_countLeadingZeros16(uint16_t a) { return a ? __builtin_clz(a) - 16 : 16; }
+INLINE uint_fast8_t softfloat_countLeadingZeros16( uint16_t a )
+    { return a ? __builtin_clz( a ) - 16 : 16; }
 #define softfloat_countLeadingZeros16 softfloat_countLeadingZeros16
 
-INLINE uint_fast8_t softfloat_countLeadingZeros32(uint32_t a) { return a ? __builtin_clz(a) : 32; }
+INLINE uint_fast8_t softfloat_countLeadingZeros32( uint32_t a )
+    { return a ? __builtin_clz( a ) : 32; }
 #define softfloat_countLeadingZeros32 softfloat_countLeadingZeros32
 
-INLINE uint_fast8_t softfloat_countLeadingZeros64(uint64_t a) { return a ? __builtin_clzll(a) : 64; }
+INLINE uint_fast8_t softfloat_countLeadingZeros64( uint64_t a )
+    { return a ? __builtin_clzll( a ) : 64; }
 #define softfloat_countLeadingZeros64 softfloat_countLeadingZeros64
 
 #endif
 
 #ifdef SOFTFLOAT_INTRINSIC_INT128
 
-INLINE struct uint128 softfloat_mul64ByShifted32To128(uint64_t a, uint32_t b) {
+INLINE struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b )
-    union {
+{
-        unsigned __int128 ui;
+    union { unsigned __int128 ui; struct uint128 s; } uZ;
-        struct uint128 s;
-    } uZ;
     uZ.ui = (unsigned __int128) a * ((uint_fast64_t) b<<32);
     return uZ.s;
 }
 #define softfloat_mul64ByShifted32To128 softfloat_mul64ByShifted32To128
 
-INLINE struct uint128 softfloat_mul64To128(uint64_t a, uint64_t b) {
+INLINE struct uint128 softfloat_mul64To128( uint64_t a, uint64_t b )
-    union {
+{
-        unsigned __int128 ui;
+    union { unsigned __int128 ui; struct uint128 s; } uZ;
-        struct uint128 s;
-    } uZ;
     uZ.ui = (unsigned __int128) a * b;
     return uZ.s;
 }
 #define softfloat_mul64To128 softfloat_mul64To128
 
 INLINE
-struct uint128 softfloat_mul128By32(uint64_t a64, uint64_t a0, uint32_t b) {
+struct uint128 softfloat_mul128By32( uint64_t a64, uint64_t a0, uint32_t b )
-    union {
+{
-        unsigned __int128 ui;
+    union { unsigned __int128 ui; struct uint128 s; } uZ;
-        struct uint128 s;
-    } uZ;
     uZ.ui = ((unsigned __int128) a64<<64 | a0) * b;
     return uZ.s;
 }
 #define softfloat_mul128By32 softfloat_mul128By32
 
 INLINE
-void softfloat_mul128To256M(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t* zPtr) {
+void
+ softfloat_mul128To256M(
+     uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t *zPtr )
+{
     unsigned __int128 z0, mid1, mid, z128;
     z0 = (unsigned __int128) a0 * b0;
     mid1 = (unsigned __int128) a64 * b0;
@@ -111,3 +111,4 @@ void softfloat_mul128To256M(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0
 #endif
 
 #endif
+

softfloat/source/include/primitiveTypes.h

@@ -42,27 +42,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifdef SOFTFLOAT_FAST_INT64
 
 #ifdef LITTLEENDIAN
-struct uint128 {
+struct uint128 { uint64_t v0, v64; };
-    uint64_t v0, v64;
+struct uint64_extra { uint64_t extra, v; };
-};
+struct uint128_extra { uint64_t extra; struct uint128 v; };
-struct uint64_extra {
-    uint64_t extra, v;
-};
-struct uint128_extra {
-    uint64_t extra;
-    struct uint128 v;
-};
 #else
-struct uint128 {
+struct uint128 { uint64_t v64, v0; };
-    uint64_t v64, v0;
+struct uint64_extra { uint64_t v, extra; };
-};
+struct uint128_extra { struct uint128 v; uint64_t extra; };
-struct uint64_extra {
-    uint64_t v, extra;
-};
-struct uint128_extra {
-    struct uint128 v;
-    uint64_t extra;
-};
 #endif
 
 #endif
@@ -81,8 +67,7 @@ struct uint128_extra {
 #define indexMultiwordLo( total, n ) 0
 #define indexMultiwordHiBut( total, n ) (n)
 #define indexMultiwordLoBut( total, n ) 0
-#define INIT_UINTM4(v3, v2, v1, v0)                                                                                                        \
+#define INIT_UINTM4( v3, v2, v1, v0 ) { v0, v1, v2, v3 }
-    { v0, v1, v2, v3 }
 #else
 #define wordIncr -1
 #define indexWord( total, n ) ((total) - 1 - (n))
@@ -93,8 +78,8 @@ struct uint128_extra {
 #define indexMultiwordLo( total, n ) ((total) - (n))
 #define indexMultiwordHiBut( total, n ) 0
 #define indexMultiwordLoBut( total, n ) (n)
-#define INIT_UINTM4(v3, v2, v1, v0)                                                                                                        \
+#define INIT_UINTM4( v3, v2, v1, v0 ) { v3, v2, v1, v0 }
-    { v3, v2, v1, v0 }
 #endif
 
 #endif
+

softfloat/source/include/primitives.h

@@ -37,9 +37,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifndef primitives_h
 #define primitives_h 1
 
-#include "primitiveTypes.h"
 #include <stdbool.h>
 #include <stdint.h>
+#include "primitiveTypes.h"
 
 #ifndef softfloat_shortShiftRightJam64
 /*----------------------------------------------------------------------------
@@ -50,7 +50,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-uint64_t softfloat_shortShiftRightJam64(uint64_t a, uint_fast8_t dist) { return a >> dist | ((a & (((uint_fast64_t)1 << dist) - 1)) != 0); }
+uint64_t softfloat_shortShiftRightJam64( uint64_t a, uint_fast8_t dist )
+    { return a>>dist | ((a & (((uint_fast64_t) 1<<dist) - 1)) != 0); }
 #else
 uint64_t softfloat_shortShiftRightJam64( uint64_t a, uint_fast8_t dist );
 #endif
@@ -67,8 +68,10 @@ uint64_t softfloat_shortShiftRightJam64(uint64_t a, uint_fast8_t dist);
 | is zero or nonzero.
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
-INLINE uint32_t softfloat_shiftRightJam32(uint32_t a, uint_fast16_t dist) {
+INLINE uint32_t softfloat_shiftRightJam32( uint32_t a, uint_fast16_t dist )
-    return (dist < 31) ? a >> dist | ((uint32_t)(a << (-dist & 31)) != 0) : (a != 0);
+{
+    return
+        (dist < 31) ? a>>dist | ((uint32_t) (a<<(-dist & 31)) != 0) : (a != 0);
 }
 #else
 uint32_t softfloat_shiftRightJam32( uint32_t a, uint_fast16_t dist );
@@ -86,8 +89,10 @@ uint32_t softfloat_shiftRightJam32(uint32_t a, uint_fast16_t dist);
 | is zero or nonzero.
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (3 <= INLINE_LEVEL)
-INLINE uint64_t softfloat_shiftRightJam64(uint64_t a, uint_fast32_t dist) {
+INLINE uint64_t softfloat_shiftRightJam64( uint64_t a, uint_fast32_t dist )
-    return (dist < 63) ? a >> dist | ((uint64_t)(a << (-dist & 63)) != 0) : (a != 0);
+{
+    return
+        (dist < 63) ? a>>dist | ((uint64_t) (a<<(-dist & 63)) != 0) : (a != 0);
 }
 #else
 uint64_t softfloat_shiftRightJam64( uint64_t a, uint_fast32_t dist );
@@ -107,7 +112,8 @@ extern const uint_least8_t softfloat_countLeadingZeros8[256];
 | 'a'.  If 'a' is zero, 16 is returned.
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
-INLINE uint_fast8_t softfloat_countLeadingZeros16(uint16_t a) {
+INLINE uint_fast8_t softfloat_countLeadingZeros16( uint16_t a )
+{
     uint_fast8_t count = 8;
     if ( 0x100 <= a ) {
         count = 0;
@@ -127,7 +133,8 @@ uint_fast8_t softfloat_countLeadingZeros16(uint16_t a);
 | 'a'.  If 'a' is zero, 32 is returned.
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (3 <= INLINE_LEVEL)
-INLINE uint_fast8_t softfloat_countLeadingZeros32(uint32_t a) {
+INLINE uint_fast8_t softfloat_countLeadingZeros32( uint32_t a )
+{
     uint_fast8_t count = 0;
     if ( a < 0x10000 ) {
         count = 16;
@@ -215,7 +222,8 @@ uint32_t softfloat_approxRecipSqrt32_1(unsigned int oddExpA, uint32_t a);
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (1 <= INLINE_LEVEL)
 INLINE
-bool softfloat_eq128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) { return (a64 == b64) && (a0 == b0); }
+bool softfloat_eq128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
+    { return (a64 == b64) && (a0 == b0); }
 #else
 bool softfloat_eq128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
 #endif
@@ -229,7 +237,8 @@ bool softfloat_eq128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0);
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-bool softfloat_le128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) { return (a64 < b64) || ((a64 == b64) && (a0 <= b0)); }
+bool softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
+    { return (a64 < b64) || ((a64 == b64) && (a0 <= b0)); }
 #else
 bool softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
 #endif
@@ -243,7 +252,8 @@ bool softfloat_le128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0);
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-bool softfloat_lt128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) { return (a64 < b64) || ((a64 == b64) && (a0 < b0)); }
+bool softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
+    { return (a64 < b64) || ((a64 == b64) && (a0 < b0)); }
 #else
 bool softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
 #endif
@@ -256,14 +266,17 @@ bool softfloat_lt128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0);
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-struct uint128 softfloat_shortShiftLeft128(uint64_t a64, uint64_t a0, uint_fast8_t dist) {
+struct uint128
+ softfloat_shortShiftLeft128( uint64_t a64, uint64_t a0, uint_fast8_t dist )
+{
     struct uint128 z;
     z.v64 = a64<<dist | a0>>(-dist & 63);
     z.v0 = a0<<dist;
     return z;
 }
 #else
-struct uint128 softfloat_shortShiftLeft128(uint64_t a64, uint64_t a0, uint_fast8_t dist);
+struct uint128
+ softfloat_shortShiftLeft128( uint64_t a64, uint64_t a0, uint_fast8_t dist );
 #endif
 #endif
 
@@ -274,14 +287,17 @@ struct uint128 softfloat_shortShiftLeft128(uint64_t a64, uint64_t a0, uint_fast8
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-struct uint128 softfloat_shortShiftRight128(uint64_t a64, uint64_t a0, uint_fast8_t dist) {
+struct uint128
+ softfloat_shortShiftRight128( uint64_t a64, uint64_t a0, uint_fast8_t dist )
+{
     struct uint128 z;
     z.v64 = a64>>dist;
     z.v0 = a64<<(-dist & 63) | a0>>dist;
     return z;
 }
 #else
-struct uint128 softfloat_shortShiftRight128(uint64_t a64, uint64_t a0, uint_fast8_t dist);
+struct uint128
+ softfloat_shortShiftRight128( uint64_t a64, uint64_t a0, uint_fast8_t dist );
 #endif
 #endif
 
@@ -292,14 +308,19 @@ struct uint128 softfloat_shortShiftRight128(uint64_t a64, uint64_t a0, uint_fast
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-struct uint64_extra softfloat_shortShiftRightJam64Extra(uint64_t a, uint64_t extra, uint_fast8_t dist) {
+struct uint64_extra
+ softfloat_shortShiftRightJam64Extra(
+     uint64_t a, uint64_t extra, uint_fast8_t dist )
+{
     struct uint64_extra z;
     z.v = a>>dist;
     z.extra = a<<(-dist & 63) | (extra != 0);
     return z;
 }
 #else
-struct uint64_extra softfloat_shortShiftRightJam64Extra(uint64_t a, uint64_t extra, uint_fast8_t dist);
+struct uint64_extra
+ softfloat_shortShiftRightJam64Extra(
+     uint64_t a, uint64_t extra, uint_fast8_t dist );
 #endif
 #endif
 
@@ -313,15 +334,22 @@ struct uint64_extra softfloat_shortShiftRightJam64Extra(uint64_t a, uint64_t ext
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (3 <= INLINE_LEVEL)
 INLINE
-struct uint128 softfloat_shortShiftRightJam128(uint64_t a64, uint64_t a0, uint_fast8_t dist) {
+struct uint128
+ softfloat_shortShiftRightJam128(
+     uint64_t a64, uint64_t a0, uint_fast8_t dist )
+{
     uint_fast8_t negDist = -dist;
     struct uint128 z;
     z.v64 = a64>>dist;
-    z.v0 = a64 << (negDist & 63) | a0 >> dist | ((uint64_t)(a0 << (negDist & 63)) != 0);
+    z.v0 =
+        a64<<(negDist & 63) | a0>>dist
+            | ((uint64_t) (a0<<(negDist & 63)) != 0);
     return z;
 }
 #else
-struct uint128 softfloat_shortShiftRightJam128(uint64_t a64, uint64_t a0, uint_fast8_t dist);
+struct uint128
+ softfloat_shortShiftRightJam128(
+     uint64_t a64, uint64_t a0, uint_fast8_t dist );
 #endif
 #endif
 
@@ -332,7 +360,10 @@ struct uint128 softfloat_shortShiftRightJam128(uint64_t a64, uint64_t a0, uint_f
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (3 <= INLINE_LEVEL)
 INLINE
-struct uint128_extra softfloat_shortShiftRightJam128Extra(uint64_t a64, uint64_t a0, uint64_t extra, uint_fast8_t dist) {
+struct uint128_extra
+ softfloat_shortShiftRightJam128Extra(
+     uint64_t a64, uint64_t a0, uint64_t extra, uint_fast8_t dist )
+{
     uint_fast8_t negDist = -dist;
     struct uint128_extra z;
     z.v.v64 = a64>>dist;
@@ -341,7 +372,9 @@ struct uint128_extra softfloat_shortShiftRightJam128Extra(uint64_t a64, uint64_t
     return z;
 }
 #else
-struct uint128_extra softfloat_shortShiftRightJam128Extra(uint64_t a64, uint64_t a0, uint64_t extra, uint_fast8_t dist);
+struct uint128_extra
+ softfloat_shortShiftRightJam128Extra(
+     uint64_t a64, uint64_t a0, uint64_t extra, uint_fast8_t dist );
 #endif
 #endif
 
@@ -364,7 +397,10 @@ struct uint128_extra softfloat_shortShiftRightJam128Extra(uint64_t a64, uint64_t
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (4 <= INLINE_LEVEL)
 INLINE
-struct uint64_extra softfloat_shiftRightJam64Extra(uint64_t a, uint64_t extra, uint_fast32_t dist) {
+struct uint64_extra
+ softfloat_shiftRightJam64Extra(
+     uint64_t a, uint64_t extra, uint_fast32_t dist )
+{
     struct uint64_extra z;
     if ( dist < 64 ) {
         z.v = a>>dist;
@@ -377,7 +413,9 @@ struct uint64_extra softfloat_shiftRightJam64Extra(uint64_t a, uint64_t extra, u
     return z;
 }
 #else
-struct uint64_extra softfloat_shiftRightJam64Extra(uint64_t a, uint64_t extra, uint_fast32_t dist);
+struct uint64_extra
+ softfloat_shiftRightJam64Extra(
+     uint64_t a, uint64_t extra, uint_fast32_t dist );
 #endif
 #endif
 
@@ -392,7 +430,8 @@ struct uint64_extra softfloat_shiftRightJam64Extra(uint64_t a, uint64_t extra, u
 | greater than 128, the result will be either 0 or 1, depending on whether the
 | original 128 bits are all zeros.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_shiftRightJam128(uint64_t a64, uint64_t a0, uint_fast32_t dist);
+struct uint128
+ softfloat_shiftRightJam128( uint64_t a64, uint64_t a0, uint_fast32_t dist );
 #endif
 
 #ifndef softfloat_shiftRightJam128Extra
@@ -413,7 +452,9 @@ struct uint128 softfloat_shiftRightJam128(uint64_t a64, uint64_t a0, uint_fast32
 | is modified as described above and returned in the 'extra' field of the
 | result.)
 *----------------------------------------------------------------------------*/
-struct uint128_extra softfloat_shiftRightJam128Extra(uint64_t a64, uint64_t a0, uint64_t extra, uint_fast32_t dist);
+struct uint128_extra
+ softfloat_shiftRightJam128Extra(
+     uint64_t a64, uint64_t a0, uint64_t extra, uint_fast32_t dist );
 #endif
 
 #ifndef softfloat_shiftRightJam256M
@@ -429,7 +470,9 @@ struct uint128_extra softfloat_shiftRightJam128Extra(uint64_t a64, uint64_t a0,
 | is greater than 256, the stored result will be either 0 or 1, depending on
 | whether the original 256 bits are all zeros.
 *----------------------------------------------------------------------------*/
-void softfloat_shiftRightJam256M(const uint64_t* aPtr, uint_fast32_t dist, uint64_t* zPtr);
+void
+ softfloat_shiftRightJam256M(
+     const uint64_t *aPtr, uint_fast32_t dist, uint64_t *zPtr );
 #endif
 
 #ifndef softfloat_add128
@@ -440,14 +483,17 @@ void softfloat_shiftRightJam256M(const uint64_t* aPtr, uint_fast32_t dist, uint6
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-struct uint128 softfloat_add128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) {
+struct uint128
+ softfloat_add128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
+{
     struct uint128 z;
     z.v0 = a0 + b0;
     z.v64 = a64 + b64 + (z.v0 < a0);
     return z;
 }
 #else
-struct uint128 softfloat_add128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0);
+struct uint128
+ softfloat_add128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
 #endif
 #endif
 
@@ -459,7 +505,9 @@ struct uint128 softfloat_add128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_
 | an array of four 64-bit elements that concatenate in the platform's normal
 | endian order to form a 256-bit integer.
 *----------------------------------------------------------------------------*/
-void softfloat_add256M(const uint64_t* aPtr, const uint64_t* bPtr, uint64_t* zPtr);
+void
+ softfloat_add256M(
+     const uint64_t *aPtr, const uint64_t *bPtr, uint64_t *zPtr );
 #endif
 
 #ifndef softfloat_sub128
@@ -470,7 +518,9 @@ void softfloat_add256M(const uint64_t* aPtr, const uint64_t* bPtr, uint64_t* zPt
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-struct uint128 softfloat_sub128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) {
+struct uint128
+ softfloat_sub128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
+{
     struct uint128 z;
     z.v0 = a0 - b0;
     z.v64 = a64 - b64;
@@ -478,7 +528,8 @@ struct uint128 softfloat_sub128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_
     return z;
 }
 #else
-struct uint128 softfloat_sub128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0);
+struct uint128
+ softfloat_sub128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
 #endif
 #endif
 
@@ -491,7 +542,9 @@ struct uint128 softfloat_sub128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_
 | 64-bit elements that concatenate in the platform's normal endian order to
 | form a 256-bit integer.
 *----------------------------------------------------------------------------*/
-void softfloat_sub256M(const uint64_t* aPtr, const uint64_t* bPtr, uint64_t* zPtr);
+void
+ softfloat_sub256M(
+     const uint64_t *aPtr, const uint64_t *bPtr, uint64_t *zPtr );
 #endif
 
 #ifndef softfloat_mul64ByShifted32To128
@@ -499,7 +552,8 @@ void softfloat_sub256M(const uint64_t* aPtr, const uint64_t* bPtr, uint64_t* zPt
 | Returns the 128-bit product of 'a', 'b', and 2^32.
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (3 <= INLINE_LEVEL)
-INLINE struct uint128 softfloat_mul64ByShifted32To128(uint64_t a, uint32_t b) {
+INLINE struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b )
+{
     uint_fast64_t mid;
     struct uint128 z;
     mid = (uint_fast64_t) (uint32_t) a * b;
@@ -527,7 +581,8 @@ struct uint128 softfloat_mul64To128(uint64_t a, uint64_t b);
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (4 <= INLINE_LEVEL)
 INLINE
-struct uint128 softfloat_mul128By32(uint64_t a64, uint64_t a0, uint32_t b) {
+struct uint128 softfloat_mul128By32( uint64_t a64, uint64_t a0, uint32_t b )
+{
     struct uint128 z;
     uint_fast64_t mid;
     uint_fast32_t carry;
@@ -550,7 +605,9 @@ struct uint128 softfloat_mul128By32(uint64_t a64, uint64_t a0, uint32_t b);
 | Argument 'zPtr' points to an array of four 64-bit elements that concatenate
 | in the platform's normal endian order to form a 256-bit integer.
 *----------------------------------------------------------------------------*/
-void softfloat_mul128To256M(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t* zPtr);
+void
+ softfloat_mul128To256M(
+     uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t *zPtr );
 #endif
 
 #else
@@ -581,7 +638,8 @@ int_fast8_t softfloat_compare96M(const uint32_t* aPtr, const uint32_t* bPtr);
 | Each of 'aPtr' and 'bPtr' points to an array of four 32-bit elements that
 | concatenate in the platform's normal endian order to form a 128-bit integer.
 *----------------------------------------------------------------------------*/
-int_fast8_t softfloat_compare128M(const uint32_t* aPtr, const uint32_t* bPtr);
+int_fast8_t
+ softfloat_compare128M( const uint32_t *aPtr, const uint32_t *bPtr );
 #endif
 
 #ifndef softfloat_shortShiftLeft64To96M
@@ -594,14 +652,19 @@ int_fast8_t softfloat_compare128M(const uint32_t* aPtr, const uint32_t* bPtr);
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-void softfloat_shortShiftLeft64To96M(uint64_t a, uint_fast8_t dist, uint32_t* zPtr) {
+void
+ softfloat_shortShiftLeft64To96M(
+     uint64_t a, uint_fast8_t dist, uint32_t *zPtr )
+{
     zPtr[indexWord( 3, 0 )] = (uint32_t) a<<dist;
     a >>= 32 - dist;
     zPtr[indexWord( 3, 2 )] = a>>32;
     zPtr[indexWord( 3, 1 )] = a;
 }
 #else
-void softfloat_shortShiftLeft64To96M(uint64_t a, uint_fast8_t dist, uint32_t* zPtr);
+void
+ softfloat_shortShiftLeft64To96M(
+     uint64_t a, uint_fast8_t dist, uint32_t *zPtr );
 #endif
 #endif
 
@@ -615,7 +678,13 @@ void softfloat_shortShiftLeft64To96M(uint64_t a, uint_fast8_t dist, uint32_t* zP
 | that concatenate in the platform's normal endian order to form an N-bit
 | integer.
 *----------------------------------------------------------------------------*/
-void softfloat_shortShiftLeftM(uint_fast8_t size_words, const uint32_t* aPtr, uint_fast8_t dist, uint32_t* zPtr);
+void
+ softfloat_shortShiftLeftM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     uint_fast8_t dist,
+     uint32_t *zPtr
+ );
 #endif
 
 #ifndef softfloat_shortShiftLeft96M
@@ -653,7 +722,13 @@ void softfloat_shortShiftLeftM(uint_fast8_t size_words, const uint32_t* aPtr, ui
 |   The value of 'dist' can be arbitrarily large.  In particular, if 'dist' is
 | greater than N, the stored result will be 0.
 *----------------------------------------------------------------------------*/
-void softfloat_shiftLeftM(uint_fast8_t size_words, const uint32_t* aPtr, uint32_t dist, uint32_t* zPtr);
+void
+ softfloat_shiftLeftM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     uint32_t dist,
+     uint32_t *zPtr
+ );
 #endif
 
 #ifndef softfloat_shiftLeft96M
@@ -690,7 +765,13 @@ void softfloat_shiftLeftM(uint_fast8_t size_words, const uint32_t* aPtr, uint32_
 | that concatenate in the platform's normal endian order to form an N-bit
 | integer.
 *----------------------------------------------------------------------------*/
-void softfloat_shortShiftRightM(uint_fast8_t size_words, const uint32_t* aPtr, uint_fast8_t dist, uint32_t* zPtr);
+void
+ softfloat_shortShiftRightM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     uint_fast8_t dist,
+     uint32_t *zPtr
+ );
 #endif
 
 #ifndef softfloat_shortShiftRight128M
@@ -720,7 +801,9 @@ void softfloat_shortShiftRightM(uint_fast8_t size_words, const uint32_t* aPtr, u
 | to a 'size_words'-long array of 32-bit elements that concatenate in the
 | platform's normal endian order to form an N-bit integer.
 *----------------------------------------------------------------------------*/
-void softfloat_shortShiftRightJamM(uint_fast8_t, const uint32_t*, uint_fast8_t, uint32_t*);
+void
+ softfloat_shortShiftRightJamM(
+     uint_fast8_t, const uint32_t *, uint_fast8_t, uint32_t * );
 #endif
 
 #ifndef softfloat_shortShiftRightJam160M
@@ -742,7 +825,13 @@ void softfloat_shortShiftRightJamM(uint_fast8_t, const uint32_t*, uint_fast8_t,
 |   The value of 'dist' can be arbitrarily large.  In particular, if 'dist' is
 | greater than N, the stored result will be 0.
 *----------------------------------------------------------------------------*/
-void softfloat_shiftRightM(uint_fast8_t size_words, const uint32_t* aPtr, uint32_t dist, uint32_t* zPtr);
+void
+ softfloat_shiftRightM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     uint32_t dist,
+     uint32_t *zPtr
+ );
 #endif
 
 #ifndef softfloat_shiftRight96M
@@ -767,7 +856,13 @@ void softfloat_shiftRightM(uint_fast8_t size_words, const uint32_t* aPtr, uint32
 | is greater than N, the stored result will be either 0 or 1, depending on
 | whether the original N bits are all zeros.
 *----------------------------------------------------------------------------*/
-void softfloat_shiftRightJamM(uint_fast8_t size_words, const uint32_t* aPtr, uint32_t dist, uint32_t* zPtr);
+void
+ softfloat_shiftRightJamM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     uint32_t dist,
+     uint32_t *zPtr
+ );
 #endif
 
 #ifndef softfloat_shiftRightJam96M
@@ -803,7 +898,13 @@ void softfloat_shiftRightJamM(uint_fast8_t size_words, const uint32_t* aPtr, uin
 | elements that concatenate in the platform's normal endian order to form an
 | N-bit integer.
 *----------------------------------------------------------------------------*/
-void softfloat_addM(uint_fast8_t size_words, const uint32_t* aPtr, const uint32_t* bPtr, uint32_t* zPtr);
+void
+ softfloat_addM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     const uint32_t *bPtr,
+     uint32_t *zPtr
+ );
 #endif
 
 #ifndef softfloat_add96M
@@ -839,7 +940,14 @@ void softfloat_addM(uint_fast8_t size_words, const uint32_t* aPtr, const uint32_
 | points to a 'size_words'-long array of 32-bit elements that concatenate in
 | the platform's normal endian order to form an N-bit integer.
 *----------------------------------------------------------------------------*/
-uint_fast8_t softfloat_addCarryM(uint_fast8_t size_words, const uint32_t* aPtr, const uint32_t* bPtr, uint_fast8_t carry, uint32_t* zPtr);
+uint_fast8_t
+ softfloat_addCarryM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     const uint32_t *bPtr,
+     uint_fast8_t carry,
+     uint32_t *zPtr
+ );
 #endif
 
 #ifndef softfloat_addComplCarryM
@@ -848,8 +956,14 @@ uint_fast8_t softfloat_addCarryM(uint_fast8_t size_words, const uint32_t* aPtr,
 | the value of the unsigned integer pointed to by 'bPtr' is bit-wise completed
 | before the addition.
 *----------------------------------------------------------------------------*/
-uint_fast8_t softfloat_addComplCarryM(uint_fast8_t size_words, const uint32_t* aPtr, const uint32_t* bPtr, uint_fast8_t carry,
+uint_fast8_t
-                                      uint32_t* zPtr);
+ softfloat_addComplCarryM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     const uint32_t *bPtr,
+     uint_fast8_t carry,
+     uint32_t *zPtr
+ );
 #endif
 
 #ifndef softfloat_addComplCarry96M
@@ -938,7 +1052,13 @@ void softfloat_sub1XM(uint_fast8_t size_words, uint32_t* zPtr);
 | array of 32-bit elements that concatenate in the platform's normal endian
 | order to form an N-bit integer.
 *----------------------------------------------------------------------------*/
-void softfloat_subM(uint_fast8_t size_words, const uint32_t* aPtr, const uint32_t* bPtr, uint32_t* zPtr);
+void
+ softfloat_subM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     const uint32_t *bPtr,
+     uint32_t *zPtr
+ );
 #endif
 
 #ifndef softfloat_sub96M
@@ -984,7 +1104,9 @@ void softfloat_mul64To128M(uint64_t a, uint64_t b, uint32_t* zPtr);
 | Argument 'zPtr' points to an array of eight 32-bit elements that concatenate
 | to form a 256-bit integer.
 *----------------------------------------------------------------------------*/
-void softfloat_mul128MTo256M(const uint32_t* aPtr, const uint32_t* bPtr, uint32_t* zPtr);
+void
+ softfloat_mul128MTo256M(
+     const uint32_t *aPtr, const uint32_t *bPtr, uint32_t *zPtr );
 #endif
 
 #ifndef softfloat_remStepMBy32
@@ -997,8 +1119,15 @@ void softfloat_mul128MTo256M(const uint32_t* aPtr, const uint32_t* bPtr, uint32_
 | to a 'size_words'-long array of 32-bit elements that concatenate in the
 | platform's normal endian order to form an N-bit integer.
 *----------------------------------------------------------------------------*/
-void softfloat_remStepMBy32(uint_fast8_t size_words, const uint32_t* remPtr, uint_fast8_t dist, const uint32_t* bPtr, uint32_t q,
+void
-                            uint32_t* zPtr);
+ softfloat_remStepMBy32(
+     uint_fast8_t size_words,
+     const uint32_t *remPtr,
+     uint_fast8_t dist,
+     const uint32_t *bPtr,
+     uint32_t q,
+     uint32_t *zPtr
+ );
 #endif
 
 #ifndef softfloat_remStep96MBy32
@@ -1028,3 +1157,4 @@ void softfloat_remStepMBy32(uint_fast8_t size_words, const uint32_t* remPtr, uin
 #endif
 
 #endif
+

softfloat/source/include/softfloat.h

@@ -34,6 +34,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 =============================================================================*/
 
+
 /*============================================================================
 | Note:  If SoftFloat is made available as a general library for programs to
 | use, it is strongly recommended that a platform-specific version of this
@@ -41,12 +42,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | eliminates all dependencies on compile-time macros.
 *============================================================================*/
 
+
 #ifndef softfloat_h
 #define softfloat_h 1
 
-#include "softfloat_types.h"
 #include <stdbool.h>
 #include <stdint.h>
+#include "softfloat_types.h"
 
 #ifndef THREAD_LOCAL
 #define THREAD_LOCAL
@@ -56,7 +58,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | Software floating-point underflow tininess-detection mode.
 *----------------------------------------------------------------------------*/
 extern THREAD_LOCAL uint_fast8_t softfloat_detectTininess;
-enum { softfloat_tininess_beforeRounding = 0, softfloat_tininess_afterRounding = 1 };
+enum {
+    softfloat_tininess_beforeRounding = 0,
+    softfloat_tininess_afterRounding  = 1
+};
 
 /*----------------------------------------------------------------------------
 | Software floating-point rounding mode.  (Mode "odd" is supported only if
@@ -283,7 +288,9 @@ float16_t extF80M_to_f16(const extFloat80_t*);
 float32_t extF80M_to_f32( const extFloat80_t * );
 float64_t extF80M_to_f64( const extFloat80_t * );
 void extF80M_to_f128M( const extFloat80_t *, float128_t * );
-void extF80M_roundToInt(const extFloat80_t*, uint_fast8_t, bool, extFloat80_t*);
+void
+ extF80M_roundToInt(
+     const extFloat80_t *, uint_fast8_t, bool, extFloat80_t * );
 void extF80M_add( const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
 void extF80M_sub( const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
 void extF80M_mul( const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
@@ -346,7 +353,10 @@ void f128M_roundToInt(const float128_t*, uint_fast8_t, bool, float128_t*);
 void f128M_add( const float128_t *, const float128_t *, float128_t * );
 void f128M_sub( const float128_t *, const float128_t *, float128_t * );
 void f128M_mul( const float128_t *, const float128_t *, float128_t * );
-void f128M_mulAdd(const float128_t*, const float128_t*, const float128_t*, float128_t*);
+void
+ f128M_mulAdd(
+     const float128_t *, const float128_t *, const float128_t *, float128_t *
+ );
 void f128M_div( const float128_t *, const float128_t *, float128_t * );
 void f128M_rem( const float128_t *, const float128_t *, float128_t * );
 void f128M_sqrt( const float128_t *, float128_t * );
@@ -359,3 +369,4 @@ bool f128M_lt_quiet(const float128_t*, const float128_t*);
 bool f128M_isSignalingNaN( const float128_t * );
 
 #endif
+

softfloat/source/include/softfloat_types.h

@@ -47,18 +47,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | the types below may, if desired, be defined as aliases for the native types
 | (typically 'float' and 'double', and possibly 'long double').
 *----------------------------------------------------------------------------*/
-typedef struct {
+typedef struct { uint16_t v; } float16_t;
-    uint16_t v;
+typedef struct { uint32_t v; } float32_t;
-} float16_t;
+typedef struct { uint64_t v; } float64_t;
-typedef struct {
+typedef struct { uint64_t v[2]; } float128_t;
-    uint32_t v;
-} float32_t;
-typedef struct {
-    uint64_t v;
-} float64_t;
-typedef struct {
-    uint64_t v[2];
-} float128_t;
 
 /*----------------------------------------------------------------------------
 | The format of an 80-bit extended floating-point number in memory.  This
@@ -66,15 +58,9 @@ typedef struct {
 | named 'signif'.
 *----------------------------------------------------------------------------*/
 #ifdef LITTLEENDIAN
-struct extFloat80M {
+struct extFloat80M { uint64_t signif; uint16_t signExp; };
-    uint64_t signif;
-    uint16_t signExp;
-};
 #else
-struct extFloat80M {
+struct extFloat80M { uint16_t signExp; uint64_t signif; };
-    uint16_t signExp;
-    uint64_t signif;
-};
 #endif
 
 /*----------------------------------------------------------------------------
@@ -92,3 +78,4 @@ struct extFloat80M {
 typedef struct extFloat80M extFloat80_t;
 
 #endif
+

src-gen/.gitignore

@@ -1,3 +1,2 @@
 /iss
 /vm
-/sysc

src/iss/arch/hwl.h

@@ -46,7 +46,7 @@ public:
     using this_class = hwl<BASE>;
     using reg_t = typename BASE::reg_t;
 
-    hwl(feature_config cfg = feature_config{});
+    hwl();
     virtual ~hwl() = default;
 
 protected:
@@ -54,9 +54,9 @@ protected:
     iss::status write_custom_csr_reg(unsigned addr, reg_t val) override;
 };
 
+
 template<typename BASE>
-inline hwl<BASE>::hwl(feature_config cfg)
+inline hwl<BASE>::hwl() {
-: BASE(cfg) {
     for (unsigned addr = 0x800; addr < 0x803; ++addr){
         this->register_custom_csr_rd(addr);
         this->register_custom_csr_wr(addr);
@@ -67,50 +67,28 @@ inline hwl<BASE>::hwl(feature_config cfg)
     }
 }
 
-template <typename BASE> inline iss::status iss::arch::hwl<BASE>::read_custom_csr_reg(unsigned addr, reg_t& val) {
+template<typename BASE>
+inline iss::status iss::arch::hwl<BASE>::read_custom_csr_reg(unsigned addr, reg_t &val) {
     switch(addr){
-    case 0x800:
+    case 0x800: val = this->reg.lpstart0; break;
-        val = this->reg.lpstart0;
+    case 0x801: val = this->reg.lpend0;   break;
-        break;
+    case 0x802: val = this->reg.lpcount0; break;
-    case 0x801:
+    case 0x804: val = this->reg.lpstart1; break;
-        val = this->reg.lpend0;
+    case 0x805: val = this->reg.lpend1;   break;
-        break;
+    case 0x806: val = this->reg.lpcount1; break;
-    case 0x802:
-        val = this->reg.lpcount0;
-        break;
-    case 0x804:
-        val = this->reg.lpstart1;
-        break;
-    case 0x805:
-        val = this->reg.lpend1;
-        break;
-    case 0x806:
-        val = this->reg.lpcount1;
-        break;
     }
     return iss::Ok;
 }
 
-template <typename BASE> inline iss::status iss::arch::hwl<BASE>::write_custom_csr_reg(unsigned addr, reg_t val) {
+template<typename BASE>
+inline iss::status iss::arch::hwl<BASE>::write_custom_csr_reg(unsigned addr, reg_t val) {
     switch(addr){
-    case 0x800:
+    case 0x800: this->reg.lpstart0 = val; break;
-        this->reg.lpstart0 = val;
+    case 0x801: this->reg.lpend0   = val; break;
-        break;
+    case 0x802: this->reg.lpcount0 = val; break;
-    case 0x801:
+    case 0x804: this->reg.lpstart1 = val; break;
-        this->reg.lpend0 = val;
+    case 0x805: this->reg.lpend1   = val; break;
-        break;
+    case 0x806: this->reg.lpcount1 = val; break;
-    case 0x802:
-        this->reg.lpcount0 = val;
-        break;
-    case 0x804:
-        this->reg.lpstart1 = val;
-        break;
-    case 0x805:
-        this->reg.lpend1 = val;
-        break;
-    case 0x806:
-        this->reg.lpcount1 = val;
-        break;
     }
     return iss::Ok;
 }
@@ -118,4 +96,5 @@ template <typename BASE> inline iss::status iss::arch::hwl<BASE>::write_custom_c
 } // namespace arch
 } // namespace iss
 
+
 #endif /* _RISCV_HART_M_P_H */

src/iss/arch/riscv_hart_common.h

@@ -175,6 +175,7 @@ enum riscv_csr {
     dscratch1 = 0x7B3
 };
 
+
 enum {
     PGSHIFT = 12,
     PTE_PPN_SHIFT = 10,
@@ -225,8 +226,6 @@ struct feature_config {
     unsigned clic_num_trigger{0};
     uint64_t tcm_base{0x10000000};
     uint64_t tcm_size{0x8000};
-    uint64_t io_address{0xf0000000};
-    uint64_t io_addr_mask{0xf0000000};
 };
 
 class trap_load_access_fault : public trap_access {
@@ -297,7 +296,7 @@ inline void write_reg_uint32(uint64_t offs, uint32_t& reg, const uint8_t* const
     }
 }
 
-} // namespace arch
+}
-} // namespace iss
+}
 
 #endif

src/iss/arch/riscv_hart_m_p.h

@@ -35,22 +35,22 @@
 #ifndef _RISCV_HART_M_P_H
 #define _RISCV_HART_M_P_H
 
+#include "riscv_hart_common.h"
 #include "iss/arch/traits.h"
 #include "iss/instrumentation_if.h"
 #include "iss/log_categories.h"
 #include "iss/vm_if.h"
-#include "riscv_hart_common.h"
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
 #endif
 #include <array>
 #include <elfio/elfio.hpp>
 #include <fmt/format.h>
-#include <functional>
 #include <iomanip>
 #include <sstream>
 #include <type_traits>
 #include <unordered_map>
+#include <functional>
 #include <util/bit_field.h>
 #include <util/ities.h>
 #include <util/sparse_array.h>
@@ -86,11 +86,10 @@ protected:
                                               "Load page fault",                // d
                                               "Reserved",                       // e
                                               "Store/AMO page fault"}};
-    const std::array<const char*, 12> irq_str = {{"User software interrupt", "Supervisor software interrupt", "Reserved",
+    const std::array<const char *, 12> irq_str = {
-                                                  "Machine software interrupt", "User timer interrupt", "Supervisor timer interrupt",
+        {"User software interrupt", "Supervisor software interrupt", "Reserved", "Machine software interrupt",
-                                                  "Reserved", "Machine timer interrupt", "User external interrupt",
+         "User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt",
-                                                  "Supervisor external interrupt", "Reserved", "Machine external interrupt"}};
+         "User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}};
-
 public:
     using core = BASE;
     using this_class = riscv_hart_m_p<BASE, FEAT>;
@@ -109,8 +108,7 @@ public:
     template <typename T> class hart_state<T, typename std::enable_if<std::is_same<T, uint32_t>::value>::type> {
     public:
         BEGIN_BF_DECL(mstatus_t, T);
-        // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR
+        // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11)))
-        // XS==11)))
         BF_FIELD(SD, 31, 1);
         // Trap SRET
         BF_FIELD(TSR, 22, 1);
@@ -124,8 +122,7 @@ public:
         BF_FIELD(SUM, 18, 1);
         // Modify PRiVilege
         BF_FIELD(MPRV, 17, 1);
-        // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None
+        // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None dirty, some clean/Some dirty
-        // dirty, some clean/Some dirty
         BF_FIELD(XS, 15, 2);
         // floating-point unit status Off/Initial/Clean/Dirty
         BF_FIELD(FS, 13, 2);
@@ -180,8 +177,7 @@ public:
     template <typename T> class hart_state<T, typename std::enable_if<std::is_same<T, uint64_t>::value>::type> {
     public:
         BEGIN_BF_DECL(mstatus_t, T);
-        // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR
+        // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11)))
-        // XS==11)))
         BF_FIELD(SD, 63, 1);
         // value of XLEN for S-mode
         BF_FIELD(SXL, 34, 2);
@@ -199,8 +195,7 @@ public:
         BF_FIELD(SUM, 18, 1);
         // Modify PRiVilege
         BF_FIELD(MPRV, 17, 1);
-        // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None
+        // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None dirty, some clean/Some dirty
-        // dirty, some clean/Some dirty
         BF_FIELD(XS, 15, 2);
         // floating-point unit status Off/Initial/Clean/Dirty
         BF_FIELD(FS, 13, 2);
@@ -257,8 +252,12 @@ public:
         return 0b100010001000; // only machine mode is supported
     }
 
-    constexpr bool has_compressed() { return traits<BASE>::MISA_VAL & 0b0100; }
+    constexpr bool has_compressed() {
-    constexpr reg_t get_pc_mask() { return has_compressed() ? (reg_t)~1 : (reg_t)~3; }
+        return traits<BASE>::MISA_VAL&0b0100;
+    }
+    constexpr reg_t get_pc_mask() {
+        return has_compressed()?(reg_t)~1:(reg_t)~3;
+    }
 
     riscv_hart_m_p(feature_config cfg = feature_config{});
     virtual ~riscv_hart_m_p() = default;
@@ -267,10 +266,10 @@ public:
 
     std::pair<uint64_t, bool> load_file(std::string name, int type = -1) override;
 
-    iss::status read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length,
+    iss::status read(const address_type type, const access_type access, const uint32_t space,
-                     uint8_t* const data) override;
+            const uint64_t addr, const unsigned length, uint8_t *const data) override;
-    iss::status write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length,
+    iss::status write(const address_type type, const access_type access, const uint32_t space,
-                      const uint8_t* const data) override;
+            const uint64_t addr, const unsigned length, const uint8_t *const data) override;
 
     uint64_t enter_trap(uint64_t flags) override { return riscv_hart_m_p::enter_trap(flags, fault_data, fault_data); }
     uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
@@ -280,16 +279,19 @@ public:
 	void set_mhartid(reg_t mhartid) { mhartid_reg = mhartid; };
 
     void disass_output(uint64_t pc, const std::string instr) override {
-        CLOG(INFO, disass) << fmt::format("0x{:016x}    {:40} [s:0x{:x};c:{}]", pc, instr, (reg_t)state.mstatus,
+        CLOG(INFO, disass) << fmt::format("0x{:016x}    {:40} [s:0x{:x};c:{}]",
-                                          this->reg.icount + cycle_offset);
+                pc, instr, (reg_t)state.mstatus, this->reg.icount + cycle_offset);
     };
 
     iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
 
-    void set_csr(unsigned addr, reg_t val) { csr[addr & csr.page_addr_mask] = val; }
+    void set_csr(unsigned addr, reg_t val){
-
+        csr[addr & csr.page_addr_mask] = val;
-    void set_irq_num(unsigned i) { mcause_max_irq = 1 << util::ilog2(i); }
+    }
 
+    void set_irq_num(unsigned i) {
+        mcause_max_irq=1<<util::ilog2(i);
+    }
 protected:
     struct riscv_instrumentation_if : public iss::instrumentation_if {
 
@@ -302,9 +304,9 @@ protected:
          */
         const std::string core_type_name() const override { return traits<BASE>::core_type; }
 
-        uint64_t get_pc() override { return arch.reg.PC; }
+        uint64_t get_pc() override { return arch.reg.PC; };
 
-        uint64_t get_next_pc() override { return arch.reg.NEXT_PC; }
+        uint64_t get_next_pc() override { return arch.reg.NEXT_PC; };
 
         uint64_t get_instr_word() override { return arch.reg.instruction; }
 
@@ -314,13 +316,9 @@ protected:
 
         uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }
 
-        void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; }
+        void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
 
-        bool is_branch_taken() override { return arch.reg.last_branch; }
+        bool is_branch_taken() override { return arch.reg.last_branch; };
-
-        unsigned get_reg_num() override { return traits<BASE>::NUM_REGS; }
-
-        unsigned get_reg_size(unsigned num) override { return traits<BASE>::reg_bit_widths[num]; }
 
         riscv_hart_m_p<BASE, FEAT> &arch;
     };
@@ -405,8 +403,12 @@ protected:
     virtual iss::status read_custom_csr_reg(unsigned addr, reg_t &val) {return iss::status::Err;};
     virtual iss::status write_custom_csr_reg(unsigned addr, reg_t val) {return iss::status::Err;};
 
-    void register_custom_csr_rd(unsigned addr) { csr_rd_cb[addr] = &this_class::read_custom_csr_reg; }
+    void register_custom_csr_rd(unsigned addr){
-    void register_custom_csr_wr(unsigned addr) { csr_wr_cb[addr] = &this_class::write_custom_csr_reg; }
+        csr_rd_cb[addr] = &this_class::read_custom_csr_reg;
+    }
+    void register_custom_csr_wr(unsigned addr){
+        csr_wr_cb[addr] = &this_class::write_custom_csr_reg;
+    }
 
     reg_t mhartid_reg{0x0};
 
@@ -419,8 +421,8 @@ protected:
     feature_config cfg;
     uint64_t mcause_max_irq{(FEAT&features_e::FEAT_CLIC)?4096:16};
     inline bool debug_mode_active() {return this->reg.PRIV&0x4;}
-    std::pair<std::function<mem_read_f>, std::function<mem_write_f>> replace_mem_access(std::function<mem_read_f> rd,
+    std::pair<std::function<mem_read_f>, std::function<mem_write_f>>
-                                                                                        std::function<mem_write_f> wr) {
+    replace_mem_access(std::function<mem_read_f> rd, std::function<mem_write_f> wr){
         std::pair<std::function<mem_read_f>, std::function<mem_write_f>> ret{hart_mem_rd_delegate, hart_mem_wr_delegate};
         hart_mem_rd_delegate = rd;
         hart_mem_wr_delegate = wr;
@@ -446,8 +448,7 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
         csr_rd_cb[addr] = &this_class::read_null;
         csr_wr_cb[addr] = &this_class::write_csr_reg;
     }
-    if(traits<BASE>::XLEN == 32)
+    if(traits<BASE>::XLEN==32) for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){
-        for(unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr) {
         csr_rd_cb[addr] = &this_class::read_null;
         csr_wr_cb[addr] = &this_class::write_csr_reg;
     }
@@ -458,8 +459,7 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
     for (unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr){
         csr_rd_cb[addr] = &this_class::read_null;
     }
-    if(traits<BASE>::XLEN == 32)
+    if(traits<BASE>::XLEN==32) for (unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr){
-        for(unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr) {
         csr_rd_cb[addr] = &this_class::read_null;
         //csr_wr_cb[addr] = &this_class::write_csr_reg;
     }
@@ -476,27 +476,20 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
     }
     // special handling & overrides
     csr_rd_cb[time] = &this_class::read_time;
-    if(traits<BASE>::XLEN == 32)
+    if(traits<BASE>::XLEN==32)  csr_rd_cb[timeh] = &this_class::read_time;
-        csr_rd_cb[timeh] = &this_class::read_time;
     csr_rd_cb[cycle] = &this_class::read_cycle;
-    if(traits<BASE>::XLEN == 32)
+    if(traits<BASE>::XLEN==32) csr_rd_cb[cycleh] = &this_class::read_cycle;
-        csr_rd_cb[cycleh] = &this_class::read_cycle;
     csr_rd_cb[instret] = &this_class::read_instret;
-    if(traits<BASE>::XLEN == 32)
+    if(traits<BASE>::XLEN==32) csr_rd_cb[instreth] = &this_class::read_instret;
-        csr_rd_cb[instreth] = &this_class::read_instret;
 
     csr_rd_cb[mcycle] = &this_class::read_cycle;
     csr_wr_cb[mcycle] = &this_class::write_cycle;
-    if(traits<BASE>::XLEN == 32)
+    if(traits<BASE>::XLEN==32) csr_rd_cb[mcycleh] = &this_class::read_cycle;
-        csr_rd_cb[mcycleh] = &this_class::read_cycle;
+    if(traits<BASE>::XLEN==32) csr_wr_cb[mcycleh] = &this_class::write_cycle;
-    if(traits<BASE>::XLEN == 32)
-        csr_wr_cb[mcycleh] = &this_class::write_cycle;
     csr_rd_cb[minstret] = &this_class::read_instret;
     csr_wr_cb[minstret] = &this_class::write_instret;
-    if(traits<BASE>::XLEN == 32)
+    if(traits<BASE>::XLEN==32) csr_rd_cb[minstreth] = &this_class::read_instret;
-        csr_rd_cb[minstreth] = &this_class::read_instret;
+    if(traits<BASE>::XLEN==32) csr_wr_cb[minstreth] = &this_class::write_instret;
-    if(traits<BASE>::XLEN == 32)
-        csr_wr_cb[minstreth] = &this_class::write_instret;
     csr_rd_cb[mstatus] = &this_class::read_status;
     csr_wr_cb[mstatus] = &this_class::write_status;
     csr_rd_cb[mcause] = &this_class::read_cause;
@@ -529,8 +522,7 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
         clic_cfg_reg=0x20;
         clic_mact_lvl = clic_mprev_lvl = (1<<(cfg.clic_int_ctl_bits)) - 1;
         csr[mintthresh] = (1<<(cfg.clic_int_ctl_bits)) - 1;
-        insert_mem_range(
+        insert_mem_range(cfg.clic_base, 0x5000UL,
-            cfg.clic_base, 0x5000UL,
                 [this](phys_addr_t addr, unsigned length, uint8_t * const data) { return read_clic(addr.val, length, data);},
                 [this](phys_addr_t addr, unsigned length, uint8_t const * const data) {return write_clic(addr.val, length, data);});
     }
@@ -558,8 +550,12 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
         csr_wr_cb[dcsr] = &this_class::write_dcsr_dcsr;
         csr_rd_cb[dcsr] = &this_class::read_dcsr_reg;
     }
-    hart_mem_rd_delegate = [this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status { return this->read_mem(a, l, d); };
+    hart_mem_rd_delegate = [this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status {
-    hart_mem_wr_delegate = [this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status { return this->write_mem(a, l, d); };
+        return this->read_mem(a, l, d);
+    };
+    hart_mem_wr_delegate = [this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status {
+        return this->write_mem(a, l, d);
+    };
 }
 
 template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m_p<BASE, FEAT>::load_file(std::string name, int type) {
@@ -568,37 +564,35 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
         std::array<char, 5> buf;
         auto n = fread(buf.data(), 1, 4, fp);
         fclose(fp);
-        if(n != 4)
+        if (n != 4) throw std::runtime_error("input file has insufficient size");
-            throw std::runtime_error("input file has insufficient size");
         buf[4] = 0;
         if (strcmp(buf.data() + 1, "ELF") == 0) {
             // Create elfio reader
             ELFIO::elfio reader;
             // Load ELF data
-            if(!reader.load(name))
+            if (!reader.load(name)) throw std::runtime_error("could not process elf file");
-                throw std::runtime_error("could not process elf file");
             // check elf properties
             if (reader.get_class() != ELFCLASS32)
-                if(sizeof(reg_t) == 4)
+                if (sizeof(reg_t) == 4) throw std::runtime_error("wrong elf class in file");
-                    throw std::runtime_error("wrong elf class in file");
+            if (reader.get_type() != ET_EXEC) throw std::runtime_error("wrong elf type in file");
-            if(reader.get_type() != ET_EXEC)
+            if (reader.get_machine() != EM_RISCV) throw std::runtime_error("wrong elf machine in file");
-                throw std::runtime_error("wrong elf type in file");
-            if(reader.get_machine() != EM_RISCV)
-                throw std::runtime_error("wrong elf machine in file");
             auto entry = reader.get_entry();
             for (const auto pseg : reader.segments) {
                 const auto fsize = pseg->get_file_size(); // 0x42c/0x0
                 const auto seg_data = pseg->get_data();
                 if (fsize > 0) {
-                    auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM,
+                    auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE,
-                                           pseg->get_physical_address(), fsize, reinterpret_cast<const uint8_t* const>(seg_data));
+                            traits<BASE>::MEM, pseg->get_physical_address(),
+                            fsize, reinterpret_cast<const uint8_t *const>(seg_data));
                     if (res != iss::Ok)
-                        LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address();
+                        LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex
+                                   << pseg->get_physical_address();
                 }
             }
             for(const auto sec : reader.sections) {
                 if(sec->get_name() == ".symtab") {
-                    if(SHT_SYMTAB == sec->get_type() || SHT_DYNSYM == sec->get_type()) {
+                    if ( SHT_SYMTAB == sec->get_type() ||
+                            SHT_DYNSYM == sec->get_type() ) {
                         ELFIO::symbol_section_accessor symbols( reader, sec );
                         auto sym_no = symbols.get_symbols_num();
                         std::string   name;
@@ -621,6 +615,7 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
                     tohost = sec->get_address();
                     fromhost = tohost + 0x40;
                 }
+
             }
             return std::make_pair(entry, true);
         }
@@ -633,9 +628,10 @@ template <typename BASE, features_e FEAT>
 inline void riscv_hart_m_p<BASE, FEAT>::insert_mem_range(uint64_t base, uint64_t size, std::function<mem_read_f> rd_f,
         std::function<mem_write_f> wr_fn) {
     std::tuple<uint64_t, uint64_t> entry{base, size};
-    auto it = std::upper_bound(
+    auto it = std::upper_bound( memfn_range.begin(), memfn_range.end(), entry,
-        memfn_range.begin(), memfn_range.end(), entry,
+            [](std::tuple<uint64_t, uint64_t> const& a, std::tuple<uint64_t, uint64_t> const& b){
-        [](std::tuple<uint64_t, uint64_t> const& a, std::tuple<uint64_t, uint64_t> const& b) { return std::get<0>(a) < std::get<0>(b); });
+        return std::get<0>(a)<std::get<0>(b);
+    });
     auto idx = std::distance(memfn_range.begin(), it);
     memfn_range.insert(it, entry);
     memfn_read.insert(std::begin(memfn_read)+idx, rd_f);
@@ -643,8 +639,8 @@ inline void riscv_hart_m_p<BASE, FEAT>::insert_mem_range(uint64_t base, uint64_t
 }
 
 template <typename BASE, features_e FEAT>
-iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr,
+iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const access_type access, const uint32_t space,
-                                             const unsigned length, uint8_t* const data) {
+        const uint64_t addr, const unsigned length, uint8_t *const data) {
 #ifndef NDEBUG
     if (access && iss::access_type::DEBUG) {
         LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
@@ -660,8 +656,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
             auto alignment = is_fetch(access)? (has_compressed()? 2 : 4) : length;
             if (unlikely(is_fetch(access) && (addr&(alignment-1)))) {
                 fault_data = addr;
-                if(is_debug(access))
+                if (is_debug(access)) throw trap_access(0, addr);
-                    throw trap_access(0, addr);
                 this->reg.trap_state = (1UL << 31); // issue trap 0
                 return iss::Err;
             }
@@ -671,11 +666,10 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
                     fault_data=addr;
                     return iss::Err;
                 }
-                phys_addr_t phys_addr{access, space, addr};
+                auto phys_addr = type==iss::address_type::PHYSICAL?phys_addr_t{access, space, addr}:BASE::v2p(iss::addr_t{access, type, space, addr});
                 auto res = iss::Err;
                 if(access != access_type::FETCH && memfn_range.size()){
-                    auto it =
+                    auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){
-                        std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a) {
                         return std::get<0>(a)<=phys_addr.val && (std::get<0>(a)+std::get<1>(a))>phys_addr.val;
                     });
                     if(it!=std::end(memfn_range)) {
@@ -686,7 +680,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
                 } else {
                     res = hart_mem_rd_delegate( phys_addr, length, data);
                 }
-                if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
+                if (unlikely(res != iss::Ok)){
                     this->reg.trap_state = (1UL << 31) | (5 << 16); // issue trap 5 (load access fault
                     fault_data=addr;
                 }
@@ -698,13 +692,11 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
             }
         } break;
         case traits<BASE>::CSR: {
-            if(length != sizeof(reg_t))
+            if (length != sizeof(reg_t)) return iss::Err;
-                return iss::Err;
             return read_csr(addr, *reinterpret_cast<reg_t *const>(data));
         } break;
         case traits<BASE>::FENCE: {
-            if((addr + length) > mem.size())
+            if ((addr + length) > mem.size()) return iss::Err;
-                return iss::Err;
             return iss::Ok;
         } break;
         case traits<BASE>::RES: {
@@ -727,26 +719,26 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
 }
 
 template <typename BASE, features_e FEAT>
-iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr,
+iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const access_type access, const uint32_t space,
-                                              const unsigned length, const uint8_t* const data) {
+        const uint64_t addr, const unsigned length, const uint8_t *const data) {
 #ifndef NDEBUG
     const char *prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
     switch (length) {
     case 8:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x"
+        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t *)&data[0] << std::dec
-                   << std::hex << addr;
+                   << ") @addr 0x" << std::hex << addr;
         break;
     case 4:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x"
+        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t *)&data[0] << std::dec
-                   << std::hex << addr;
+                   << ") @addr 0x" << std::hex << addr;
         break;
     case 2:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x"
+        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t *)&data[0] << std::dec
-                   << std::hex << addr;
+                   << ") @addr 0x" << std::hex << addr;
         break;
     case 1:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x"
+        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec
-                   << std::hex << addr;
+                   << ") @addr 0x" << std::hex << addr;
         break;
     default:
         LOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
@@ -757,8 +749,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
         case traits<BASE>::MEM: {
             if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) {
                 fault_data = addr;
-                if(access && iss::access_type::DEBUG)
+                if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                    throw trap_access(0, addr);
                 this->reg.trap_state = (1UL << 31); // issue trap 0
                 return iss::Err;
             }
@@ -768,11 +759,10 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
                     fault_data=addr;
                     return iss::Err;
                 }
-                phys_addr_t phys_addr{access, space, addr};
+                auto phys_addr = type==iss::address_type::PHYSICAL?phys_addr_t{access, space, addr}:BASE::v2p(iss::addr_t{access, type, space, addr});
                 auto res = iss::Err;
                 if(access != access_type::FETCH && memfn_range.size()){
-                    auto it =
+                    auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){
-                        std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a) {
                         return std::get<0>(a)<=phys_addr.val && (std::get<0>(a)+std::get<1>(a))>phys_addr.val;
                     });
                     if(it!=std::end(memfn_range)) {
@@ -783,7 +773,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
                 } else {
                     res = write_mem( phys_addr, length, data);
                 }
-                if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
+                if (unlikely(res != iss::Ok)) {
                     this->reg.trap_state = (1UL << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
                     fault_data=addr;
                 }
@@ -794,9 +784,9 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
                 return iss::Err;
             }
 
-            if((addr + length) > mem.size())
+            phys_addr_t paddr = BASE::v2p(iss::addr_t{access, type, space, addr});
-                return iss::Err;
+            if ((paddr.val + length) > mem.size()) return iss::Err;
-            switch(addr) {
+            switch (paddr.val) {
             case 0x10013000: // UART0 base, TXFIFO reg
             case 0x10023000: // UART1 base, TXFIFO reg
                 uart_buf << (char)data[0];
@@ -808,34 +798,30 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
                 }
                 return iss::Ok;
             case 0x10008000: { // HFROSC base, hfrosccfg reg
-                auto& p = mem(addr / mem.page_size);
+                auto &p = mem(paddr.val / mem.page_size);
-                auto offs = addr & mem.page_addr_mask;
+                auto offs = paddr.val & mem.page_addr_mask;
                 std::copy(data, data + length, p.data() + offs);
                 auto &x = *(p.data() + offs + 3);
-                if(x & 0x40)
+                if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1
-                    x |= 0x80; // hfroscrdy = 1 if hfroscen==1
                 return iss::Ok;
             }
             case 0x10008008: { // HFROSC base, pllcfg reg
-                auto& p = mem(addr / mem.page_size);
+                auto &p = mem(paddr.val / mem.page_size);
-                auto offs = addr & mem.page_addr_mask;
+                auto offs = paddr.val & mem.page_addr_mask;
                 std::copy(data, data + length, p.data() + offs);
                 auto &x = *(p.data() + offs + 3);
                 x |= 0x80; // set pll lock upon writing
                 return iss::Ok;
             } break;
-            default: {
+            default: {}
-            }
             }
         } break;
         case traits<BASE>::CSR: {
-            if(length != sizeof(reg_t))
+            if (length != sizeof(reg_t)) return iss::Err;
-                return iss::Err;
             return write_csr(addr, *reinterpret_cast<const reg_t *>(data));
         } break;
         case traits<BASE>::FENCE: {
-            if((addr + length) > mem.size())
+            if ((addr + length) > mem.size()) return iss::Err;
-                return iss::Err;
             switch (addr) {
             case 2:
             case 3: {
@@ -860,8 +846,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
 }
 
 template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_csr(unsigned addr, reg_t &val) {
-    if(addr >= csr.size())
+    if (addr >= csr.size()) return iss::Err;
-        return iss::Err;
     auto req_priv_lvl = (addr >> 8) & 0x3;
     if (this->reg.PRIV < req_priv_lvl) // not having required privileges
         throw illegal_instruction_fault(this->fault_data);
@@ -872,8 +857,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
 }
 
 template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_csr(unsigned addr, reg_t val) {
-    if(addr >= csr.size())
+    if (addr >= csr.size()) return iss::Err;
-        return iss::Err;
     auto req_priv_lvl = (addr >> 8) & 0x3;
     if (this->reg.PRIV < req_priv_lvl) // not having required privileges
         throw illegal_instruction_fault(this->fault_data);
@@ -952,8 +936,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
     if (addr == time) {
         val = static_cast<reg_t>(time_val);
     } else if (addr == timeh) {
-        if(sizeof(typename traits<BASE>::reg_t) != 4)
+        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
-            return iss::Err;
         val = static_cast<reg_t>(time_val >> 32);
     }
     return iss::Ok;
@@ -1068,17 +1051,20 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
     return iss::Ok;
 }
 
-template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_intstatus(unsigned addr, reg_t& val) {
+template<typename BASE, features_e FEAT>
+iss::status riscv_hart_m_p<BASE, FEAT>::read_intstatus(unsigned addr, reg_t& val) {
 	val = (clic_mact_lvl&0xff) <<24;
     return iss::Ok;
 }
 
-template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_intthresh(unsigned addr, reg_t val) {
+template<typename BASE, features_e FEAT>
+iss::status riscv_hart_m_p<BASE, FEAT>::write_intthresh(unsigned addr, reg_t val) {
     csr[addr]= (val &0xff) | (1<<(cfg.clic_int_ctl_bits)) - 1;
     return iss::Ok;
 }
 
-template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_xtvt(unsigned addr, reg_t val) {
+template<typename BASE, features_e FEAT>
+iss::status riscv_hart_m_p<BASE, FEAT>::write_xtvt(unsigned addr, reg_t val) {
     csr[addr]= val & ~0x3fULL;
     return iss::Ok;
 }
@@ -1110,9 +1096,10 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned le
         std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
         // tohost handling in case of riscv-test
         if (paddr.access && iss::access_type::FUNC) {
-            auto tohost_upper =
+            auto tohost_upper = (traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4)) ||
-                (traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4)) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
+                                (traits<BASE>::XLEN == 64 && paddr.val == tohost);
-            auto tohost_lower = (traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
+            auto tohost_lower =
+                (traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
             if (tohost_lower || tohost_upper) {
                 uint64_t hostvar = *reinterpret_cast<uint64_t *>(p.data() + (tohost & mem.page_addr_mask));
                 if (tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) {
@@ -1127,10 +1114,8 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned le
                         }
                         this->reg.trap_state=std::numeric_limits<uint32_t>::max();
                         this->interrupt_sim=hostvar;
-#ifndef WITH_TCC
-                        throw(iss::simulation_stopped(hostvar));
-#endif
                         break;
+                        //throw(iss::simulation_stopped(hostvar));
                     case 0x0101: {
                         char c = static_cast<char>(hostvar & 0xff);
                         if (c == '\n' || c == 0) {
@@ -1145,7 +1130,8 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned le
                     }
                 } else if (tohost_lower)
                     to_host_wr_cnt++;
-            } else if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
+            } else if ((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) ||
+                       (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
                 uint64_t fhostvar = *reinterpret_cast<uint64_t *>(p.data() + (fromhost & mem.page_addr_mask));
                 *reinterpret_cast<uint64_t *>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
             }
@@ -1159,18 +1145,15 @@ template <typename BASE, features_e FEAT>
 iss::status riscv_hart_m_p<BASE, FEAT>::read_clic(uint64_t addr, unsigned length, uint8_t *const data) {
     if(addr==cfg.clic_base) { // cliccfg
         *data=clic_cfg_reg;
-        for(auto i = 1; i < length; ++i)
+        for(auto i=1; i<length; ++i) *(data+i)=0;
-            *(data + i) = 0;
     } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
         auto offset = ((addr&0x7fff)-0x40)/4;
         read_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
-    } else if(addr >= (cfg.clic_base + 0x1000) &&
+    } else if(addr>=(cfg.clic_base+0x1000) && (addr+length)<=(cfg.clic_base+0x1000+cfg.clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
-              (addr + length) <= (cfg.clic_base + 0x1000 + cfg.clic_num_irq * 4)) { // clicintip/clicintie/clicintattr/clicintctl
         auto offset = ((addr&0x7fff)-0x1000)/4;
         read_reg_uint32(addr, clic_int_reg[offset].raw, data, length);
     } else {
-        for(auto i = 0U; i < length; ++i)
+        for(auto i = 0U; i<length; ++i) *(data+i)=0;
-            *(data + i) = 0;
     }
     return iss::Ok;
 }
@@ -1182,8 +1165,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write_clic(uint64_t addr, unsigned lengt
     } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
         auto offset = ((addr&0x7fff)-0x40)/4;
         write_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
-    } else if(addr >= (cfg.clic_base + 0x1000) &&
+    } else if(addr>=(cfg.clic_base+0x1000) && (addr+length)<=(cfg.clic_base+0x1000+cfg.clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
-              (addr + length) <= (cfg.clic_base + 0x1000 + cfg.clic_num_irq * 4)) { // clicintip/clicintie/clicintattr/clicintctl
         auto offset = ((addr&0x7fff)-0x1000)/4;
         write_reg_uint32(addr, clic_int_reg[offset].raw, data, length);
         clic_int_reg[offset].raw &= 0xf0c70101; // clicIntCtlBits->0xf0, clicintattr->0xc7, clicintie->0x1, clicintip->0x1
@@ -1227,8 +1209,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
     // calculate effective privilege level
     unsigned new_priv = PRIV_M;
     if (trap_id == 0) { // exception
-        if(cause == 11)
+        if (cause == 11) cause = 0x8 + PRIV_M; // adjust environment call cause
-            cause = 0x8 + PRIV_M; // adjust environment call cause
         // store ret addr in xepc register
         csr[mepc] = static_cast<reg_t>(addr) & get_pc_mask(); // store actual address instruction of exception
         /*
@@ -1290,8 +1271,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
     } else {
         // bits in mtvec
         this->reg.NEXT_PC = xtvec & ~0x3UL;
-        if((xtvec & 0x1) == 1 && trap_id != 0)
+        if ((xtvec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
-            this->reg.NEXT_PC += 4 * cause;
     }
     // reset trap state
     this->reg.PRIV = new_priv;
@@ -1303,8 +1283,8 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
     sprintf(buffer.data(), "0x%016lx", addr);
 #endif
     if((flags&0xffffffff) != 0xffffffff)
-        CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '" << (trap_id ? irq_str[cause] : trap_str[cause]) << "' ("
+    CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '"
-                           << cause << ")"
+                       << (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << cause << ")"
                        << " at address " << buffer.data() << " occurred";
     return this->reg.NEXT_PC;
 }

src/iss/arch/riscv_hart_msu_vp.h

@@ -35,22 +35,22 @@
 #ifndef _RISCV_HART_MSU_VP_H
 #define _RISCV_HART_MSU_VP_H
 
+#include "riscv_hart_common.h"
 #include "iss/arch/traits.h"
 #include "iss/instrumentation_if.h"
 #include "iss/log_categories.h"
 #include "iss/vm_if.h"
-#include "riscv_hart_common.h"
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
 #endif
 #include <array>
 #include <elfio/elfio.hpp>
 #include <fmt/format.h>
-#include <functional>
 #include <iomanip>
 #include <sstream>
 #include <type_traits>
 #include <unordered_map>
+#include <functional>
 #include <util/bit_field.h>
 #include <util/ities.h>
 #include <util/sparse_array.h>
@@ -86,11 +86,10 @@ protected:
                                               "Load page fault",                // d
                                               "Reserved",                       // e
                                               "Store/AMO page fault"}};
-    const std::array<const char*, 12> irq_str = {{"User software interrupt", "Supervisor software interrupt", "Reserved",
+    const std::array<const char *, 12> irq_str = {
-                                                  "Machine software interrupt", "User timer interrupt", "Supervisor timer interrupt",
+        {"User software interrupt", "Supervisor software interrupt", "Reserved", "Machine software interrupt",
-                                                  "Reserved", "Machine timer interrupt", "User external interrupt",
+         "User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt",
-                                                  "Supervisor external interrupt", "Reserved", "Machine external interrupt"}};
+         "User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}};
-
 public:
     using core = BASE;
     using this_class = riscv_hart_msu_vp<BASE>;
@@ -108,8 +107,7 @@ public:
     template <typename T> class hart_state<T, typename std::enable_if<std::is_same<T, uint32_t>::value>::type> {
     public:
         BEGIN_BF_DECL(mstatus_t, T);
-        // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR
+        // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11)))
-        // XS==11)))
         BF_FIELD(SD, 31, 1);
         // Trap SRET
         BF_FIELD(TSR, 22, 1);
@@ -123,8 +121,7 @@ public:
         BF_FIELD(SUM, 18, 1);
         // Modify PRiVilege
         BF_FIELD(MPRV, 17, 1);
-        // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None
+        // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None dirty, some clean/Some dirty
-        // dirty, some clean/Some dirty
         BF_FIELD(XS, 15, 2);
         // floating-point unit status Off/Initial/Clean/Dirty
         BF_FIELD(FS, 13, 2);
@@ -165,27 +162,20 @@ public:
             return priv_lvl == PRIV_U ? 0x80000011UL : priv_lvl == PRIV_S ? 0x800de133UL : 0x807ff9ddUL;
 #else
             switch (priv_lvl) {
-            case PRIV_U:
+            case PRIV_U: return 0x80000011UL; // 0b1000 0000 0000 0000 0000 0000 0001 0001
-                return 0x80000011UL; // 0b1000 0000 0000 0000 0000 0000 0001 0001
+            case PRIV_S: return 0x800de133UL; // 0b1000 0000 0000 1101 1110 0001 0011 0011
-            case PRIV_S:
+            default:     return 0x807ff9ddUL; // 0b1000 0000 0111 1111 1111 1001 1011 1011
-                return 0x800de133UL; // 0b1000 0000 0000 1101 1110 0001 0011 0011
-            default:
-                return 0x807ff9ddUL; // 0b1000 0000 0111 1111 1111 1001 1011 1011
             }
 #endif
         }
 
         static inline vm_info decode_vm_info(uint32_t state, T sptbr) {
-            if(state == PRIV_M)
+            if (state == PRIV_M) return {0, 0, 0, 0};
-                return {0, 0, 0, 0};
             if (state <= PRIV_S)
                 switch (bit_sub<31, 1>(sptbr)) {
-                case 0:
+                case 0:  return {0, 0, 0, 0}; // off
-                    return {0, 0, 0, 0}; // off
+                case 1:  return {2, 10, 4, bit_sub<0, 22>(sptbr) << PGSHIFT}; // SV32
-                case 1:
+                default: abort();
-                    return {2, 10, 4, bit_sub<0, 22>(sptbr) << PGSHIFT}; // SV32
-                default:
-                    abort();
                 }
             abort();
             return {0, 0, 0, 0}; // dummy
@@ -195,8 +185,7 @@ public:
     template <typename T> class hart_state<T, typename std::enable_if<std::is_same<T, uint64_t>::value>::type> {
     public:
         BEGIN_BF_DECL(mstatus_t, T);
-        // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR
+        // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11)))
-        // XS==11)))
         BF_FIELD(SD, 63, 1);
         // value of XLEN for S-mode
         BF_FIELD(SXL, 34, 2);
@@ -214,8 +203,7 @@ public:
         BF_FIELD(SUM, 18, 1);
         // Modify PRiVilege
         BF_FIELD(MPRV, 17, 1);
-        // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None
+        // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None dirty, some clean/Some dirty
-        // dirty, some clean/Some dirty
         BF_FIELD(XS, 15, 2);
         // floating-point unit status Off/Initial/Clean/Dirty
         BF_FIELD(FS, 13, 2);
@@ -261,36 +249,23 @@ public:
         static constexpr T get_mask(unsigned priv_lvl) {
             uint64_t ret;
             switch (priv_lvl) {
-            case PRIV_U:
+            case PRIV_U: ret = 0x8000000f00000011ULL;break; // 0b1...0 1111 0000 0000 0111 1111 1111 1001 1011 1011
-                ret = 0x8000000f00000011ULL;
+            case PRIV_S: ret = 0x8000000f000de133ULL;break; // 0b1...0 0011 0000 0000 0000 1101 1110 0001 0011 0011
-                break; // 0b1...0 1111 0000 0000 0111 1111 1111 1001 1011 1011
+            default:     ret = 0x8000000f007ff9ddULL;break; // 0b1...0 1111 0000 0000 0111 1111 1111 1001 1011 1011
-            case PRIV_S:
-                ret = 0x8000000f000de133ULL;
-                break; // 0b1...0 0011 0000 0000 0000 1101 1110 0001 0011 0011
-            default:
-                ret = 0x8000000f007ff9ddULL;
-                break; // 0b1...0 1111 0000 0000 0111 1111 1111 1001 1011 1011
             }
             return ret;
         }
 
         static inline vm_info decode_vm_info(uint32_t state, T sptbr) {
-            if(state == PRIV_M)
+            if (state == PRIV_M) return {0, 0, 0, 0};
-                return {0, 0, 0, 0};
             if (state <= PRIV_S)
                 switch (bit_sub<60, 4>(sptbr)) {
-                case 0:
+                case 0:  return {0, 0, 0, 0}; // off
-                    return {0, 0, 0, 0}; // off
+                case 8:  return {3, 9, 8, bit_sub<0, 44>(sptbr) << PGSHIFT};// SV39
-                case 8:
+                case 9:  return {4, 9, 8, bit_sub<0, 44>(sptbr) << PGSHIFT};// SV48
-                    return {3, 9, 8, bit_sub<0, 44>(sptbr) << PGSHIFT}; // SV39
+                case 10: return {5, 9, 8, bit_sub<0, 44>(sptbr) << PGSHIFT};// SV57
-                case 9:
+                case 11: return {6, 9, 8, bit_sub<0, 44>(sptbr) << PGSHIFT};// SV64
-                    return {4, 9, 8, bit_sub<0, 44>(sptbr) << PGSHIFT}; // SV48
+                default: abort();
-                case 10:
-                    return {5, 9, 8, bit_sub<0, 44>(sptbr) << PGSHIFT}; // SV57
-                case 11:
-                    return {6, 9, 8, bit_sub<0, 44>(sptbr) << PGSHIFT}; // SV64
-                default:
-                    abort();
                 }
             abort();
             return {0, 0, 0, 0}; // dummy
@@ -311,7 +286,7 @@ public:
         return m[mode];
     }
 
-    riscv_hart_msu_vp(feature_config cfg = feature_config{});
+    riscv_hart_msu_vp();
     virtual ~riscv_hart_msu_vp() = default;
 
     void reset(uint64_t address) override;
@@ -320,10 +295,10 @@ public:
 
     phys_addr_t virt2phys(const iss::addr_t &addr) override;
 
-    iss::status read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length,
+    iss::status read(const address_type type, const access_type access, const uint32_t space,
-                     uint8_t* const data) override;
+            const uint64_t addr, const unsigned length, uint8_t *const data) override;
-    iss::status write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length,
+    iss::status write(const address_type type, const access_type access, const uint32_t space,
-                      const uint8_t* const data) override;
+            const uint64_t addr, const unsigned length, const uint8_t *const data) override;
 
     uint64_t enter_trap(uint64_t flags) override { return riscv_hart_msu_vp::enter_trap(flags, fault_data, fault_data); }
     uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
@@ -331,16 +306,19 @@ public:
     void wait_until(uint64_t flags) override;
 
     void disass_output(uint64_t pc, const std::string instr) override {
-        CLOG(INFO, disass) << fmt::format("0x{:016x}    {:40} [p:{};s:0x{:x};c:{}]", pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus,
+        CLOG(INFO, disass) << fmt::format("0x{:016x}    {:40} [p:{};s:0x{:x};c:{}]",
-                                          this->reg.icount + cycle_offset);
+                pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus, this->reg.icount + cycle_offset);
     };
 
     iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
 
-    void set_csr(unsigned addr, reg_t val) { csr[addr & csr.page_addr_mask] = val; }
+    void set_csr(unsigned addr, reg_t val){
-
+        csr[addr & csr.page_addr_mask] = val;
-    void set_irq_num(unsigned i) { mcause_max_irq = 1 << util::ilog2(i); }
+    }
 
+    void set_irq_num(unsigned i) {
+        mcause_max_irq=1<<util::ilog2(i);
+    }
 protected:
     struct riscv_instrumentation_if : public iss::instrumentation_if {
 
@@ -353,9 +331,9 @@ protected:
          */
         const std::string core_type_name() const override { return traits<BASE>::core_type; }
 
-        uint64_t get_pc() override { return arch.reg.PC; }
+        uint64_t get_pc() override { return arch.reg.PC; };
 
-        uint64_t get_next_pc() override { return arch.reg.NEXT_PC; }
+        uint64_t get_next_pc() override { return arch.reg.NEXT_PC; };
 
         uint64_t get_instr_word() override { return arch.reg.instruction; }
 
@@ -365,13 +343,9 @@ protected:
 
         uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }
 
-        void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; }
+        void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
 
-        bool is_branch_taken() override { return arch.reg.last_branch; }
+        bool is_branch_taken() override { return arch.reg.last_branch; };
-
-        unsigned get_reg_num() override { return traits<BASE>::NUM_REGS; }
-
-        unsigned get_reg_size(unsigned num) override { return traits<BASE>::reg_bit_widths[num]; }
 
         riscv_hart_msu_vp<BASE> &arch;
     };
@@ -440,8 +414,12 @@ protected:
     virtual iss::status read_custom_csr_reg(unsigned addr, reg_t &val) {return iss::status::Err;};
     virtual iss::status write_custom_csr_reg(unsigned addr, reg_t val) {return iss::status::Err;};
 
-    void register_custom_csr_rd(unsigned addr) { csr_rd_cb[addr] = &this_class::read_custom_csr_reg; }
+    void register_custom_csr_rd(unsigned addr){
-    void register_custom_csr_wr(unsigned addr) { csr_wr_cb[addr] = &this_class::write_custom_csr_reg; }
+        csr_rd_cb[addr] = &this_class::read_custom_csr_reg;
+    }
+    void register_custom_csr_wr(unsigned addr){
+        csr_wr_cb[addr] = &this_class::write_custom_csr_reg;
+    }
 
     reg_t mhartid_reg{0x0};
 
@@ -452,7 +430,6 @@ template <typename BASE>
 riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
 : state()
 , instr_if(*this) {
-    this->_has_mmu = true;
     // reset values
     csr[misa] = traits<BASE>::MISA_VAL;
     csr[mvendorid] = 0x669;
@@ -480,36 +457,32 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
         //csr_wr_cb[addr] = &this_class::write_csr_reg;
     }
     // common regs
-    const std::array<unsigned, 22> addrs{{misa,  mvendorid, marchid,  mimpid, mepc,     mtvec,   mscratch, mcause,
+    const std::array<unsigned, 22> addrs{{
-                                          mtval, mscratch,  sepc,     stvec,  sscratch, scause,  stval,    sscratch,
+        misa, mvendorid, marchid, mimpid,
-                                          uepc,  utvec,     uscratch, ucause, utval,    uscratch}};
+        mepc, mtvec, mscratch, mcause, mtval, mscratch,
+        sepc, stvec, sscratch, scause, stval, sscratch,
+        uepc, utvec, uscratch, ucause, utval, uscratch
+    }};
     for(auto addr: addrs) {
         csr_rd_cb[addr] = &this_class::read_csr_reg;
         csr_wr_cb[addr] = &this_class::write_csr_reg;
     }
     // special handling & overrides
     csr_rd_cb[time] = &this_class::read_time;
-    if(traits<BASE>::XLEN == 32)
+    if(traits<BASE>::XLEN==32)  csr_rd_cb[timeh] = &this_class::read_time;
-        csr_rd_cb[timeh] = &this_class::read_time;
     csr_rd_cb[cycle] = &this_class::read_cycle;
-    if(traits<BASE>::XLEN == 32)
+    if(traits<BASE>::XLEN==32) csr_rd_cb[cycleh] = &this_class::read_cycle;
-        csr_rd_cb[cycleh] = &this_class::read_cycle;
     csr_rd_cb[instret] = &this_class::read_instret;
-    if(traits<BASE>::XLEN == 32)
+    if(traits<BASE>::XLEN==32) csr_rd_cb[instreth] = &this_class::read_instret;
-        csr_rd_cb[instreth] = &this_class::read_instret;
 
     csr_rd_cb[mcycle] = &this_class::read_cycle;
     csr_wr_cb[mcycle] = &this_class::write_cycle;
-    if(traits<BASE>::XLEN == 32)
+    if(traits<BASE>::XLEN==32) csr_rd_cb[mcycleh] = &this_class::read_cycle;
-        csr_rd_cb[mcycleh] = &this_class::read_cycle;
+    if(traits<BASE>::XLEN==32) csr_wr_cb[mcycleh] = &this_class::write_cycle;
-    if(traits<BASE>::XLEN == 32)
-        csr_wr_cb[mcycleh] = &this_class::write_cycle;
     csr_rd_cb[minstret] = &this_class::read_instret;
     csr_wr_cb[minstret] = &this_class::write_instret;
-    if(traits<BASE>::XLEN == 32)
+    if(traits<BASE>::XLEN==32) csr_rd_cb[minstreth] = &this_class::read_instret;
-        csr_rd_cb[minstreth] = &this_class::read_instret;
+    if(traits<BASE>::XLEN==32) csr_wr_cb[minstreth] = &this_class::write_instret;
-    if(traits<BASE>::XLEN == 32)
-        csr_wr_cb[minstreth] = &this_class::write_instret;
     csr_rd_cb[mstatus] = &this_class::read_status;
     csr_wr_cb[mstatus] = &this_class::write_status;
     csr_wr_cb[mcause] = &this_class::write_cause;
@@ -560,37 +533,35 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_msu_vp<BASE>::load
         std::array<char, 5> buf;
         auto n = fread(buf.data(), 1, 4, fp);
         fclose(fp);
-        if(n != 4)
+        if (n != 4) throw std::runtime_error("input file has insufficient size");
-            throw std::runtime_error("input file has insufficient size");
         buf[4] = 0;
         if (strcmp(buf.data() + 1, "ELF") == 0) {
             // Create elfio reader
             ELFIO::elfio reader;
             // Load ELF data
-            if(!reader.load(name))
+            if (!reader.load(name)) throw std::runtime_error("could not process elf file");
-                throw std::runtime_error("could not process elf file");
             // check elf properties
             if (reader.get_class() != ELFCLASS32)
-                if(sizeof(reg_t) == 4)
+                if (sizeof(reg_t) == 4) throw std::runtime_error("wrong elf class in file");
-                    throw std::runtime_error("wrong elf class in file");
+            if (reader.get_type() != ET_EXEC) throw std::runtime_error("wrong elf type in file");
-            if(reader.get_type() != ET_EXEC)
+            if (reader.get_machine() != EM_RISCV) throw std::runtime_error("wrong elf machine in file");
-                throw std::runtime_error("wrong elf type in file");
-            if(reader.get_machine() != EM_RISCV)
-                throw std::runtime_error("wrong elf machine in file");
             auto entry = reader.get_entry();
             for (const auto pseg : reader.segments) {
                 const auto fsize = pseg->get_file_size(); // 0x42c/0x0
                 const auto seg_data = pseg->get_data();
                 if (fsize > 0) {
-                    auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM,
+                    auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE,
-                                           pseg->get_physical_address(), fsize, reinterpret_cast<const uint8_t* const>(seg_data));
+                            traits<BASE>::MEM, pseg->get_physical_address(),
+                            fsize, reinterpret_cast<const uint8_t *const>(seg_data));
                     if (res != iss::Ok)
-                        LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address();
+                        LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex
+                                   << pseg->get_physical_address();
                 }
             }
             for(const auto sec : reader.sections) {
                 if(sec->get_name() == ".symtab") {
-                    if(SHT_SYMTAB == sec->get_type() || SHT_DYNSYM == sec->get_type()) {
+                    if ( SHT_SYMTAB == sec->get_type() ||
+                            SHT_DYNSYM == sec->get_type() ) {
                         ELFIO::symbol_section_accessor symbols( reader, sec );
                         auto sym_no = symbols.get_symbols_num();
                         std::string   name;
@@ -613,6 +584,7 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_msu_vp<BASE>::load
                     tohost = sec->get_address();
                     fromhost = tohost + 0x40;
                 }
+
             }
             return std::make_pair(entry, true);
         }
@@ -622,8 +594,8 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_msu_vp<BASE>::load
 }
 
 template <typename BASE>
-iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr,
+iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_type access, const uint32_t space,
-                                          const unsigned length, uint8_t* const data) {
+        const uint64_t addr, const unsigned length, uint8_t *const data) {
 #ifndef NDEBUG
     if (access && iss::access_type::DEBUG) {
         LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
@@ -639,8 +611,7 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
             auto alignment = is_fetch(access)? (traits<BASE>::MISA_VAL&0x100? 2 : 4) : length;
             if (unlikely(is_fetch(access) && (addr&(alignment-1)))) {
                 fault_data = addr;
-                if(access && iss::access_type::DEBUG)
+                if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                    throw trap_access(0, addr);
                 this->reg.trap_state = (1 << 31); // issue trap 0
                 return iss::Err;
             }
@@ -661,8 +632,10 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
                         return res;
                     }
                 }
-                auto res = read_mem(BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
+                auto res = type==iss::address_type::PHYSICAL?
-                if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
+                        read_mem( BASE::v2p(phys_addr_t{access, space, addr}), length, data):
+                        read_mem( BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
+                if (unlikely(res != iss::Ok)){
                 	this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
                     fault_data=addr;
                 }
@@ -674,13 +647,11 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
             }
         } break;
         case traits<BASE>::CSR: {
-            if(length != sizeof(reg_t))
+            if (length != sizeof(reg_t)) return iss::Err;
-                return iss::Err;
             return read_csr(addr, *reinterpret_cast<reg_t *const>(data));
         } break;
         case traits<BASE>::FENCE: {
-            if((addr + length) > mem.size())
+            if ((addr + length) > mem.size()) return iss::Err;
-                return iss::Err;
             switch (addr) {
             case 2:   // SFENCE:VMA lower
             case 3: { // SFENCE:VMA upper
@@ -714,26 +685,26 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
 }
 
 template <typename BASE>
-iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr,
+iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access_type access, const uint32_t space,
-                                           const unsigned length, const uint8_t* const data) {
+        const uint64_t addr, const unsigned length, const uint8_t *const data) {
 #ifndef NDEBUG
     const char *prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
     switch (length) {
     case 8:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x"
+        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t *)&data[0] << std::dec
-                   << std::hex << addr;
+                   << ") @addr 0x" << std::hex << addr;
         break;
     case 4:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x"
+        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t *)&data[0] << std::dec
-                   << std::hex << addr;
+                   << ") @addr 0x" << std::hex << addr;
         break;
     case 2:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x"
+        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t *)&data[0] << std::dec
-                   << std::hex << addr;
+                   << ") @addr 0x" << std::hex << addr;
         break;
     case 1:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x"
+        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec
-                   << std::hex << addr;
+                   << ") @addr 0x" << std::hex << addr;
         break;
     default:
         LOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
@@ -744,12 +715,10 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
         case traits<BASE>::MEM: {
             if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) {
                 fault_data = addr;
-                if(access && iss::access_type::DEBUG)
+                if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                    throw trap_access(0, addr);
                 this->reg.trap_state = (1 << 31); // issue trap 0
                 return iss::Err;
             }
-            phys_addr_t paddr = BASE::v2p(iss::addr_t{access, type, space, addr});
             try {
                 if (unlikely((addr & ~PGMASK) != ((addr + length - 1) & ~PGMASK))) { // we may cross a page boundary
                     vm_info vm = hart_state_type::decode_vm_info(this->reg.PRIV, state.satp);
@@ -762,8 +731,10 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
                         return res;
                     }
                 }
-                auto res = write_mem(paddr, length, data);
+                auto res = type==iss::address_type::PHYSICAL?
-                if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
+                        write_mem(phys_addr_t{access, space, addr}, length, data):
+                        write_mem(BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
+                if (unlikely(res != iss::Ok)) {
                     this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault)
                     fault_data=addr;
                 }
@@ -774,8 +745,8 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
                 return iss::Err;
             }
 
-            if((paddr.val + length) > mem.size())
+            phys_addr_t paddr = BASE::v2p(iss::addr_t{access, type, space, addr});
-                return iss::Err;
+            if ((paddr.val + length) > mem.size()) return iss::Err;
             switch (paddr.val) {
             case 0x10013000: // UART0 base, TXFIFO reg
             case 0x10023000: // UART1 base, TXFIFO reg
@@ -792,8 +763,7 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
                 auto offs = paddr.val & mem.page_addr_mask;
                 std::copy(data, data + length, p.data() + offs);
                 auto &x = *(p.data() + offs + 3);
-                if(x & 0x40)
+                if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1
-                    x |= 0x80; // hfroscrdy = 1 if hfroscen==1
                 return iss::Ok;
             }
             case 0x10008008: { // HFROSC base, pllcfg reg
@@ -804,18 +774,15 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
                 x |= 0x80; // set pll lock upon writing
                 return iss::Ok;
             } break;
-            default: {
+            default: {}
-            }
             }
         } break;
         case traits<BASE>::CSR: {
-            if(length != sizeof(reg_t))
+            if (length != sizeof(reg_t)) return iss::Err;
-                return iss::Err;
             return write_csr(addr, *reinterpret_cast<const reg_t *>(data));
         } break;
         case traits<BASE>::FENCE: {
-            if((addr + length) > mem.size())
+            if ((addr + length) > mem.size()) return iss::Err;
-                return iss::Err;
             switch (addr) {
             case 2:
             case 3: {
@@ -845,8 +812,7 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
 }
 
 template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_csr(unsigned addr, reg_t &val) {
-    if(addr >= csr.size())
+    if (addr >= csr.size()) return iss::Err;
-        return iss::Err;
     auto req_priv_lvl = (addr >> 8) & 0x3;
     if (this->reg.PRIV < req_priv_lvl) // not having required privileges
     	throw illegal_instruction_fault(this->fault_data);
@@ -857,8 +823,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_csr(unsigned
 }
 
 template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_csr(unsigned addr, reg_t val) {
-    if(addr >= csr.size())
+    if (addr >= csr.size()) return iss::Err;
-        return iss::Err;
     auto req_priv_lvl = (addr >> 8) & 0x3;
     if (this->reg.PRIV < req_priv_lvl) // not having required privileges
         throw illegal_instruction_fault(this->fault_data);
@@ -890,8 +855,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_cycle(unsigne
     if (addr == mcycle) {
         val = static_cast<reg_t>(cycle_val);
     } else if (addr == mcycleh) {
-        if(sizeof(typename traits<BASE>::reg_t) != 4)
+        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
-            return iss::Err;
         val = static_cast<reg_t>(cycle_val >> 32);
     }
     return iss::Ok;
@@ -939,8 +903,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_time(unsigned
     if (addr == time) {
         val = static_cast<reg_t>(time_val);
     } else if (addr == timeh) {
-        if(sizeof(typename traits<BASE>::reg_t) != 4)
+        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
-            return iss::Err;
         val = static_cast<reg_t>(time_val >> 32);
     }
     return iss::Ok;
@@ -972,10 +935,8 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_cause(unsign
 
 template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_ie(unsigned addr, reg_t &val) {
     val = csr[mie];
-    if(addr < mie)
+    if (addr < mie) val &= csr[mideleg];
-        val &= csr[mideleg];
+    if (addr < sie) val &= csr[sideleg];
-    if(addr < sie)
-        val &= csr[sideleg];
     return iss::Ok;
 }
 
@@ -994,10 +955,8 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_ie(unsigned
 
 template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_ip(unsigned addr, reg_t &val) {
     val = csr[mip];
-    if(addr < mip)
+    if (addr < mip) val &= csr[mideleg];
-        val &= csr[mideleg];
+    if (addr < sip) val &= csr[sideleg];
-    if(addr < sip)
-        val &= csr[sideleg];
     return iss::Ok;
 }
 
@@ -1062,7 +1021,8 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_fcsr(unsigne
     return iss::Ok;
 }
 
-template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_mem(phys_addr_t paddr, unsigned length, uint8_t* const data) {
+template <typename BASE>
+iss::status riscv_hart_msu_vp<BASE>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
     switch (paddr.val) {
     default: {
         for(auto offs=0U; offs<length; ++offs) {
@@ -1073,7 +1033,8 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_mem(phys_addr
     return iss::Ok;
 }
 
-template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) {
+template <typename BASE>
+iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
     switch (paddr.val) {
     case 0xFFFF0000: // UART0 base, TXFIFO reg
         if (((char)data[0]) == '\n' || data[0] == 0) {
@@ -1087,9 +1048,10 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_add
         std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
         // tohost handling in case of riscv-test
         if (paddr.access && iss::access_type::FUNC) {
-            auto tohost_upper =
+            auto tohost_upper = (traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4)) ||
-                (traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4)) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
+                                (traits<BASE>::XLEN == 64 && paddr.val == tohost);
-            auto tohost_lower = (traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
+            auto tohost_lower =
+                (traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
             if (tohost_lower || tohost_upper) {
                 uint64_t hostvar = *reinterpret_cast<uint64_t *>(p.data() + (tohost & mem.page_addr_mask));
                 if (tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) {
@@ -1120,7 +1082,8 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_add
                     }
                 } else if (tohost_lower)
                     to_host_wr_cnt++;
-            } else if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
+            } else if ((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) ||
+                       (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
                 uint64_t fhostvar = *reinterpret_cast<uint64_t *>(p.data() + (fromhost & mem.page_addr_mask));
                 *reinterpret_cast<uint64_t *>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
             }
@@ -1169,13 +1132,13 @@ template <typename BASE> void riscv_hart_msu_vp<BASE>::check_interrupt() {
     }
     if (enabled_interrupts != 0) {
         int res = 0;
-        while((enabled_interrupts & 1) == 0)
+        while ((enabled_interrupts & 1) == 0) enabled_interrupts >>= 1, res++;
-            enabled_interrupts >>= 1, res++;
         this->reg.pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id
     }
 }
 
-template <typename BASE> typename riscv_hart_msu_vp<BASE>::phys_addr_t riscv_hart_msu_vp<BASE>::virt2phys(const iss::addr_t& addr) {
+template <typename BASE>
+typename riscv_hart_msu_vp<BASE>::phys_addr_t riscv_hart_msu_vp<BASE>::virt2phys(const iss::addr_t &addr) {
     const auto type = addr.access & iss::access_type::FUNC;
     auto it = ptw.find(addr.val >> PGSHIFT);
     if (it != ptw.end()) {
@@ -1194,8 +1157,8 @@ template <typename BASE> typename riscv_hart_msu_vp<BASE>::phys_addr_t riscv_har
 #endif
     } else {
         uint32_t mode = type != iss::access_type::FETCH && state.mstatus.MPRV ? // MPRV
-                            state.mstatus.MPP
+                            state.mstatus.MPP :
-                                                                              : this->reg.PRIV;
+                            this->reg.PRIV;
 
         const vm_info &vm = this->vm[static_cast<uint16_t>(type) / 2];
 
@@ -1216,10 +1179,9 @@ template <typename BASE> typename riscv_hart_msu_vp<BASE>::phys_addr_t riscv_har
 
             // check that physical address of PTE is legal
             reg_t pte = 0;
-            const uint8_t res = this->read(iss::address_type::PHYSICAL, addr.access, traits<BASE>::MEM, base + idx * vm.ptesize, vm.ptesize,
+            const uint8_t res = this->read(iss::address_type::PHYSICAL, addr.access,
-                                           (uint8_t*)&pte);
+                    traits<BASE>::MEM, base + idx * vm.ptesize, vm.ptesize, (uint8_t *)&pte);
-            if(res != 0)
+            if (res != 0) throw trap_load_access_fault(addr.val);
-                throw trap_load_access_fault(addr.val);
             const reg_t ppn = pte >> PTE_PPN_SHIFT;
 
             if (PTE_TABLE(pte)) { // next level of page table
@@ -1228,7 +1190,8 @@ template <typename BASE> typename riscv_hart_msu_vp<BASE>::phys_addr_t riscv_har
                 break;
             } else if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) {
                 break;
-            } else if(type == iss::access_type::FETCH  ? !(pte & PTE_X)
+            } else if (type == iss::access_type::FETCH
+                           ? !(pte & PTE_X)
                            : type == iss::access_type::READ ? !(pte & PTE_R) && !(mxr && (pte & PTE_X))
                                                             : !((pte & PTE_R) && (pte & PTE_W))) {
                 break;
@@ -1241,8 +1204,7 @@ template <typename BASE> typename riscv_hart_msu_vp<BASE>::phys_addr_t riscv_har
                 *(uint32_t *)ppte |= ad;
 #else
                 // take exception if access or possibly dirty bit is not set.
-                if((pte & ad) != ad)
+                if ((pte & ad) != ad) break;
-                    break;
 #endif
                 // for superpage mappings, make a fake leaf PTE for the TLB's benefit.
                 const reg_t vpn = addr.val >> PGSHIFT;
@@ -1272,12 +1234,10 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t f
     auto cur_priv = this->reg.PRIV;
     // flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
     // calculate and write mcause val
-    if(flags == std::numeric_limits<uint64_t>::max())
+    if(flags==std::numeric_limits<uint64_t>::max()) flags=this->reg.trap_state;
-        flags = this->reg.trap_state;
     auto trap_id = bit_sub<0, 16>(flags);
     auto cause = bit_sub<16, 15>(flags);
-    if(trap_id == 0 && cause == 11)
+    if (trap_id == 0 && cause == 11) cause = 0x8 + cur_priv; // adjust environment call cause
-        cause = 0x8 + cur_priv; // adjust environment call cause
     // calculate effective privilege level
     auto new_priv = PRIV_M;
     if (trap_id == 0) { // exception
@@ -1353,15 +1313,14 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t f
     // calculate addr// set NEXT_PC to trap addressess to jump to based on MODE
     // bits in mtvec
     this->reg.NEXT_PC = ivec & ~0x3UL;
-    if((ivec & 0x1) == 1 && trap_id != 0)
+    if ((ivec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
-        this->reg.NEXT_PC += 4 * cause;
     std::array<char, 32> buffer;
     sprintf(buffer.data(), "0x%016lx", addr);
     if((flags&0xffffffff) != 0xffffffff)
-        CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '" << (trap_id ? irq_str[cause] : trap_str[cause]) << "' ("
+    CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '"
-                           << cause << ")"
+                       << (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << cause << ")"
-                           << " at address " << buffer.data() << " occurred, changing privilege level from " << lvl[cur_priv] << " to "
+                       << " at address " << buffer.data() << " occurred, changing privilege level from "
-                           << lvl[new_priv];
+                       << lvl[cur_priv] << " to " << lvl[new_priv];
     // reset trap state
     this->reg.PRIV = new_priv;
     this->reg.trap_state = 0;
@@ -1404,7 +1363,8 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::leave_trap(uint64_t f
     }
     // sets the pc to the value stored in the x epc register.
     this->reg.NEXT_PC = csr[uepc | inst_priv << 8];
-    CLOG(INFO, disass) << "Executing xRET , changing privilege level from " << lvl[cur_priv] << " to " << lvl[this->reg.PRIV];
+    CLOG(INFO, disass) << "Executing xRET , changing privilege level from " << lvl[cur_priv] << " to "
+                       << lvl[this->reg.PRIV];
     update_vm_info();
     check_interrupt();
     return this->reg.NEXT_PC;
@@ -1418,7 +1378,7 @@ template <typename BASE> void riscv_hart_msu_vp<BASE>::wait_until(uint64_t flags
         this->fault_data = this->reg.PC;
     }
 }
-} // namespace arch
+}
-} // namespace iss
+}
 
 #endif /* _RISCV_HART_MSU_VP_H */

src/iss/arch/riscv_hart_mu_p.h

@@ -35,22 +35,22 @@
 #ifndef _RISCV_HART_MU_P_H
 #define _RISCV_HART_MU_P_H
 
+#include "riscv_hart_common.h"
 #include "iss/arch/traits.h"
 #include "iss/instrumentation_if.h"
 #include "iss/log_categories.h"
 #include "iss/vm_if.h"
-#include "riscv_hart_common.h"
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
 #endif
 #include <array>
 #include <elfio/elfio.hpp>
 #include <fmt/format.h>
-#include <functional>
 #include <iomanip>
 #include <sstream>
 #include <type_traits>
 #include <unordered_map>
+#include <functional>
 #include <util/bit_field.h>
 #include <util/ities.h>
 #include <util/sparse_array.h>
@@ -86,11 +86,10 @@ protected:
                                               "Load page fault",                // d
                                               "Reserved",                       // e
                                               "Store/AMO page fault"}};
-    const std::array<const char*, 12> irq_str = {{"User software interrupt", "Supervisor software interrupt", "Reserved",
+    const std::array<const char *, 12> irq_str = {
-                                                  "Machine software interrupt", "User timer interrupt", "Supervisor timer interrupt",
+        {"User software interrupt", "Supervisor software interrupt", "Reserved", "Machine software interrupt",
-                                                  "Reserved", "Machine timer interrupt", "User external interrupt",
+         "User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt",
-                                                  "Supervisor external interrupt", "Reserved", "Machine external interrupt"}};
+         "User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}};
-
 public:
     using core = BASE;
     using this_class = riscv_hart_mu_p<BASE, FEAT>;
@@ -109,8 +108,7 @@ public:
     template <typename T> class hart_state<T, typename std::enable_if<std::is_same<T, uint32_t>::value>::type> {
     public:
         BEGIN_BF_DECL(mstatus_t, T);
-        // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR
+        // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11)))
-        // XS==11)))
         BF_FIELD(SD, 31, 1);
         // Trap SRET
         BF_FIELD(TSR, 22, 1);
@@ -124,8 +122,7 @@ public:
         BF_FIELD(SUM, 18, 1);
         // Modify PRiVilege
         BF_FIELD(MPRV, 17, 1);
-        // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None
+        // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None dirty, some clean/Some dirty
-        // dirty, some clean/Some dirty
         BF_FIELD(XS, 15, 2);
         // floating-point unit status Off/Initial/Clean/Dirty
         BF_FIELD(FS, 13, 2);
@@ -162,8 +159,7 @@ public:
             return priv_lvl == PRIV_U ? 0x80000011UL : priv_lvl == PRIV_S ? 0x800de133UL : 0x807ff9ddUL;
 #else
             switch (priv_lvl) {
-            case PRIV_U:
+            case PRIV_U: return 0x00000011UL; // 0b1000 0000 0000 0000 0000 0000 0001 0001
-                return 0x00000011UL; // 0b1000 0000 0000 0000 0000 0000 0001 0001
             default:
             //       +-SD
             //       |        +-TSR
@@ -190,8 +186,7 @@ public:
     template <typename T> class hart_state<T, typename std::enable_if<std::is_same<T, uint64_t>::value>::type> {
     public:
         BEGIN_BF_DECL(mstatus_t, T);
-        // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR
+        // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11)))
-        // XS==11)))
         BF_FIELD(SD, 63, 1);
         // value of XLEN for S-mode
         BF_FIELD(SXL, 34, 2);
@@ -209,8 +204,7 @@ public:
         BF_FIELD(SUM, 18, 1);
         // Modify PRiVilege
         BF_FIELD(MPRV, 17, 1);
-        // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None
+        // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None dirty, some clean/Some dirty
-        // dirty, some clean/Some dirty
         BF_FIELD(XS, 15, 2);
         // floating-point unit status Off/Initial/Clean/Dirty
         BF_FIELD(FS, 13, 2);
@@ -247,8 +241,7 @@ public:
             return priv_lvl == PRIV_U ? 0x011ULL : priv_lvl == PRIV_S ? 0x000de133ULL : 0x007ff9ddULL;
 #else
             switch (priv_lvl) {
-            case PRIV_U:
+            case PRIV_U: return 0x00000011UL; // 0b1000 0000 0000 0000 0000 0000 0001 0001
-                return 0x00000011UL; // 0b1000 0000 0000 0000 0000 0000 0001 0001
             default:
             //       +-SD
             //       |        +-TSR
@@ -283,8 +276,12 @@ public:
         return m[mode];
     }
 
-    constexpr bool has_compressed() { return traits<BASE>::MISA_VAL & 0b0100; }
+    constexpr bool has_compressed() {
-    constexpr reg_t get_pc_mask() { return has_compressed() ? ~1 : ~3; }
+        return traits<BASE>::MISA_VAL&0b0100;
+    }
+    constexpr reg_t get_pc_mask() {
+        return has_compressed()?~1:~3;
+    }
 
     riscv_hart_mu_p(feature_config cfg = feature_config{});
     
@@ -294,10 +291,10 @@ public:
 
     std::pair<uint64_t, bool> load_file(std::string name, int type = -1) override;
 
-    iss::status read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length,
+    iss::status read(const address_type type, const access_type access, const uint32_t space,
-                     uint8_t* const data) override;
+            const uint64_t addr, const unsigned length, uint8_t *const data) override;
-    iss::status write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length,
+    iss::status write(const address_type type, const access_type access, const uint32_t space,
-                      const uint8_t* const data) override;
+            const uint64_t addr, const unsigned length, const uint8_t *const data) override;
 
     uint64_t enter_trap(uint64_t flags) override { return riscv_hart_mu_p::enter_trap(flags, fault_data, fault_data); }
     uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
@@ -307,16 +304,19 @@ public:
 	void set_mhartid(reg_t mhartid) { mhartid_reg = mhartid; };
 
     void disass_output(uint64_t pc, const std::string instr) override {
-        CLOG(INFO, disass) << fmt::format("0x{:016x}    {:40} [p:{};s:0x{:x};c:{}]", pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus,
+        CLOG(INFO, disass) << fmt::format("0x{:016x}    {:40} [p:{};s:0x{:x};c:{}]",
-                                          this->reg.icount + cycle_offset);
+                pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus, this->reg.icount + cycle_offset);
     };
 
     iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
 
-    void set_csr(unsigned addr, reg_t val) { csr[addr & csr.page_addr_mask] = val; }
+    void set_csr(unsigned addr, reg_t val){
-
+        csr[addr & csr.page_addr_mask] = val;
-    void set_irq_num(unsigned i) { mcause_max_irq = 1 << util::ilog2(i); }
+    }
 
+    void set_irq_num(unsigned i) {
+        mcause_max_irq=1<<util::ilog2(i);
+    }
 protected:
     struct riscv_instrumentation_if : public iss::instrumentation_if {
 
@@ -329,9 +329,9 @@ protected:
          */
         const std::string core_type_name() const override { return traits<BASE>::core_type; }
 
-        uint64_t get_pc() override { return arch.reg.PC; }
+        uint64_t get_pc() override { return arch.reg.PC; };
 
-        uint64_t get_next_pc() override { return arch.reg.NEXT_PC; }
+        uint64_t get_next_pc() override { return arch.reg.NEXT_PC; };
 
         uint64_t get_instr_word() override { return arch.reg.instruction; }
 
@@ -341,13 +341,9 @@ protected:
 
         uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }
 
-        void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; }
+        void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
 
-        bool is_branch_taken() override { return arch.reg.last_branch; }
+        bool is_branch_taken() override { return arch.reg.last_branch; };
-
-        unsigned get_reg_num() override { return traits<BASE>::NUM_REGS; }
-
-        unsigned get_reg_size(unsigned num) override { return traits<BASE>::reg_bit_widths[num]; }
 
         riscv_hart_mu_p<BASE, FEAT> &arch;
     };
@@ -435,8 +431,12 @@ protected:
     virtual iss::status read_custom_csr_reg(unsigned addr, reg_t &val) {return iss::status::Err;};
     virtual iss::status write_custom_csr_reg(unsigned addr, reg_t val) {return iss::status::Err;};
 
-    void register_custom_csr_rd(unsigned addr) { csr_rd_cb[addr] = &this_class::read_custom_csr_reg; }
+    void register_custom_csr_rd(unsigned addr){
-    void register_custom_csr_wr(unsigned addr) { csr_wr_cb[addr] = &this_class::write_custom_csr_reg; }
+        csr_rd_cb[addr] = &this_class::read_custom_csr_reg;
+    }
+    void register_custom_csr_wr(unsigned addr){
+        csr_wr_cb[addr] = &this_class::write_custom_csr_reg;
+    }
 
     reg_t mhartid_reg{0x0};
 
@@ -450,8 +450,8 @@ protected:
     uint64_t mcause_max_irq{(FEAT&features_e::FEAT_CLIC)?4096:16};
     inline bool debug_mode_active() {return this->reg.PRIV&0x4;}
 
-    std::pair<std::function<mem_read_f>, std::function<mem_write_f>> replace_mem_access(std::function<mem_read_f> rd,
+    std::pair<std::function<mem_read_f>, std::function<mem_write_f>>
-                                                                                        std::function<mem_write_f> wr) {
+    replace_mem_access(std::function<mem_read_f> rd, std::function<mem_write_f> wr){
         std::pair<std::function<mem_read_f>, std::function<mem_write_f>> ret{hart_mem_rd_delegate, hart_mem_wr_delegate};
         hart_mem_rd_delegate = rd;
         hart_mem_wr_delegate = wr;
@@ -477,8 +477,7 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
         csr_rd_cb[addr] = &this_class::read_null;
         csr_wr_cb[addr] = &this_class::write_csr_reg;
     }
-    if(traits<BASE>::XLEN == 32)
+    if(traits<BASE>::XLEN==32) for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){
-        for(unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr) {
         csr_rd_cb[addr] = &this_class::read_null;
         csr_wr_cb[addr] = &this_class::write_csr_reg;
     }
@@ -489,8 +488,7 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
     for (unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr){
         csr_rd_cb[addr] = &this_class::read_null;
     }
-    if(traits<BASE>::XLEN == 32)
+    if(traits<BASE>::XLEN==32) for (unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr){
-        for(unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr) {
         csr_rd_cb[addr] = &this_class::read_null;
         //csr_wr_cb[addr] = &this_class::write_csr_reg;
     }
@@ -501,14 +499,8 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
         csr_wr_cb[addr] = &this_class::write_null;
     }
     const std::array<unsigned, 8> rwaddrs{{
-        mepc,
+        mepc, mtvec, mscratch, mtval,
-        mtvec,
+        uepc, utvec, uscratch, utval,
-        mscratch,
-        mtval,
-        uepc,
-        utvec,
-        uscratch,
-        utval,
     }};
     for(auto addr: rwaddrs) {
         csr_rd_cb[addr] = &this_class::read_csr_reg;
@@ -516,27 +508,20 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
     }
     // special handling & overrides
     csr_rd_cb[time] = &this_class::read_time;
-    if(traits<BASE>::XLEN == 32)
+    if(traits<BASE>::XLEN==32)  csr_rd_cb[timeh] = &this_class::read_time;
-        csr_rd_cb[timeh] = &this_class::read_time;
     csr_rd_cb[cycle] = &this_class::read_cycle;
-    if(traits<BASE>::XLEN == 32)
+    if(traits<BASE>::XLEN==32) csr_rd_cb[cycleh] = &this_class::read_cycle;
-        csr_rd_cb[cycleh] = &this_class::read_cycle;
     csr_rd_cb[instret] = &this_class::read_instret;
-    if(traits<BASE>::XLEN == 32)
+    if(traits<BASE>::XLEN==32) csr_rd_cb[instreth] = &this_class::read_instret;
-        csr_rd_cb[instreth] = &this_class::read_instret;
 
     csr_rd_cb[mcycle] = &this_class::read_cycle;
     csr_wr_cb[mcycle] = &this_class::write_cycle;
-    if(traits<BASE>::XLEN == 32)
+    if(traits<BASE>::XLEN==32) csr_rd_cb[mcycleh] = &this_class::read_cycle;
-        csr_rd_cb[mcycleh] = &this_class::read_cycle;
+    if(traits<BASE>::XLEN==32) csr_wr_cb[mcycleh] = &this_class::write_cycle;
-    if(traits<BASE>::XLEN == 32)
-        csr_wr_cb[mcycleh] = &this_class::write_cycle;
     csr_rd_cb[minstret] = &this_class::read_instret;
     csr_wr_cb[minstret] = &this_class::write_instret;
-    if(traits<BASE>::XLEN == 32)
+    if(traits<BASE>::XLEN==32) csr_rd_cb[minstreth] = &this_class::read_instret;
-        csr_rd_cb[minstreth] = &this_class::read_instret;
+    if(traits<BASE>::XLEN==32) csr_wr_cb[minstreth] = &this_class::write_instret;
-    if(traits<BASE>::XLEN == 32)
-        csr_wr_cb[minstreth] = &this_class::write_instret;
     csr_rd_cb[mstatus] = &this_class::read_status;
     csr_wr_cb[mstatus] = &this_class::write_status;
     csr_rd_cb[mcause] = &this_class::read_cause;
@@ -608,8 +593,7 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
         clic_uact_lvl = clic_uprev_lvl = (1<<(cfg.clic_int_ctl_bits)) - 1;
         csr[mintthresh] = (1<<(cfg.clic_int_ctl_bits)) - 1;
         csr[uintthresh] = (1<<(cfg.clic_int_ctl_bits)) - 1;
-        insert_mem_range(
+        insert_mem_range(cfg.clic_base, 0x5000UL,
-            cfg.clic_base, 0x5000UL,
                 [this](phys_addr_t addr, unsigned length, uint8_t * const data) { return read_clic(addr.val, length, data);},
                 [this](phys_addr_t addr, unsigned length, uint8_t const * const data) {return write_clic(addr.val, length, data);});
     }
@@ -637,8 +621,12 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
         csr_wr_cb[dcsr] = &this_class::write_dcsr_dcsr;
         csr_rd_cb[dcsr] = &this_class::read_dcsr_reg;
     }
-    hart_mem_rd_delegate = [this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status { return this->read_mem(a, l, d); };
+    hart_mem_rd_delegate = [this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status {
-    hart_mem_wr_delegate = [this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status { return this->write_mem(a, l, d); };
+        return this->read_mem(a, l, d);
+    };
+    hart_mem_wr_delegate = [this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status {
+        return this->write_mem(a, l, d);
+    };
 }
 
 template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_mu_p<BASE, FEAT>::load_file(std::string name, int type) {
@@ -647,37 +635,35 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
         std::array<char, 5> buf;
         auto n = fread(buf.data(), 1, 4, fp);
         fclose(fp);
-        if(n != 4)
+        if (n != 4) throw std::runtime_error("input file has insufficient size");
-            throw std::runtime_error("input file has insufficient size");
         buf[4] = 0;
         if (strcmp(buf.data() + 1, "ELF") == 0) {
             // Create elfio reader
             ELFIO::elfio reader;
             // Load ELF data
-            if(!reader.load(name))
+            if (!reader.load(name)) throw std::runtime_error("could not process elf file");
-                throw std::runtime_error("could not process elf file");
             // check elf properties
             if (reader.get_class() != ELFCLASS32)
-                if(sizeof(reg_t) == 4)
+                if (sizeof(reg_t) == 4) throw std::runtime_error("wrong elf class in file");
-                    throw std::runtime_error("wrong elf class in file");
+            if (reader.get_type() != ET_EXEC) throw std::runtime_error("wrong elf type in file");
-            if(reader.get_type() != ET_EXEC)
+            if (reader.get_machine() != EM_RISCV) throw std::runtime_error("wrong elf machine in file");
-                throw std::runtime_error("wrong elf type in file");
-            if(reader.get_machine() != EM_RISCV)
-                throw std::runtime_error("wrong elf machine in file");
             auto entry = reader.get_entry();
             for (const auto pseg : reader.segments) {
                 const auto fsize = pseg->get_file_size(); // 0x42c/0x0
                 const auto seg_data = pseg->get_data();
                 if (fsize > 0) {
-                    auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM,
+                    auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE,
-                                           pseg->get_physical_address(), fsize, reinterpret_cast<const uint8_t* const>(seg_data));
+                            traits<BASE>::MEM, pseg->get_physical_address(),
+                            fsize, reinterpret_cast<const uint8_t *const>(seg_data));
                     if (res != iss::Ok)
-                        LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address();
+                        LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex
+                                   << pseg->get_physical_address();
                 }
             }
             for(const auto sec : reader.sections) {
                 if(sec->get_name() == ".symtab") {
-                    if(SHT_SYMTAB == sec->get_type() || SHT_DYNSYM == sec->get_type()) {
+                    if ( SHT_SYMTAB == sec->get_type() ||
+                            SHT_DYNSYM == sec->get_type() ) {
                         ELFIO::symbol_section_accessor symbols( reader, sec );
                         auto sym_no = symbols.get_symbols_num();
                         std::string   name;
@@ -700,6 +686,7 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
                     tohost = sec->get_address();
                     fromhost = tohost + 0x40;
                 }
+
             }
             return std::make_pair(entry, true);
         }
@@ -712,22 +699,23 @@ template <typename BASE, features_e FEAT>
 inline void riscv_hart_mu_p<BASE, FEAT>::insert_mem_range(uint64_t base, uint64_t size, std::function<mem_read_f> rd_f,
         std::function<mem_write_f> wr_fn) {
     std::tuple<uint64_t, uint64_t> entry{base, size};
-    auto it = std::upper_bound(
+    auto it = std::upper_bound( memfn_range.begin(), memfn_range.end(), entry,
-        memfn_range.begin(), memfn_range.end(), entry,
+            [](std::tuple<uint64_t, uint64_t> const& a, std::tuple<uint64_t, uint64_t> const& b){
-        [](std::tuple<uint64_t, uint64_t> const& a, std::tuple<uint64_t, uint64_t> const& b) { return std::get<0>(a) < std::get<0>(b); });
+        return std::get<0>(a)<std::get<0>(b);
+    });
     auto idx = std::distance(memfn_range.begin(), it);
     memfn_range.insert(it, entry);
     memfn_read.insert(std::begin(memfn_read)+idx, rd_f);
     memfn_write.insert(std::begin(memfn_write)+idx, wr_fn);
 }
 
-template <typename BASE, features_e FEAT> inline iss::status riscv_hart_mu_p<BASE, FEAT>::write_pmpcfg_reg(unsigned addr, reg_t val) {
+template<typename BASE, features_e FEAT>
+inline iss::status riscv_hart_mu_p<BASE, FEAT>::write_pmpcfg_reg(unsigned addr, reg_t val) {
     csr[addr] = val & 0x9f9f9f9f;
     return iss::Ok;
 }
 
-template <typename BASE, features_e FEAT>
+template <typename BASE, features_e FEAT> bool riscv_hart_mu_p<BASE, FEAT>::pmp_check(const access_type type, const uint64_t addr, const unsigned len) {
-bool riscv_hart_mu_p<BASE, FEAT>::pmp_check(const access_type type, const uint64_t addr, const unsigned len) {
     constexpr auto PMP_SHIFT=2U;
     constexpr auto PMP_R = 0x1U;
     constexpr auto PMP_W = 0x2U;
@@ -767,8 +755,10 @@ bool riscv_hart_mu_p<BASE, FEAT>::pmp_check(const access_type type, const uint64
                 // If the PMP matches only a strict subset of the access, fail it
                 if (!all_match)
                     return false;
-                return (this->reg.PRIV == PRIV_M && !(cfg & PMP_L)) || (type == access_type::READ && (cfg & PMP_R)) ||
+                return  (this->reg.PRIV == PRIV_M && !(cfg & PMP_L)) ||
-                       (type == access_type::WRITE && (cfg & PMP_W)) || (type == access_type::FETCH && (cfg & PMP_X));
+                        (type == access_type::READ && (cfg & PMP_R)) ||
+                        (type == access_type::WRITE && (cfg & PMP_W)) ||
+                        (type == access_type::FETCH && (cfg & PMP_X));
             }
         }
         base = tor;
@@ -807,9 +797,10 @@ bool riscv_hart_mu_p<BASE, FEAT>::pmp_check(const access_type type, const uint64
     return !any_active || this->reg.PRIV == PRIV_M;
 }
 
+
 template <typename BASE, features_e FEAT>
-iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr,
+iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const access_type access, const uint32_t space,
-                                              const unsigned length, uint8_t* const data) {
+        const uint64_t addr, const unsigned length, uint8_t *const data) {
 #ifndef NDEBUG
     if (access && iss::access_type::DEBUG) {
         LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
@@ -825,8 +816,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
             if(FEAT & FEAT_PMP){
                 if(!pmp_check(access, addr, length) && !is_debug(access)) {
                     fault_data = addr;
-                    if(is_debug(access))
+                    if (is_debug(access)) throw trap_access(0, addr);
-                        throw trap_access(0, addr);
                     this->reg.trap_state = (1UL << 31) | ((access==access_type::FETCH?1:5) << 16); // issue trap 1
                     return iss::Err;
                 }
@@ -834,8 +824,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
             auto alignment = is_fetch(access)? (has_compressed()? 2 : 4) : length;
             if (unlikely(is_fetch(access) && (addr&(alignment-1)))) {
                 fault_data = addr;
-                if(is_debug(access))
+                if (is_debug(access)) throw trap_access(0, addr);
-                    throw trap_access(0, addr);
                 this->reg.trap_state = (1UL << 31); // issue trap 0
                 return iss::Err;
             }
@@ -845,11 +834,10 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
                     fault_data=addr;
                     return iss::Err;
                 }
-                phys_addr_t phys_addr{access, space, addr};
+                auto phys_addr = type==iss::address_type::PHYSICAL?phys_addr_t{access, space, addr}:BASE::v2p(iss::addr_t{access, type, space, addr});
                 auto res = iss::Err;
                 if(!is_fetch(access) && memfn_range.size()){
-                    auto it =
+                    auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){
-                        std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a) {
                         return std::get<0>(a)<=phys_addr.val && (std::get<0>(a)+std::get<1>(a))>phys_addr.val;
                     });
                     if(it!=std::end(memfn_range)) {
@@ -860,7 +848,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
                 } else {
                     res = hart_mem_rd_delegate( phys_addr, length, data);
                 }
-                if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
+                if (unlikely(res != iss::Ok)){
                     this->reg.trap_state = (1UL << 31) | (5 << 16); // issue trap 5 (load access fault
                     fault_data=addr;
                 }
@@ -872,13 +860,11 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
             }
         } break;
         case traits<BASE>::CSR: {
-            if(length != sizeof(reg_t))
+            if (length != sizeof(reg_t)) return iss::Err;
-                return iss::Err;
             return read_csr(addr, *reinterpret_cast<reg_t *const>(data));
         } break;
         case traits<BASE>::FENCE: {
-            if((addr + length) > mem.size())
+            if ((addr + length) > mem.size()) return iss::Err;
-                return iss::Err;
             return iss::Ok;
         } break;
         case traits<BASE>::RES: {
@@ -901,26 +887,26 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
 }
 
 template <typename BASE, features_e FEAT>
-iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr,
+iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const access_type access, const uint32_t space,
-                                               const unsigned length, const uint8_t* const data) {
+        const uint64_t addr, const unsigned length, const uint8_t *const data) {
 #ifndef NDEBUG
     const char *prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
     switch (length) {
     case 8:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x"
+        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t *)&data[0] << std::dec
-                   << std::hex << addr;
+                   << ") @addr 0x" << std::hex << addr;
         break;
     case 4:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x"
+        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t *)&data[0] << std::dec
-                   << std::hex << addr;
+                   << ") @addr 0x" << std::hex << addr;
         break;
     case 2:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x"
+        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t *)&data[0] << std::dec
-                   << std::hex << addr;
+                   << ") @addr 0x" << std::hex << addr;
         break;
     case 1:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x"
+        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec
-                   << std::hex << addr;
+                   << ") @addr 0x" << std::hex << addr;
         break;
     default:
         LOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
@@ -932,16 +918,14 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
             if(FEAT & FEAT_PMP){
                 if(!pmp_check(access, addr, length) && (access&access_type::DEBUG) != access_type::DEBUG) {
                     fault_data = addr;
-                    if(access && iss::access_type::DEBUG)
+                    if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                        throw trap_access(0, addr);
                     this->reg.trap_state = (1UL << 31) | (7 << 16); // issue trap 1
                     return iss::Err;
                 }
             }
             if (unlikely(is_fetch(access) && (addr & 0x1) == 1)) {
                 fault_data = addr;
-                if(access && iss::access_type::DEBUG)
+                if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                    throw trap_access(0, addr);
                 this->reg.trap_state = (1UL << 31); // issue trap 0
                 return iss::Err;
             }
@@ -951,11 +935,10 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
                     fault_data=addr;
                     return iss::Err;
                 }
-                phys_addr_t phys_addr{access, space, addr};
+                auto phys_addr = type==iss::address_type::PHYSICAL?phys_addr_t{access, space, addr}:BASE::v2p(iss::addr_t{access, type, space, addr});
                 auto res = iss::Err;
                 if(!is_fetch(access) && memfn_range.size()){
-                    auto it =
+                    auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){
-                        std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a) {
                         return std::get<0>(a)<=phys_addr.val && (std::get<0>(a)+std::get<1>(a))>phys_addr.val;
                     });
                     if(it!=std::end(memfn_range)) {
@@ -966,7 +949,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
                 } else {
                     res = hart_mem_wr_delegate( phys_addr, length, data);
                 }
-                if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
+                if (unlikely(res != iss::Ok)) {
                     this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault)
                     fault_data=addr;
                 }
@@ -977,48 +960,44 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
                 return iss::Err;
             }
 
-            if((addr + length) > mem.size())
+            phys_addr_t paddr = BASE::v2p(iss::addr_t{access, type, space, addr});
-                return iss::Err;
+            if ((paddr.val + length) > mem.size()) return iss::Err;
-            switch(addr) {
+            switch (paddr.val) {
             case 0x10013000: // UART0 base, TXFIFO reg
             case 0x10023000: // UART1 base, TXFIFO reg
                 uart_buf << (char)data[0];
                 if (((char)data[0]) == '\n' || data[0] == 0) {
-                    // LOG(INFO)<<"UART"<<((addr>>16)&0x3)<<" send
+                    // LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
                     // '"<<uart_buf.str()<<"'";
                     std::cout << uart_buf.str();
                     uart_buf.str("");
                 }
                 return iss::Ok;
             case 0x10008000: { // HFROSC base, hfrosccfg reg
-                auto& p = mem(addr / mem.page_size);
+                auto &p = mem(paddr.val / mem.page_size);
-                auto offs = addr & mem.page_addr_mask;
+                auto offs = paddr.val & mem.page_addr_mask;
                 std::copy(data, data + length, p.data() + offs);
                 auto &x = *(p.data() + offs + 3);
-                if(x & 0x40)
+                if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1
-                    x |= 0x80; // hfroscrdy = 1 if hfroscen==1
                 return iss::Ok;
             }
             case 0x10008008: { // HFROSC base, pllcfg reg
-                auto& p = mem(addr / mem.page_size);
+                auto &p = mem(paddr.val / mem.page_size);
-                auto offs = addr & mem.page_addr_mask;
+                auto offs = paddr.val & mem.page_addr_mask;
                 std::copy(data, data + length, p.data() + offs);
                 auto &x = *(p.data() + offs + 3);
                 x |= 0x80; // set pll lock upon writing
                 return iss::Ok;
             } break;
-            default: {
+            default: {}
-            }
             }
         } break;
         case traits<BASE>::CSR: {
-            if(length != sizeof(reg_t))
+            if (length != sizeof(reg_t)) return iss::Err;
-                return iss::Err;
             return write_csr(addr, *reinterpret_cast<const reg_t *>(data));
         } break;
         case traits<BASE>::FENCE: {
-            if((addr + length) > mem.size())
+            if ((addr + length) > mem.size()) return iss::Err;
-                return iss::Err;
             switch (addr) {
             case 2:
             case 3: {
@@ -1043,8 +1022,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
 }
 
 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_csr(unsigned addr, reg_t &val) {
-    if(addr >= csr.size())
+    if (addr >= csr.size()) return iss::Err;
-        return iss::Err;
     auto req_priv_lvl = (addr >> 8) & 0x3;
     if (this->reg.PRIV < req_priv_lvl) // not having required privileges
         throw illegal_instruction_fault(this->fault_data);
@@ -1055,8 +1033,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
 }
 
 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_csr(unsigned addr, reg_t val) {
-    if(addr >= csr.size())
+    if (addr >= csr.size()) return iss::Err;
-        return iss::Err;
     auto req_priv_lvl = (addr >> 8) & 0x3;
     if (this->reg.PRIV < req_priv_lvl) // not having required privileges
         throw illegal_instruction_fault(this->fault_data);
@@ -1135,8 +1112,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
     if (addr == time) {
         val = static_cast<reg_t>(time_val);
     } else if (addr == timeh) {
-        if(sizeof(typename traits<BASE>::reg_t) != 4)
+        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
-            return iss::Err;
         val = static_cast<reg_t>(time_val >> 32);
     }
     return iss::Ok;
@@ -1284,7 +1260,8 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
     return iss::Ok;
 }
 
-template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_intstatus(unsigned addr, reg_t& val) {
+template<typename BASE, features_e FEAT>
+iss::status riscv_hart_mu_p<BASE, FEAT>::read_intstatus(unsigned addr, reg_t& val) {
     auto mode = (addr >> 8) & 0x3;
     val = clic_uact_lvl&0xff;
     if(mode==0x3)
@@ -1292,12 +1269,14 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
     return iss::Ok;
 }
 
-template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_intthresh(unsigned addr, reg_t val) {
+template<typename BASE, features_e FEAT>
+iss::status riscv_hart_mu_p<BASE, FEAT>::write_intthresh(unsigned addr, reg_t val) {
     csr[addr]= (val &0xff) | (1<<(cfg.clic_int_ctl_bits)) - 1;
     return iss::Ok;
 }
 
-template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_xtvt(unsigned addr, reg_t val) {
+template<typename BASE, features_e FEAT>
+iss::status riscv_hart_mu_p<BASE, FEAT>::write_xtvt(unsigned addr, reg_t val) {
     csr[addr]= val & ~0x3fULL;
     return iss::Ok;
 }
@@ -1329,9 +1308,10 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned l
         std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
         // tohost handling in case of riscv-test
         if (paddr.access && iss::access_type::FUNC) {
-            auto tohost_upper =
+            auto tohost_upper = (traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4)) ||
-                (traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4)) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
+                                (traits<BASE>::XLEN == 64 && paddr.val == tohost);
-            auto tohost_lower = (traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
+            auto tohost_lower =
+                (traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
             if (tohost_lower || tohost_upper) {
                 uint64_t hostvar = *reinterpret_cast<uint64_t *>(p.data() + (tohost & mem.page_addr_mask));
                 if (tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) {
@@ -1362,7 +1342,8 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned l
                     }
                 } else if (tohost_lower)
                     to_host_wr_cnt++;
-            } else if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
+            } else if ((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) ||
+                       (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
                 uint64_t fhostvar = *reinterpret_cast<uint64_t *>(p.data() + (fromhost & mem.page_addr_mask));
                 *reinterpret_cast<uint64_t *>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
             }
@@ -1376,18 +1357,15 @@ template <typename BASE, features_e FEAT>
 iss::status riscv_hart_mu_p<BASE, FEAT>::read_clic(uint64_t addr, unsigned length, uint8_t *const data) {
     if(addr==cfg.clic_base) { // cliccfg
         *data=clic_cfg_reg;
-        for(auto i = 1; i < length; ++i)
+        for(auto i=1; i<length; ++i) *(data+i)=0;
-            *(data + i) = 0;
     } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
         auto offset = ((addr&0x7fff)-0x40)/4;
         read_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
-    } else if(addr >= (cfg.clic_base + 0x1000) &&
+    } else if(addr>=(cfg.clic_base+0x1000) && (addr+length)<=(cfg.clic_base+0x1000+cfg.clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
-              (addr + length) <= (cfg.clic_base + 0x1000 + cfg.clic_num_irq * 4)) { // clicintip/clicintie/clicintattr/clicintctl
         auto offset = ((addr&0x7fff)-0x1000)/4;
         read_reg_uint32(addr, clic_int_reg[offset].raw, data, length);
     } else {
-        for(auto i = 0U; i < length; ++i)
+        for(auto i = 0U; i<length; ++i) *(data+i)=0;
-            *(data + i) = 0;
     }
     return iss::Ok;
 }
@@ -1399,8 +1377,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write_clic(uint64_t addr, unsigned leng
     } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
         auto offset = ((addr&0x7fff)-0x40)/4;
         write_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
-    } else if(addr >= (cfg.clic_base + 0x1000) &&
+    } else if(addr>=(cfg.clic_base+0x1000) && (addr+length)<=(cfg.clic_base+0x1000+cfg.clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
-              (addr + length) <= (cfg.clic_base + 0x1000 + cfg.clic_num_irq * 4)) { // clicintip/clicintie/clicintattr/clicintctl
         auto offset = ((addr&0x7fff)-0x1000)/4;
         write_reg_uint32(addr, clic_int_reg[offset].raw, data, length);
         clic_int_reg[offset].raw &= 0xf0c70101; // clicIntCtlBits->0xf0, clicintattr->0xc7, clicintie->0x1, clicintip->0x1
@@ -1439,12 +1416,10 @@ template <typename BASE, features_e FEAT> void riscv_hart_mu_p<BASE, FEAT>::chec
 template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) {
     // flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
     // calculate and write mcause val
-    if(flags == std::numeric_limits<uint64_t>::max())
+    if(flags==std::numeric_limits<uint64_t>::max()) flags=this->reg.trap_state;
-        flags = this->reg.trap_state;
     auto trap_id = bit_sub<0, 16>(flags);
     auto cause = bit_sub<16, 15>(flags);
-    if(trap_id == 0 && cause == 11)
+    if (trap_id == 0 && cause == 11) cause = 0x8 + this->reg.PRIV; // adjust environment call cause
-        cause = 0x8 + this->reg.PRIV; // adjust environment call cause
     // calculate effective privilege level
     unsigned new_priv = PRIV_M;
     if (trap_id == 0) { // exception
@@ -1535,10 +1510,10 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
     sprintf(buffer.data(), "0x%016lx", addr);
 #endif
     if((flags&0xffffffff) != 0xffffffff)
-        CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '" << (trap_id ? irq_str[cause] : trap_str[cause]) << "' ("
+    CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '"
-                           << cause << ")"
+                       << (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << cause << ")"
-                           << " at address " << buffer.data() << " occurred, changing privilege level from " << lvl[this->reg.PRIV]
+                       << " at address " << buffer.data() << " occurred, changing privilege level from "
-                           << " to " << lvl[new_priv];
+                       << lvl[this->reg.PRIV] << " to " << lvl[new_priv];
     // reset trap state
     this->reg.PRIV = new_priv;
     this->reg.trap_state = 0;
@@ -1571,7 +1546,8 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
         }
         // sets the pc to the value stored in the x epc register.
         this->reg.NEXT_PC = csr[uepc | inst_priv << 8];
-        CLOG(INFO, disass) << "Executing xRET , changing privilege level from " << lvl[cur_priv] << " to " << lvl[this->reg.PRIV];
+        CLOG(INFO, disass) << "Executing xRET , changing privilege level from " << lvl[cur_priv] << " to "
+                           << lvl[this->reg.PRIV];
         check_interrupt();
     }
     return this->reg.NEXT_PC;

src/iss/arch/tgc_c.cpp

@@ -30,8 +30,7 @@
  *
  *******************************************************************************/
 
-// clang-format off
+#include "tgc_c.h"
-#include "tgc5c.h"
 #include "util/ities.h"
 #include <util/logging.h>
 #include <cstdio>
@@ -40,18 +39,18 @@
 
 using namespace iss::arch;
 
-constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc5c>::reg_names;
+constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc_c>::reg_names;
-constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc5c>::reg_aliases;
+constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc_c>::reg_aliases;
-constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc5c>::reg_bit_widths;
+constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths;
-constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc5c>::reg_byte_offsets;
+constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets;
 
-tgc5c::tgc5c()  = default;
+tgc_c::tgc_c()  = default;
 
-tgc5c::~tgc5c() = default;
+tgc_c::~tgc_c() = default;
 
-void tgc5c::reset(uint64_t address) {
+void tgc_c::reset(uint64_t address) {
-    auto base_ptr = reinterpret_cast<traits<tgc5c>::reg_t*>(get_regs_base_ptr());
+    auto base_ptr = reinterpret_cast<traits<tgc_c>::reg_t*>(get_regs_base_ptr());
-    for(size_t i=0; i<traits<tgc5c>::NUM_REGS; ++i)
+    for(size_t i=0; i<traits<tgc_c>::NUM_REGS; ++i)
         *(base_ptr+i)=0;
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
@@ -60,11 +59,11 @@ void tgc5c::reset(uint64_t address) {
     reg.icount=0;
 }
 
-uint8_t *tgc5c::get_regs_base_ptr() {
+uint8_t *tgc_c::get_regs_base_ptr() {
 	return reinterpret_cast<uint8_t*>(&reg);
 }
 
-tgc5c::phys_addr_t tgc5c::virt2phys(const iss::addr_t &addr) {
+tgc_c::phys_addr_t tgc_c::virt2phys(const iss::addr_t &pc) {
-    return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc5c>::addr_mask);
+    return phys_addr_t(pc); // change logical address to physical address
 }
-// clang-format on
+

src/iss/arch/tgc_c.h

@@ -30,9 +30,9 @@
  *
  *******************************************************************************/
 
-#ifndef _TGC5C_H_
+#ifndef _TGC_C_H_
-#define _TGC5C_H_
+#define _TGC_C_H_
-// clang-format off
+
 #include <array>
 #include <iss/arch/traits.h>
 #include <iss/arch_if.h>
@@ -41,19 +41,19 @@
 namespace iss {
 namespace arch {
 
-struct tgc5c;
+struct tgc_c;
 
-template <> struct traits<tgc5c> {
+template <> struct traits<tgc_c> {
 
-    constexpr static char const* const core_type = "TGC5C";
+    constexpr static char const* const core_type = "TGC_C";
     
     static constexpr std::array<const char*, 36> reg_names{
-        {"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc", "next_pc", "priv", "dpc"}};
+        {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV", "DPC"}};
  
     static constexpr std::array<const char*, 36> reg_aliases{
-        {"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "next_pc", "priv", "dpc"}};
+        {"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV", "DPC"}};
 
-    enum constants {MISA_VAL=1073746180ULL, MARCHID_VAL=2147483651ULL, XLEN=32ULL, INSTR_ALIGNMENT=2ULL, RFS=32ULL, fence=0ULL, fencei=1ULL, fencevmal=2ULL, fencevmau=3ULL, CSR_SIZE=4096ULL, MUL_LEN=64ULL};
+    enum constants {MISA_VAL=1073746180, MARCHID_VAL=2147483651, XLEN=32, INSTR_ALIGNMENT=2, RFS=32, fence=0, fencei=1, fencevmal=2, fencevmau=3, CSR_SIZE=4096, MUL_LEN=64};
 
     constexpr static unsigned FP_REGS_SIZE = 0;
 
@@ -141,49 +141,49 @@ template <> struct traits<tgc5c> {
         DIVU = 54,
         REM = 55,
         REMU = 56,
-        C__ADDI4SPN = 57,
+        CADDI4SPN = 57,
-        C__LW = 58,
+        CLW = 58,
-        C__SW = 59,
+        CSW = 59,
-        C__ADDI = 60,
+        CADDI = 60,
-        C__NOP = 61,
+        CNOP = 61,
-        C__JAL = 62,
+        CJAL = 62,
-        C__LI = 63,
+        CLI = 63,
-        C__LUI = 64,
+        CLUI = 64,
-        C__ADDI16SP = 65,
+        CADDI16SP = 65,
         __reserved_clui = 66,
-        C__SRLI = 67,
+        CSRLI = 67,
-        C__SRAI = 68,
+        CSRAI = 68,
-        C__ANDI = 69,
+        CANDI = 69,
-        C__SUB = 70,
+        CSUB = 70,
-        C__XOR = 71,
+        CXOR = 71,
-        C__OR = 72,
+        COR = 72,
-        C__AND = 73,
+        CAND = 73,
-        C__J = 74,
+        CJ = 74,
-        C__BEQZ = 75,
+        CBEQZ = 75,
-        C__BNEZ = 76,
+        CBNEZ = 76,
-        C__SLLI = 77,
+        CSLLI = 77,
-        C__LWSP = 78,
+        CLWSP = 78,
-        C__MV = 79,
+        CMV = 79,
-        C__JR = 80,
+        CJR = 80,
         __reserved_cmv = 81,
-        C__ADD = 82,
+        CADD = 82,
-        C__JALR = 83,
+        CJALR = 83,
-        C__EBREAK = 84,
+        CEBREAK = 84,
-        C__SWSP = 85,
+        CSWSP = 85,
         DII = 86,
         MAX_OPCODE
     };
 };
 
-struct tgc5c: public arch_if {
+struct tgc_c: public arch_if {
 
-    using virt_addr_t = typename traits<tgc5c>::virt_addr_t;
+    using virt_addr_t = typename traits<tgc_c>::virt_addr_t;
-    using phys_addr_t = typename traits<tgc5c>::phys_addr_t;
+    using phys_addr_t = typename traits<tgc_c>::phys_addr_t;
-    using reg_t =  typename traits<tgc5c>::reg_t;
+    using reg_t =  typename traits<tgc_c>::reg_t;
-    using addr_t = typename traits<tgc5c>::addr_t;
+    using addr_t = typename traits<tgc_c>::addr_t;
 
-    tgc5c();
+    tgc_c();
-    ~tgc5c();
+    ~tgc_c();
 
     void reset(uint64_t address=0) override;
 
@@ -195,6 +195,14 @@ struct tgc5c: public arch_if {
 
     inline uint64_t stop_code() { return interrupt_sim; }
 
+    inline phys_addr_t v2p(const iss::addr_t& addr){
+        if (addr.space != traits<tgc_c>::MEM || addr.type == iss::address_type::PHYSICAL ||
+                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
+            return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc_c>::addr_mask);
+        } else
+            return virt2phys(addr);
+    }
+
     virtual phys_addr_t virt2phys(const iss::addr_t& addr);
 
     virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
@@ -203,7 +211,7 @@ struct tgc5c: public arch_if {
 
 
 #pragma pack(push, 1)
-    struct TGC5C_regs { 
+    struct TGC_C_regs { 
         uint32_t X0 = 0; 
         uint32_t X1 = 0; 
         uint32_t X2 = 0; 
@@ -259,5 +267,4 @@ struct tgc5c: public arch_if {
 
 }
 }            
-#endif /* _TGC5C_H_ */
+#endif /* _TGC_C_H_ */
-// clang-format on

src/iss/arch/tgc_c_decoder.cpp

@@ -0,0 +1,175 @@
+#include "tgc_c.h"
+#include <vector>
+#include <array>
+#include <cstdlib>
+#include <algorithm>
+
+namespace iss {
+namespace arch {
+namespace {
+// according to
+// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
+#ifdef __GCC__
+constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); }
+#elif __cplusplus < 201402L
+constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); }
+constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; }
+#else
+constexpr size_t bit_count(uint32_t u) {
+    size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111);
+    return ((uCount + (uCount >> 3)) & 030707070707) % 63;
+}
+#endif
+
+using opcode_e = traits<tgc_c>::opcode_e;
+
+/****************************************************************************
+ * start opcode definitions
+ ****************************************************************************/
+struct instruction_desriptor {
+    size_t length;
+    uint32_t value;
+    uint32_t mask;
+    opcode_e op;
+};
+
+const std::array<instruction_desriptor, 90> instr_descr = {{
+     /* entries are: size, valid value, valid mask, function ptr */
+    {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, opcode_e::LUI},
+    {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, opcode_e::AUIPC},
+    {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, opcode_e::JAL},
+    {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, opcode_e::JALR},
+    {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, opcode_e::BEQ},
+    {32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, opcode_e::BNE},
+    {32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, opcode_e::BLT},
+    {32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, opcode_e::BGE},
+    {32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, opcode_e::BLTU},
+    {32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, opcode_e::BGEU},
+    {32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, opcode_e::LB},
+    {32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, opcode_e::LH},
+    {32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, opcode_e::LW},
+    {32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, opcode_e::LBU},
+    {32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, opcode_e::LHU},
+    {32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, opcode_e::SB},
+    {32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, opcode_e::SH},
+    {32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, opcode_e::SW},
+    {32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, opcode_e::ADDI},
+    {32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, opcode_e::SLTI},
+    {32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, opcode_e::SLTIU},
+    {32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, opcode_e::XORI},
+    {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, opcode_e::ORI},
+    {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, opcode_e::ANDI},
+    {32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, opcode_e::SLLI},
+    {32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, opcode_e::SRLI},
+    {32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, opcode_e::SRAI},
+    {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, opcode_e::ADD},
+    {32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, opcode_e::SUB},
+    {32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, opcode_e::SLL},
+    {32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, opcode_e::SLT},
+    {32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, opcode_e::SLTU},
+    {32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, opcode_e::XOR},
+    {32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, opcode_e::SRL},
+    {32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, opcode_e::SRA},
+    {32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, opcode_e::OR},
+    {32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, opcode_e::AND},
+    {32, 0b00000000000000000000000000001111, 0b00000000000000000111000001111111, opcode_e::FENCE},
+    {32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, opcode_e::ECALL},
+    {32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, opcode_e::EBREAK},
+    {32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::URET},
+    {32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::SRET},
+    {32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::MRET},
+    {32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, opcode_e::WFI},
+    {32, 0b01111011001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::DRET},
+    {32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRW},
+    {32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRS},
+    {32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRC},
+    {32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRWI},
+    {32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRSI},
+    {32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRCI},
+    {32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, opcode_e::FENCE_I},
+    {32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, opcode_e::MUL},
+    {32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, opcode_e::MULH},
+    {32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, opcode_e::MULHSU},
+    {32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, opcode_e::MULHU},
+    {32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, opcode_e::DIV},
+    {32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, opcode_e::DIVU},
+    {32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, opcode_e::REM},
+    {32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, opcode_e::REMU},
+    {16, 0b0000000000000000, 0b1110000000000011, opcode_e::CADDI4SPN},
+    {16, 0b0100000000000000, 0b1110000000000011, opcode_e::CLW},
+    {16, 0b1100000000000000, 0b1110000000000011, opcode_e::CSW},
+    {16, 0b0000000000000001, 0b1110000000000011, opcode_e::CADDI},
+    {16, 0b0000000000000001, 0b1110111110000011, opcode_e::CNOP},
+    {16, 0b0010000000000001, 0b1110000000000011, opcode_e::CJAL},
+    {16, 0b0100000000000001, 0b1110000000000011, opcode_e::CLI},
+    {16, 0b0110000000000001, 0b1110000000000011, opcode_e::CLUI},
+    {16, 0b0110000100000001, 0b1110111110000011, opcode_e::CADDI16SP},
+    {16, 0b0110000000000001, 0b1111000001111111, opcode_e::__reserved_clui},
+    {16, 0b1000000000000001, 0b1111110000000011, opcode_e::CSRLI},
+    {16, 0b1000010000000001, 0b1111110000000011, opcode_e::CSRAI},
+    {16, 0b1000100000000001, 0b1110110000000011, opcode_e::CANDI},
+    {16, 0b1000110000000001, 0b1111110001100011, opcode_e::CSUB},
+    {16, 0b1000110000100001, 0b1111110001100011, opcode_e::CXOR},
+    {16, 0b1000110001000001, 0b1111110001100011, opcode_e::COR},
+    {16, 0b1000110001100001, 0b1111110001100011, opcode_e::CAND},
+    {16, 0b1010000000000001, 0b1110000000000011, opcode_e::CJ},
+    {16, 0b1100000000000001, 0b1110000000000011, opcode_e::CBEQZ},
+    {16, 0b1110000000000001, 0b1110000000000011, opcode_e::CBNEZ},
+    {16, 0b0000000000000010, 0b1111000000000011, opcode_e::CSLLI},
+    {16, 0b0100000000000010, 0b1110000000000011, opcode_e::CLWSP},
+    {16, 0b1000000000000010, 0b1111000000000011, opcode_e::CMV},
+    {16, 0b1000000000000010, 0b1111000001111111, opcode_e::CJR},
+    {16, 0b1000000000000010, 0b1111111111111111, opcode_e::__reserved_cmv},
+    {16, 0b1001000000000010, 0b1111000000000011, opcode_e::CADD},
+    {16, 0b1001000000000010, 0b1111000001111111, opcode_e::CJALR},
+    {16, 0b1001000000000010, 0b1111111111111111, opcode_e::CEBREAK},
+    {16, 0b1100000000000010, 0b1110000000000011, opcode_e::CSWSP},
+    {16, 0b0000000000000000, 0b1111111111111111, opcode_e::DII},
+}};
+
+}
+
+template<>
+struct instruction_decoder<tgc_c> {
+    using opcode_e = traits<tgc_c>::opcode_e;
+    using code_word_t=traits<tgc_c>::code_word_t;
+
+    struct instruction_pattern {
+        uint32_t value;
+        uint32_t mask;
+        opcode_e id;
+    };
+
+    std::array<std::vector<instruction_pattern>, 4> qlut;
+
+    template<typename T>
+    unsigned decode_instruction(T);
+
+    instruction_decoder() {
+        for (auto instr : instr_descr) {
+            auto quadrant = instr.value & 0x3;
+            qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
+        }
+        for(auto& lut: qlut){
+            std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
+                return bit_count(a.mask) > bit_count(b.mask);
+            });
+        }
+    }
+};
+
+template<>
+unsigned instruction_decoder<tgc_c>::decode_instruction<traits<tgc_c>::code_word_t>(traits<tgc_c>::code_word_t instr){
+    auto res = std::find_if(std::begin(qlut[instr&0x3]), std::end(qlut[instr&0x3]), [instr](instruction_pattern const& e){
+        return !((instr&e.mask) ^ e.value );
+    });
+    return static_cast<unsigned>(res!=std::end(qlut[instr&0x3])? res->id : opcode_e::MAX_OPCODE);
+}
+
+
+std::unique_ptr<instruction_decoder<tgc_c>> traits<tgc_c>::get_decoder(){
+    return std::make_unique<instruction_decoder<tgc_c>>();
+}
+
+}
+}

src/iss/arch/tgc_mapper.h

@@ -2,56 +2,49 @@
 #define _ISS_ARCH_TGC_MAPPER_H
 
 #include "riscv_hart_m_p.h"
-#include "tgc5c.h"
+#include "tgc_c.h"
-using tgc5c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc5c>;
+using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
-#ifdef CORE_TGC5A
+#ifdef CORE_TGC_A
 #include "riscv_hart_m_p.h"
-#include <iss/arch/tgc5a.h>
+#include <iss/arch/tgc_a.h>
-using tgc5a_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc5a>;
+using tgc_a_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_a>;
 #endif
-#ifdef CORE_TGC5B
+#ifdef CORE_TGC_B
 #include "riscv_hart_m_p.h"
-#include <iss/arch/tgc5b.h>
+#include <iss/arch/tgc_b.h>
-using tgc5b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc5b>;
+using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
 #endif
-#ifdef CORE_TGC5C_XRB_NN
+#ifdef CORE_TGC_C_XRB_NN
+#include "riscv_hart_m_p.h"
 #include "hwl.h"
-#include "riscv_hart_m_p.h"
+#include <iss/arch/tgc_c_xrb_nn.h>
-#include <iss/arch/tgc5c_xrb_nn.h>
+using tgc_c_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_m_p<iss::arch::tgc_c_xrb_nn>>;
-using tgc5c_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_m_p<iss::arch::tgc5c_xrb_nn>>;
 #endif
-#ifdef CORE_TGC5D
+#ifdef CORE_TGC_D
 #include "riscv_hart_mu_p.h"
-#include <iss/arch/tgc5d.h>
+#include <iss/arch/tgc_d.h>
-using tgc5d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc5d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC |
+using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
-                                                                                             iss::arch::FEAT_EXT_N)>;
 #endif
-#ifdef CORE_TGC5D_XRB_MAC
+#ifdef CORE_TGC_D_XRB_MAC
 #include "riscv_hart_mu_p.h"
-#include <iss/arch/tgc5d_xrb_mac.h>
+#include <iss/arch/tgc_d_xrb_mac.h>
-using tgc5d_xrb_mac_plat_type =
+using tgc_d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_mac, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
-    iss::arch::riscv_hart_mu_p<iss::arch::tgc5d_xrb_mac,
-                               (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
 #endif
-#ifdef CORE_TGC5D_XRB_NN
+#ifdef CORE_TGC_D_XRB_NN
+#include "riscv_hart_mu_p.h"
 #include "hwl.h"
-#include "riscv_hart_mu_p.h"
+#include <iss/arch/tgc_d_xrb_nn.h>
-#include <iss/arch/tgc5d_xrb_nn.h>
+using tgc_d_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_nn, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>>;
-using tgc5d_xrb_nn_plat_type =
-    iss::arch::hwl<iss::arch::riscv_hart_mu_p<iss::arch::tgc5d_xrb_nn,
-                                              (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>>;
 #endif
-#ifdef CORE_TGC5E
+#ifdef CORE_TGC_E
 #include "riscv_hart_mu_p.h"
-#include <iss/arch/tgc5e.h>
+#include <iss/arch/tgc_e.h>
-using tgc5e_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc5e, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC |
+using tgc_e_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_e, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
-                                                                                             iss::arch::FEAT_EXT_N)>;
 #endif
-#ifdef CORE_TGC5X
+#ifdef CORE_TGC_X
 #include "riscv_hart_mu_p.h"
-#include <iss/arch/tgc5x.h>
+#include <iss/arch/tgc_x.h>
-using tgc5x_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc5x, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC |
+using tgc_x_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_x, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N | iss::arch::FEAT_TCM)>;
-                                                                                             iss::arch::FEAT_EXT_N | iss::arch::FEAT_TCM)>;
 #endif
 
 #endif

src/iss/arch/wt_cache.h

@@ -36,10 +36,10 @@
 #define _RISCV_HART_M_P_WT_CACHE_H
 
 #include <iss/vm_types.h>
-#include <map>
-#include <memory>
 #include <util/ities.h>
 #include <vector>
+#include <map>
+#include <memory>
 
 namespace iss {
 namespace arch {
@@ -50,13 +50,11 @@ struct line {
     uint64_t tag_addr{0};
     state st{state::INVALID};
     std::vector<uint8_t> data;
-    line(unsigned line_sz)
+    line(unsigned line_sz):  data(line_sz) {}
-    : data(line_sz) {}
 };
 struct set {
     std::vector<line> ways;
-    set(unsigned ways_count, line const& l)
+    set(unsigned ways_count, line const& l): ways(ways_count, l) {}
-    : ways(ways_count, l) {}
 };
 struct cache {
     std::vector<set> sets;
@@ -71,7 +69,7 @@ struct cache {
 struct wt_policy {
     bool is_cacheline_hit(cache& c );
 };
-} // namespace cache
+}
 
 // write thru, allocate on read, direct mapped or set-associative with round-robin replacement policy
 template <typename BASE> class wt_cache : public BASE {
@@ -83,7 +81,7 @@ public:
     using mem_write_f = typename BASE::mem_write_f;
     using phys_addr_t = typename BASE::phys_addr_t;
 
-    wt_cache(feature_config cfg = feature_config{});
+    wt_cache();
     virtual ~wt_cache() = default;
 
     unsigned size{4096};
@@ -91,7 +89,6 @@ public:
     unsigned ways{1};
     uint64_t io_address{0xf0000000};
     uint64_t io_addr_mask{0xf0000000};
-
 protected:
     iss::status read_cache(phys_addr_t addr, unsigned, uint8_t *const);
     iss::status write_cache(phys_addr_t addr, unsigned, uint8_t const *const);
@@ -99,14 +96,14 @@ protected:
     std::function<mem_write_f> cache_mem_wr_delegate;
     std::unique_ptr<cache::cache> dcache_ptr;
     std::unique_ptr<cache::cache> icache_ptr;
-    size_t get_way_select() { return 0; }
+    size_t get_way_select() {
+        return 0;
+    }
 };
 
+
 template<typename BASE>
-inline wt_cache<BASE>::wt_cache(feature_config cfg)
+inline wt_cache<BASE>::wt_cache() {
-: BASE(cfg)
-, io_address{cfg.io_address}
-, io_addr_mask{cfg.io_addr_mask} {
     auto cb = base_class::replace_mem_access(
             [this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status { return read_cache(a, l,d);},
             [this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status { return write_cache(a, l,d);});
@@ -114,7 +111,8 @@ inline wt_cache<BASE>::wt_cache(feature_config cfg)
     cache_mem_wr_delegate = cb.second;
 }
 
-template <typename BASE> iss::status iss::arch::wt_cache<BASE>::read_cache(phys_addr_t a, unsigned l, uint8_t* const d) {
+template<typename BASE>
+iss::status iss::arch::wt_cache<BASE>::read_cache(phys_addr_t a, unsigned l, uint8_t* const d) {
     if(!icache_ptr) {
         icache_ptr.reset(new cache::cache(size, line_sz, ways));
         dcache_ptr.reset(new cache::cache(size, line_sz, ways));
@@ -145,7 +143,8 @@ template <typename BASE> iss::status iss::arch::wt_cache<BASE>::read_cache(phys_
         return cache_mem_rd_delegate(a, l, d);
 }
 
-template <typename BASE> iss::status iss::arch::wt_cache<BASE>::write_cache(phys_addr_t a, unsigned l, const uint8_t* const d) {
+template<typename BASE>
+iss::status iss::arch::wt_cache<BASE>::write_cache(phys_addr_t a, unsigned l, const uint8_t* const d) {
     if(!dcache_ptr)
         dcache_ptr.reset(new cache::cache(size, line_sz, ways));
     auto res = cache_mem_wr_delegate(a, l, d);
@@ -165,6 +164,8 @@ template <typename BASE> iss::status iss::arch::wt_cache<BASE>::write_cache(phys
     return res;
 }
 
+
+
 } // namespace arch
 } // namespace iss
 

src/iss/debugger/riscv_target_adapter.h

@@ -84,7 +84,8 @@ public:
      target byte order. If  register is not available
      corresponding bytes in avail_buf are 0, otherwise
      avail buf is 1 */
-    status read_single_register(unsigned int reg_no, std::vector<uint8_t>& buf, std::vector<uint8_t>& avail_buf) override;
+    status read_single_register(unsigned int reg_no, std::vector<uint8_t> &buf,
+            std::vector<uint8_t> &avail_buf) override;
 
     /* Write one register. buf is 4-byte aligned and it is in target byte
      order */
@@ -102,8 +103,8 @@ public:
 
     status process_query(unsigned int &mask, const rp_thread_ref &arg, rp_thread_info &info) override;
 
-    status thread_list_query(int first, const rp_thread_ref& arg, std::vector<rp_thread_ref>& result, size_t max_num, size_t& num,
+    status thread_list_query(int first, const rp_thread_ref &arg, std::vector<rp_thread_ref> &result, size_t max_num,
-                             bool& done) override;
+            size_t &num, bool &done) override;
 
     status current_thread_query(rp_thread_ref &thread) override;
 
@@ -123,7 +124,8 @@ public:
 
     status remove_break(break_type type, uint64_t addr, unsigned int length) override;
 
-    status resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread, std::function<void(unsigned)> stop_callback) override;
+    status resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
+            std::function<void(unsigned)> stop_callback) override;
 
     status target_xml_query(std::string &out_buf) override;
 
@@ -156,8 +158,9 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::is_thread_alive(rp_t
  * set if all threads are processed.
  */
 template <typename ARCH>
-status riscv_target_adapter<ARCH>::thread_list_query(int first, const rp_thread_ref& arg, std::vector<rp_thread_ref>& result,
+status riscv_target_adapter<ARCH>::thread_list_query(int first, const rp_thread_ref &arg,
-                                                     size_t max_num, size_t& num, bool& done) {
+        std::vector<rp_thread_ref> &result, size_t max_num, size_t &num,
+        bool &done) {
     if (first == 0) {
         result.clear();
         result.push_back(thread_idx);
@@ -173,7 +176,8 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::current_thread_query
     return Ok;
 }
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
+template <typename ARCH>
+status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t> &data, std::vector<uint8_t> &avail) {
     LOG(TRACE) << "reading target registers";
     // return idx<0?:;
     data.clear();
@@ -235,7 +239,8 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(cons
 }
 
 template <typename ARCH>
-status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
+status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t> &data,
+        std::vector<uint8_t> &avail) {
     if (reg_no < 65) {
         // auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename
         // arch::traits<ARCH>::reg_e>(reg_no))/8;
@@ -256,7 +261,8 @@ status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std
     return data.size() > 0 ? Ok : Err;
 }
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::write_single_register(unsigned int reg_no, const std::vector<uint8_t>& data) {
+template <typename ARCH>
+status riscv_target_adapter<ARCH>::write_single_register(unsigned int reg_no, const std::vector<uint8_t> &data) {
     if (reg_no < 65) {
         auto *reg_base = core->get_regs_base_ptr();
         auto reg_width = arch::traits<ARCH>::reg_bit_widths[static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)] / 8;
@@ -286,16 +292,21 @@ status riscv_target_adapter<ARCH>::process_query(unsigned int& mask, const rp_th
     return NotSupported;
 }
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::offsets_query(uint64_t& text, uint64_t& data, uint64_t& bss) {
+template <typename ARCH>
+status riscv_target_adapter<ARCH>::offsets_query(uint64_t &text, uint64_t &data, uint64_t &bss) {
     text = 0;
     data = 0;
     bss = 0;
     return Ok;
 }
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::crc_query(uint64_t addr, size_t len, uint32_t& val) { return NotSupported; }
+template <typename ARCH> status riscv_target_adapter<ARCH>::crc_query(uint64_t addr, size_t len, uint32_t &val) {
+    return NotSupported;
+}
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::raw_query(std::string in_buf, std::string& out_buf) { return NotSupported; }
+template <typename ARCH> status riscv_target_adapter<ARCH>::raw_query(std::string in_buf, std::string &out_buf) {
+    return NotSupported;
+}
 
 template <typename ARCH> status riscv_target_adapter<ARCH>::threadinfo_query(int first, std::string &out_buf) {
     if (first) {
@@ -306,7 +317,8 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::threadinfo_query(int
     return Ok;
 }
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::threadextrainfo_query(const rp_thread_ref& thread, std::string& out_buf) {
+template <typename ARCH>
+status riscv_target_adapter<ARCH>::threadextrainfo_query(const rp_thread_ref &thread, std::string &out_buf) {
     std::array<char, 20> buf;
     memset(buf.data(), 0, 20);
     sprintf(buf.data(), "%02x%02x%02x%02x%02x%02x%02x%02x%02x", 'R', 'u', 'n', 'n', 'a', 'b', 'l', 'e', 0);
@@ -328,8 +340,8 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(break_type
         auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
         auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
         target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
-        LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex << saddr.val
+        LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex
-                   << std::dec;
+                << saddr.val << std::dec;
         LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
         return Ok;
     }
@@ -345,7 +357,8 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(break_t
         auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
         unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
         if (handle) {
-            LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val << std::dec;
+            LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val
+                    << std::dec;
             // TODO: check length of addr range
             target_adapter_base::bp_lut.removeEntry(handle);
             LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
@@ -455,7 +468,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::target_xml_query(std
 </target>
 
  */
-} // namespace debugger
+}
-} // namespace iss
+}
 
 #endif /* _ISS_DEBUGGER_RISCV_TARGET_ADAPTER_H_ */

src/iss/factory.h

@@ -33,12 +33,12 @@
 #ifndef _ISS_FACTORY_H_
 #define _ISS_FACTORY_H_
 
-#include <algorithm>
-#include <functional>
 #include <iss/iss.h>
 #include <memory>
-#include <string>
 #include <unordered_map>
+#include <functional>
+#include <string>
+#include <algorithm>
 #include <vector>
 
 namespace iss {
@@ -46,7 +46,8 @@ namespace iss {
 using cpu_ptr = std::unique_ptr<iss::arch_if>;
 using vm_ptr= std::unique_ptr<iss::vm_if>;
 
-template <typename PLAT> std::tuple<cpu_ptr, vm_ptr> create_cpu(std::string const& backend, unsigned gdb_port) {
+template<typename PLAT>
+std::tuple<cpu_ptr, vm_ptr> create_cpu(std::string const& backend, unsigned gdb_port){
     using core_type = typename PLAT::core;
     core_type* lcpu = new PLAT();
     if(backend == "interp")
@@ -62,6 +63,7 @@ template <typename PLAT> std::tuple<cpu_ptr, vm_ptr> create_cpu(std::string cons
     return {nullptr, nullptr};
 }
 
+
 class core_factory {
     using cpu_ptr = std::unique_ptr<iss::arch_if>;
     using vm_ptr= std::unique_ptr<iss::vm_if>;
@@ -76,31 +78,33 @@ class core_factory {
     core_factory & operator=(const core_factory &) = delete;
 
 public:
-    static core_factory& instance() {
+    static core_factory & instance() { static core_factory bf; return bf; }
-        static core_factory bf;
-        return bf;
-    }
 
-    bool register_creator(const std::string& className, create_fn const& fn) {
+    bool register_creator(const std::string &, create_fn const&);
-        registry[className] = fn;
-        return true;
-    }
 
-    base_t create(std::string const& className, unsigned gdb_port = 0, void* init_data = nullptr) const {
+    base_t create(const std::string &, unsigned gdb_port=0, void* init_data=nullptr) const;
-        registry_t::const_iterator regEntry = registry.find(className);
-        if(regEntry != registry.end())
-            return regEntry->second(gdb_port, init_data);
-        return {nullptr, nullptr};
-    }
 
     std::vector<std::string> get_names() {
         std::vector<std::string> keys{registry.size()};
-        std::transform(std::begin(registry), std::end(registry), std::begin(keys),
+        std::transform(std::begin(registry), std::end(registry), std::begin(keys), [](std::pair<std::string, create_fn> const& p){
-                       [](std::pair<std::string, create_fn> const& p) { return p.first; });
+            return p.first;
+        });
         return keys;
     }
 };
 
-} // namespace iss
+inline bool core_factory::register_creator(const std::string & className, create_fn const& fn) {
+    registry[className] = fn;
+    return true;
+}
+
+inline core_factory::base_t core_factory::create(const std::string &className, unsigned gdb_port, void* data) const {
+    registry_t::const_iterator regEntry = registry.find(className);
+    if (regEntry != registry.end())
+        return regEntry->second(gdb_port, data);
+    return {nullptr, nullptr};
+}
+
+}
 
 #endif /* _ISS_FACTORY_H_ */

src/iss/plugin/README.md

@@ -1,8 +0,0 @@
-# pctrace
-
-Trace functionality to allow visualizing coverage in lcov and cachegrind tools. Use environment variables NOCOMPRES and REGDUMP to toggle functionality.
-- NOCOMPRES: any value turns off the LZ4 compression
-- REGDUMP: any value switches to tracing the registers instead. Also turns off compression.
-
-Known Bugs: 
-- currently does not work correctly with jit backends, the plugin cant tell if instructions are compressed. Additionaly the cost of instrs that raise a trap is not known. It takes the cost of the instrid -1 (0 at the moment).

src/iss/plugin/cycle_estimate.cpp

@@ -33,60 +33,68 @@
  ******************************************************************************/
 
 #include "cycle_estimate.h"
-#include <iss/plugin/calculator.h>
-#include <yaml-cpp/yaml.h>
 
-#include <fstream>
 #include <iss/arch_if.h>
 #include <util/logging.h>
+#include <rapidjson/document.h>
+#include <rapidjson/istreamwrapper.h>
+#include <rapidjson/writer.h>
+#include <rapidjson/stringbuffer.h>
+#include <rapidjson/ostreamwrapper.h>
+#include <rapidjson/error/en.h>
+#include <fstream>
 
+using namespace rapidjson;
 using namespace std;
 
 iss::plugin::cycle_estimate::cycle_estimate(string const& config_file_name)
 : instr_if(nullptr)
-, config_file_name(config_file_name) {}
+, config_file_name(config_file_name)
+{
+}
 
-iss::plugin::cycle_estimate::~cycle_estimate() = default;
+iss::plugin::cycle_estimate::~cycle_estimate() {
+}
 
 bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if& vm) {
     instr_if = vm.get_arch()->get_instrumentation_if();
-    assert(instr_if && "No instrumentation interface available but callback executed");
+    if(!instr_if) return false;
-    reg_base_ptr = reinterpret_cast<uint32_t*>(vm.get_arch()->get_regs_base_ptr());
-    if(!instr_if)
-        return false;
     const string  core_name = instr_if->core_type_name();
     if (config_file_name.length() > 0) {
-        std::ifstream is(config_file_name);
+        ifstream is(config_file_name);
         if (is.is_open()) {
             try {
-                auto root = YAML::LoadAll(is);
+                IStreamWrapper isw(is);
-                if(root.size() != 1) {
+                Document d;
-                    LOG(ERR) << "Too many root nodes in YAML file " << config_file_name;
+                ParseResult ok = d.ParseStream(isw);
+                if(ok) {
+                    Value& val = d[core_name.c_str()];
+                    if(val.IsArray()){
+                        delays.reserve(val.Size());
+                        for (auto it = val.Begin(); it != val.End(); ++it) {
+                            auto& name = (*it)["name"];
+                            auto& size = (*it)["size"];
+                            auto& delay = (*it)["delay"];
+                            auto& branch = (*it)["branch"];
+                            if(delay.IsArray()) {
+                                auto dt = delay[0].Get<unsigned>();
+                                auto dnt = delay[1].Get<unsigned>();
+                                delays.push_back(instr_desc{size.Get<unsigned>(), dt, dnt, branch.Get<bool>()});
+                            } else if(delay.Is<unsigned>()) {
+                                auto d = delay.Get<unsigned>();
+                                delays.push_back(instr_desc{size.Get<unsigned>(), d, d, branch.Get<bool>()});
+                            } else
+                                throw runtime_error("JSON parse error");
                        }
-                for(auto p : root[0]) {
-                    auto isa_subset = p.first;
-                    auto instructions = p.second;
-                    for(auto const& instr : instructions) {
-                        auto idx = instr.second["index"].as<unsigned>();
-                        if(delays.size() <= idx)
-                            delays.resize(idx + 1);
-                        auto& res = delays[idx];
-                        res.is_branch = instr.second["branch"].as<bool>();
-                        auto delay = instr.second["delay"];
-                        if(delay.IsSequence()) {
-                            res.not_taken = delay[0].as<uint64_t>();
-                            res.taken = delay[1].as<uint64_t>();
                     } else {
-                            try {
+                        LOG(ERR)<<"plugin cycle_estimate: could not find an entry for "<<core_name<<" in JSON file"<<endl;
-                                res.not_taken = delay.as<uint64_t>();
+                        return false;
-                                res.taken = res.not_taken;
-                            } catch(const YAML::BadConversion& e) {
-                                res.f = iss::plugin::calculator(reg_base_ptr, delay.as<std::string>());
                    }
+                } else {
+                    LOG(ERR)<<"plugin cycle_estimate: could not parse in JSON file at "<< ok.Offset()<<": "<<GetParseError_En(ok.Code())<<endl;
+                    return false;
                }
-                    }
+            } catch (runtime_error &e) {
-                }
-            } catch(YAML::ParserException& e) {
                 LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
                 return false;
             }
@@ -96,19 +104,15 @@ bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if&
         }
     }
     return true;
+
 }
 
 void iss::plugin::cycle_estimate::callback(instr_info_t instr_info) {
-    size_t instr_id = instr_info.instr_id;
+    assert(instr_if && "No instrumentation interface available but callback executed");
-    auto& entry = instr_id < delays.size() ? delays[instr_id] : illegal_desc;
+    auto entry = delays[instr_info.instr_id];
-    if(instr_info.phase_id == PRE_SYNC) {
+    bool taken = instr_if->is_branch_taken();
-        if(entry.f)
+    if (taken && (entry.taken > 1))
-            current_delay = entry.f(instr_if->get_instr_word());
+        instr_if->update_last_instr_cycles(entry.taken);
-    } else {
+    else if (entry.not_taken > 1)
-        if(!entry.f)
+        instr_if->update_last_instr_cycles(entry.not_taken);
-            current_delay = instr_if->is_branch_taken() ? entry.taken : entry.not_taken;
-        if(current_delay > 1)
-            instr_if->update_last_instr_cycles(current_delay);
-        current_delay = 1;
-    }
 }

src/iss/plugin/cycle_estimate.h

@@ -37,7 +37,6 @@
 
 #include "iss/instrumentation_if.h"
 #include "iss/vm_plugin.h"
-#include <functional>
 #include <string>
 #include <unordered_map>
 #include <vector>
@@ -47,13 +46,18 @@ namespace iss {
 namespace plugin {
 
 class cycle_estimate: public vm_plugin {
-    struct instr_desc {
+	BEGIN_BF_DECL(instr_desc, uint32_t)
-        size_t size{0};
+		BF_FIELD(taken, 24, 8)
-        bool is_branch{false};
+		BF_FIELD(not_taken, 16, 8)
-        unsigned not_taken{1};
+        BF_FIELD(is_branch, 8, 8)
-        unsigned taken{1};
+        BF_FIELD(size, 0, 8)
-        std::function<unsigned(uint64_t)> f;
+		instr_desc(uint32_t size, uint32_t taken, uint32_t not_taken, bool branch): instr_desc() {
-    };
+			this->size=size;
+			this->taken=taken;
+			this->not_taken=not_taken;
+			this->is_branch=branch;
+		}
+	END_BF_DECL();
 
 public:
     cycle_estimate() = delete;
@@ -72,16 +76,13 @@ public:
 
     bool registration(const char *const version, vm_if &arch) override;
 
-    sync_type get_sync() override { return ALL_SYNC; };
+    sync_type get_sync() override { return POST_SYNC; };
 
     void callback(instr_info_t instr_info) override;
 
 private:
-    iss::instrumentation_if* instr_if{nullptr};
+    iss::instrumentation_if *instr_if;
-    uint32_t* reg_base_ptr{nullptr};
-    instr_desc illegal_desc{};
     std::vector<instr_desc> delays;
-    unsigned current_delay{0};
     struct pair_hash {
         size_t operator()(const std::pair<uint64_t, uint64_t> &p) const {
             std::hash<uint64_t> hash;
@@ -91,7 +92,7 @@ private:
     std::unordered_map<std::pair<uint64_t, uint64_t>, uint64_t, pair_hash> blocks;
     std::string config_file_name;
 };
-} // namespace plugin
+}
-} // namespace iss
+}
 
 #endif /* _ISS_PLUGIN_CYCLE_ESTIMATE_H_ */

src/iss/plugin/instruction_count.cpp

@@ -34,41 +34,18 @@
 
 #include "instruction_count.h"
 #include <iss/instrumentation_if.h>
-#include <yaml-cpp/yaml.h>
 
-#include <fstream>
 #include <iss/arch_if.h>
 #include <util/logging.h>
+#include <fstream>
 
 iss::plugin::instruction_count::instruction_count(std::string config_file_name) {
     if (config_file_name.length() > 0) {
         std::ifstream is(config_file_name);
         if (is.is_open()) {
             try {
-                auto root = YAML::LoadAll(is);
+                is >> root;
-                if(root.size() != 1) {
+            } catch (Json::RuntimeError &e) {
-                    LOG(ERR) << "Too many rro nodes in YAML file " << config_file_name;
-                }
-                for(auto p : root[0]) {
-                    auto isa_subset = p.first;
-                    auto instructions = p.second;
-                    for(auto const& instr : instructions) {
-                        instr_delay res;
-                        res.instr_name = instr.first.as<std::string>();
-                        res.size = instr.second["encoding"].as<std::string>().size() - 2; // not counting 0b
-                        auto delay = instr.second["delay"];
-                        if(delay.IsSequence()) {
-                            res.not_taken_delay = delay[0].as<uint64_t>();
-                            res.taken_delay = delay[1].as<uint64_t>();
-                        } else {
-                            res.not_taken_delay = delay.as<uint64_t>();
-                            res.taken_delay = res.not_taken_delay;
-                        }
-                        delays.push_back(std::move(res));
-                    }
-                }
-                rep_counts.resize(delays.size());
-            } catch(YAML::ParserException& e) {
                 LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
             }
         } else {
@@ -80,7 +57,7 @@ iss::plugin::instruction_count::instruction_count(std::string config_file_name)
 iss::plugin::instruction_count::~instruction_count() {
 	size_t idx=0;
 	for(auto it:delays){
-        if(rep_counts[idx] > 0 && it.instr_name.find("__" != 0))
+		if(rep_counts[idx]>0)
 			LOG(INFO)<<it.instr_name<<";"<<rep_counts[idx];
 		idx++;
 	}
@@ -88,9 +65,31 @@ iss::plugin::instruction_count::~instruction_count() {
 
 bool iss::plugin::instruction_count::registration(const char* const version, vm_if& vm) {
     auto instr_if = vm.get_arch()->get_instrumentation_if();
-    if(!instr_if)
+    if(!instr_if) return false;
-        return false;
+	const std::string  core_name = instr_if->core_type_name();
+    Json::Value &val = root[core_name];
+    if(!val.isNull() && val.isArray()){
+    	delays.reserve(val.size());
+    	for(auto it:val){
+    		auto name = it["name"];
+    		auto size = it["size"];
+    		auto delay = it["delay"];
+    		if(!name.isString() || !size.isUInt() || !(delay.isUInt() || delay.isArray())) throw std::runtime_error("JSON parse error");
+    		if(delay.isUInt()){
+				const instr_delay entry{name.asCString(), size.asUInt(), delay.asUInt(), 0};
+				delays.push_back(entry);
+    		} else {
+				const instr_delay entry{name.asCString(), size.asUInt(), delay[0].asUInt(), delay[1].asUInt()};
+				delays.push_back(entry);
+    		}
+    	}
+    	rep_counts.resize(delays.size());
+    } else {
+        LOG(ERR)<<"plugin instruction_count: could not find an entry for "<<core_name<<" in JSON file"<<std::endl;
+    }
 	return true;
 }
 
-void iss::plugin::instruction_count::callback(instr_info_t instr_info) { rep_counts[instr_info.instr_id]++; }
+void iss::plugin::instruction_count::callback(instr_info_t instr_info) {
+	rep_counts[instr_info.instr_id]++;
+}

src/iss/plugin/instruction_count.h

@@ -36,8 +36,8 @@
 #define _ISS_PLUGIN_INSTRUCTION_COUNTER_H_
 
 #include <iss/vm_plugin.h>
+#include <json/json.h>
 #include <string>
-#include <vector>
 
 namespace iss {
 namespace plugin {
@@ -72,10 +72,11 @@ public:
     void callback(instr_info_t) override;
 
 private:
+    Json::Value root;
     std::vector<instr_delay> delays;
     std::vector<uint64_t> rep_counts;
 };
-} // namespace plugin
+}
-} // namespace iss
+}
 
 #endif /* _ISS_PLUGIN_INSTRUCTION_COUNTER_H_ */

src/iss/plugin/pctrace.cpp

@@ -0,0 +1,214 @@
+/*******************************************************************************
+ * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Contributors:
+ *       alex.com - initial implementation
+ ******************************************************************************/
+
+#include <iss/arch_if.h>
+#include <iss/plugin/pctrace.h>
+#include <util/logging.h>
+#include <util/ities.h>
+#include <rapidjson/document.h>
+#include <rapidjson/istreamwrapper.h>
+#include <rapidjson/writer.h>
+#include <rapidjson/stringbuffer.h>
+#include <rapidjson/ostreamwrapper.h>
+#include <rapidjson/error/en.h>
+#include <fstream>
+#include <iostream>
+#ifdef WITH_LZ4
+#include <lz4frame.h>
+#endif
+
+namespace iss {
+namespace plugin {
+
+using namespace rapidjson;
+using namespace std;
+
+#ifdef WITH_LZ4
+class lz4compress_steambuf: public std::streambuf {
+public:
+    lz4compress_steambuf(const lz4compress_steambuf&) = delete;
+    lz4compress_steambuf& operator=(const lz4compress_steambuf&) = delete;
+    lz4compress_steambuf(std::ostream &sink, size_t buf_size)
+    : sink(sink)
+    , src_buf(buf_size)
+    , dest_buf(LZ4F_compressBound(buf_size, nullptr))
+    {
+        auto errCode = LZ4F_createCompressionContext(&ctx, LZ4F_VERSION);
+        if (LZ4F_isError(errCode) != 0)
+            throw std::runtime_error(std::string("Failed to create LZ4 context: ") + LZ4F_getErrorName(errCode));
+        size_t ret = LZ4F_compressBegin(ctx, &dest_buf.front(), dest_buf.capacity(), nullptr);
+        if (LZ4F_isError(ret) != 0)
+            throw std::runtime_error(std::string("Failed to start LZ4 compression: ") + LZ4F_getErrorName(ret));
+        setp(src_buf.data(), src_buf.data() + src_buf.size() - 1);
+        sink.write(dest_buf.data(), ret);
+    }
+
+    ~lz4compress_steambuf() {
+        close();
+    }
+
+    void close() {
+        if (closed)
+            return;
+        sync();
+        auto ret = LZ4F_compressEnd(ctx, dest_buf.data(), dest_buf.capacity(), nullptr);
+        if (LZ4F_isError(ret) != 0)
+            throw std::runtime_error(std::string("Failed to finish LZ4 compression: ") + LZ4F_getErrorName(ret));
+        sink.write(dest_buf.data(), ret);
+        LZ4F_freeCompressionContext(ctx);
+        closed = true;
+    }
+
+private:
+    int_type overflow(int_type ch) override {
+        compress_and_write();
+        *pptr() = static_cast<char_type>(ch);
+        pbump(1);
+        return ch;
+    }
+
+    int_type sync() override {
+        compress_and_write();
+        return 0;
+    }
+
+    void compress_and_write() {
+        if (closed)
+            throw std::runtime_error("Cannot write to closed stream");
+        if(auto orig_size = pptr() - pbase()){
+            auto ret = LZ4F_compressUpdate(ctx, dest_buf.data(), dest_buf.capacity(), pbase(), orig_size, nullptr);
+            if (LZ4F_isError(ret) != 0)
+                throw std::runtime_error(std::string("LZ4 compression failed: ") + LZ4F_getErrorName(ret));
+            if(ret) sink.write(dest_buf.data(), ret);
+            pbump(-orig_size);
+        }
+    }
+
+    std::ostream &sink;
+    std::vector<char> src_buf;
+    std::vector<char> dest_buf;
+    LZ4F_compressionContext_t ctx{ nullptr };
+    bool closed{ false };
+};
+#endif
+
+pctrace::pctrace(std::string const &filename)
+: instr_if(nullptr)
+, filename(filename)
+, output("output.trc")
+#ifdef WITH_LZ4
+, strbuf(new lz4compress_steambuf(output, 4096))
+, ostr(strbuf.get())
+#endif
+{ }
+
+pctrace::~pctrace() { }
+
+bool pctrace::registration(const char *const version, vm_if& vm) {
+    instr_if = vm.get_arch()->get_instrumentation_if();
+    if(!instr_if) return false;
+    const string  core_name = instr_if->core_type_name();
+    if (filename.length() > 0) {
+        ifstream is(filename);
+        if (is.is_open()) {
+            try {
+                IStreamWrapper isw(is);
+                Document d;
+                ParseResult ok = d.ParseStream(isw);
+                if(ok) {
+                    Value& val = d[core_name.c_str()];
+                    if(val.IsArray()){
+                        delays.reserve(val.Size());
+                        for (auto it = val.Begin(); it != val.End(); ++it) {
+                            auto& name = (*it)["name"];
+                            auto& size = (*it)["size"];
+                            auto& delay = (*it)["delay"];
+                            auto& branch = (*it)["branch"];
+                            if(delay.IsArray()) {
+                                auto dt = delay[0].Get<unsigned>();
+                                auto dnt = delay[1].Get<unsigned>();
+                                delays.push_back(instr_desc{size.Get<unsigned>(), dt, dnt, branch.Get<bool>()});
+                            } else if(delay.Is<unsigned>()) {
+                                auto d = delay.Get<unsigned>();
+                                delays.push_back(instr_desc{size.Get<unsigned>(), d, d, branch.Get<bool>()});
+                            } else
+                                throw runtime_error("JSON parse error");
+
+                        }
+                    } else {
+                        LOG(ERR)<<"plugin cycle_estimate: could not find an entry for "<<core_name<<" in JSON file"<<endl;
+                        return false;
+                    }
+                } else {
+                    LOG(ERR)<<"plugin cycle_estimate: could not parse in JSON file at "<< ok.Offset()<<": "<<GetParseError_En(ok.Code())<<endl;
+                    return false;
+                }
+            } catch (runtime_error &e) {
+                LOG(ERR) << "Could not parse input file " << filename << ", reason: " << e.what();
+                return false;
+            }
+        } else {
+            LOG(ERR) << "Could not open input file " << filename;
+            return false;
+        }
+    }
+    return true;
+}
+
+void pctrace::callback(instr_info_t iinfo) {
+    auto delay = 0;
+    size_t id = iinfo.instr_id;
+    auto entry = delays[id];
+    auto instr = instr_if->get_instr_word();
+    auto call = id==65 || id ==86 || ((id==2 || id==3) && bit_sub<7,5>(instr)!=0) ;//not taking care of tail calls (jalr with loading x6)
+    bool taken = instr_if->is_branch_taken();
+    bool compressed = (instr&0x3)!=0x3;
+    if (taken) {
+        delay = entry.taken;
+        if(entry.taken > 1)
+            instr_if->update_last_instr_cycles(entry.taken);
+    } else {
+        delay = entry.not_taken;
+        if (entry.not_taken > 1)
+            instr_if->update_last_instr_cycles(entry.not_taken);
+    }
+#ifndef WITH_LZ4
+    output<<std::hex <<"0x" << instr_if->get_pc() <<"," << delay <<"," << call<<","<<(compressed?2:4) <<"\n";
+#else
+    auto rdbuf=ostr.rdbuf();
+    ostr<<std::hex <<"0x" << instr_if->get_pc() <<"," << delay <<"," << call<<","<<(compressed?2:4) <<"\n";
+#endif
+}
+}
+}

src/iss/plugin/pctrace.h

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2021 MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -28,63 +28,75 @@
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  *
- *******************************************************************************/
+ * Contributors:
+ *       eyck@minres.com - initial API and implementation
+ ******************************************************************************/
 
-#ifndef _ISS_FACTORY_H_
+#ifndef _ISS_PLUGIN_COV_H_
-#define _ISS_FACTORY_H_
+#define _ISS_PLUGIN_COV_H_
 
-#include "sc_core_adapter_if.h"
+#include <iss/vm_plugin.h>
-#include <algorithm>
+#include "iss/instrumentation_if.h"
-#include <functional>
+#include <json/json.h>
-#include <iss/iss.h>
-#include <memory>
 #include <string>
-#include <unordered_map>
+#include <fstream>
-#include <vector>
 
-namespace sysc {
 
-using sc_cpu_ptr = std::unique_ptr<sc_core_adapter_if>;
+namespace iss {
-using vm_ptr = std::unique_ptr<iss::vm_if>;
+namespace plugin {
+class lz4compress_steambuf;
+class pctrace : public iss::vm_plugin {
+    struct instr_delay {
+        std::string instr_name;
+        size_t size;
+        size_t not_taken_delay;
+        size_t taken_delay;
+    };
+    BEGIN_BF_DECL(instr_desc, uint32_t)
+        BF_FIELD(taken, 24, 8)
+        BF_FIELD(not_taken, 16, 8)
+        BF_FIELD(is_branch, 8, 8)
+        BF_FIELD(size, 0, 8)
+        instr_desc(uint32_t size, uint32_t taken, uint32_t not_taken, bool branch): instr_desc() {
+            this->size=size;
+            this->taken=taken;
+            this->not_taken=not_taken;
+            this->is_branch=branch;
+        }
+    END_BF_DECL();
 
-class iss_factory {
 public:
-    using base_t = std::tuple<sc_cpu_ptr, vm_ptr>;
-    using create_fn = std::function<base_t(unsigned, void*)>;
-    using registry_t = std::unordered_map<std::string, create_fn>;
 
-    iss_factory() = default;
+    pctrace(const pctrace &) = delete;
-    iss_factory(const iss_factory&) = delete;
-    iss_factory& operator=(const iss_factory&) = delete;
 
-    static iss_factory& instance() {
+    pctrace(const pctrace &&) = delete;
-        static iss_factory bf;
-        return bf;
-    }
 
-    bool register_creator(const std::string& className, create_fn const& fn) {
+    pctrace(std::string const &);
-        registry[className] = fn;
-        return true;
-    }
 
-    base_t create(std::string const& className, unsigned gdb_port = 0, void* init_data = nullptr) const {
+    virtual ~pctrace();
-        registry_t::const_iterator regEntry = registry.find(className);
-        if(regEntry != registry.end())
-            return regEntry->second(gdb_port, init_data);
-        return {nullptr, nullptr};
-    }
 
-    std::vector<std::string> get_names() {
+    pctrace &operator=(const pctrace &) = delete;
-        std::vector<std::string> keys{registry.size()};
+
-        std::transform(std::begin(registry), std::end(registry), std::begin(keys),
+    pctrace &operator=(const pctrace &&) = delete;
-                       [](std::pair<std::string, create_fn> const& p) { return p.first; });
+
-        return keys;
+    bool registration(const char *const version, vm_if &arch) override;
-    }
+
+    sync_type get_sync() override { return POST_SYNC; };
+
+    void callback(instr_info_t) override;
 
 private:
-    registry_t registry;
+    iss::instrumentation_if *instr_if  {nullptr};
+    std::ofstream output;
+#ifdef WITH_LZ4
+    std::unique_ptr<lz4compress_steambuf> strbuf;
+    std::ostream ostr;
+#endif
+    std::string filename;
+    std::vector<instr_desc> delays;
+    bool jumped{false}, first{true};
 };
+}
+}
 
-} // namespace sysc
+#endif /* _ISS_PLUGIN_COV_H_ */
-
-#endif /* _ISS_FACTORY_H_ */

src/main.cpp

@@ -30,20 +30,21 @@
  *
  *******************************************************************************/
 
-#include <array>
 #include <iostream>
-#include <iss/factory.h>
 #include <vector>
+#include <array>
+#include <iss/factory.h>
 
-#include "iss/arch/tgc_mapper.h"
 #include <boost/lexical_cast.hpp>
 #include <boost/program_options.hpp>
+#include "iss/arch/tgc_mapper.h"
 #ifdef WITH_LLVM
-#include <iss/llvm/jit_init.h>
+#include <iss/llvm/jit_helper.h>
 #endif
+#include <iss/log_categories.h>
 #include "iss/plugin/cycle_estimate.h"
 #include "iss/plugin/instruction_count.h"
-#include <iss/log_categories.h>
+#include "iss/plugin/pctrace.h"
 #ifndef WIN32
 #include <iss/plugin/loader.h>
 #endif
@@ -73,14 +74,14 @@ int main(int argc, char* argv[]) {
         ("mem,m", po::value<std::string>(), "the memory input file")
         ("plugin,p", po::value<std::vector<std::string>>(), "plugin to activate")
         ("backend", po::value<std::string>()->default_value("interp"), "the ISS backend to use, options are: interp, tcc")
-        ("isa", po::value<std::string>()->default_value("tgc5c"), "core or isa name to use for simulation, use '?' to get list");
+        ("isa", po::value<std::string>()->default_value("tgc_c"), "isa to use for simulation");
     // clang-format on
     auto parsed = po::command_line_parser(argc, argv).options(desc).allow_unregistered().run();
     try {
         po::store(parsed, clim); // can throw
         // --help option
         if (clim.count("help")) {
-            std::cout << "DBT-RISE-TGC simulator for TGC RISC-V cores" << std::endl << desc << std::endl;
+            std::cout << "DBT-RISE-RiscV simulator for RISC-V" << std::endl << desc << std::endl;
             return 0;
         }
         po::notify(clim); // throws on error, so do after help in case
@@ -118,15 +119,13 @@ int main(int argc, char* argv[]) {
         iss::cpu_ptr cpu{nullptr};
         std::string isa_opt(clim["isa"].as<std::string>());
         if(isa_opt.size()==0 || isa_opt == "?") {
-            auto list = f.get_names();
+            std::cout<<"Available cores: "<<util::join(f.get_names(), ", ")<<std::endl;
-            std::sort(std::begin(list), std::end(list));
-            std::cout << "Available implementations (core|platform|backend):\n  - " << util::join(list, "\n  - ") << std::endl;
             return 0;
         } else if (isa_opt.find('|') != std::string::npos) {
             std::tie(cpu, vm) = f.create(isa_opt+"|"+clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
         } else {
             auto base_isa = isa_opt.substr(0, 5);
-            if(base_isa == "tgc5d" || base_isa == "tgc5e") {
+            if(base_isa=="tgc_d" || base_isa=="tgc_e") {
                 isa_opt += "|mu_p_clic_pmp|"+clim["backend"].as<std::string>();
             } else {
                 isa_opt += "|m_p|"+clim["backend"].as<std::string>();
@@ -150,7 +149,6 @@ int main(int argc, char* argv[]) {
                     plugin_name = opt_val.substr(0, found);
                     arg = opt_val.substr(found + 1, opt_val.size());
                 }
-#if defined(WITH_PLUGINS)
                 if (plugin_name == "ic") {
                     auto *ic_plugin = new iss::plugin::instruction_count(arg);
                     vm->register_plugin(*ic_plugin);
@@ -159,10 +157,12 @@ int main(int argc, char* argv[]) {
                     auto *ce_plugin = new iss::plugin::cycle_estimate(arg);
                     vm->register_plugin(*ce_plugin);
                     plugin_list.push_back(ce_plugin);
-                } else
+                } else if (plugin_name == "pctrace") {
-#endif
+                    auto *plugin = new iss::plugin::pctrace(arg);
-                {
+                    vm->register_plugin(*plugin);
-#if !defined(WIN32)
+                    plugin_list.push_back(plugin);
+               } else {
+#ifndef WIN32
                     std::vector<char const*> a{};
                     if(arg.length())
                         a.push_back({arg.c_str()});
@@ -196,13 +196,11 @@ int main(int argc, char* argv[]) {
         if (clim.count("elf"))
             for (std::string input : clim["elf"].as<std::vector<std::string>>()) {
                 auto start_addr = vm->get_arch()->load_file(input);
-                if(start_addr.second)
+                if (start_addr.second) start_address = start_addr.first;
-                    start_address = start_addr.first;
             }
         for (std::string input : args) {
             auto start_addr = vm->get_arch()->load_file(input); // treat remaining arguments as elf files
-            if(start_addr.second)
+            if (start_addr.second) start_address = start_addr.first;
-                start_address = start_addr.first;
         }
         if (clim.count("reset")) {
             auto str = clim["reset"].as<std::string>();
@@ -212,7 +210,8 @@ int main(int argc, char* argv[]) {
         auto cycles = clim["instructions"].as<uint64_t>();
         res = vm->start(cycles, dump);
     } catch (std::exception &e) {
-        LOG(ERR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit" << std::endl;
+        LOG(ERR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit"
+                   << std::endl;
         res = 2;
     }
     // cleanup to let plugins report of needed

src/sysc/core_complex.cpp

@@ -37,28 +37,25 @@
 #include <iss/debugger/target_adapter_if.h>
 #include <iss/iss.h>
 #include <iss/vm_types.h>
-#include "iss_factory.h"
 #ifndef WIN32
 #include <iss/plugin/loader.h>
 #endif
-#include "sc_core_adapter_if.h"
+#include "core_complex.h"
 #include <iss/arch/tgc_mapper.h>
 #include <scc/report.h>
 #include <util/ities.h>
 #include <iostream>
 #include <sstream>
 #include <array>
-#include <numeric>
 #include <iss/plugin/cycle_estimate.h>
 #include <iss/plugin/instruction_count.h>
+#include <iss/plugin/pctrace.h>
 
 // clang-format on
 
 #define STR(X) #X
 #define CREATE_CORE(CN) \
-    if(type == STR(CN)) {                                                                                                                  \
+if (type == STR(CN)) { std::tie(cpu, vm) = create_core<CN ## _plat_type>(backend, gdb_port, hart_id); } else
-        std::tie(cpu, vm) = create_core<CN##_plat_type>(backend, gdb_port, hart_id);                                                       \
-    } else
 
 #ifdef HAS_SCV
 #include <scv.h>
@@ -88,10 +85,138 @@ using namespace sc_core;
 
 namespace {
 iss::debugger::encoder_decoder encdec;
-std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
-} // namespace
 
-int cmd_sysc(int argc, char* argv[], debugger::out_func of, debugger::data_func df, debugger::target_adapter_if* tgt_adapter) {
+std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
+}
+
+template<typename PLAT>
+class core_wrapper_t : public PLAT {
+public:
+    using reg_t       = typename arch::traits<typename PLAT::core>::reg_t;
+    using phys_addr_t = typename arch::traits<typename PLAT::core>::phys_addr_t;
+    using heart_state_t = typename PLAT::hart_state_type;
+    core_wrapper_t(core_complex *owner)
+    : owner(owner) { }
+
+    uint32_t get_mode() { return this->reg.PRIV; }
+
+    inline void set_interrupt_execution(bool v) { this->interrupt_sim = v?1:0; }
+
+    inline bool get_interrupt_execution() { return this->interrupt_sim; }
+
+    heart_state_t &get_state() { return this->state; }
+
+    void notify_phase(iss::arch_if::exec_phase p) override {
+        if (p == iss::arch_if::ISTART)
+            owner->sync(this->instr_if.get_total_cycles());
+    }
+
+    sync_type needed_sync() const override { return PRE_SYNC; }
+
+    void disass_output(uint64_t pc, const std::string instr) override {
+        if (!owner->disass_output(pc, instr)) {
+            std::stringstream s;
+            s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0')
+              << std::setw(sizeof(reg_t) * 2) << (reg_t)this->state.mstatus << std::dec << ";c:"
+              << this->reg.icount + this->cycle_offset << "]";
+            SCCDEBUG(owner->name())<<"disass: "
+                << "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
+                << std::setfill(' ') << std::left << instr << s.str();
+        }
+    };
+
+    status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data) override {
+        if (addr.access && access_type::DEBUG)
+            return owner->read_mem_dbg(addr.val, length, data) ? Ok : Err;
+        else {
+            return owner->read_mem(addr.val, length, data, is_fetch(addr.access)) ? Ok : Err;
+        }
+    }
+
+    status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data) override {
+        if (addr.access && access_type::DEBUG)
+            return owner->write_mem_dbg(addr.val, length, data) ? Ok : Err;
+        else {
+            auto res = owner->write_mem(addr.val, length, data) ? Ok : Err;
+            // clear MTIP on mtimecmp write
+            if (addr.val == 0x2004000) {
+                reg_t val;
+                this->read_csr(arch::mip, val);
+                if (val & (1ULL << 7)) this->write_csr(arch::mip, val & ~(1ULL << 7));
+            }
+            return res;
+        }
+    }
+
+    status read_csr(unsigned addr, reg_t &val) override {
+#ifndef CWR_SYSTEMC
+        if((addr==arch::time || addr==arch::timeh) && owner->mtime_o.get_interface(0)){
+            uint64_t time_val;
+            bool ret = owner->mtime_o->nb_peek(time_val);
+            if (addr == iss::arch::time) {
+                val = static_cast<reg_t>(time_val);
+            } else if (addr == iss::arch::timeh) {
+                if (sizeof(reg_t) != 4) return iss::Err;
+                val = static_cast<reg_t>(time_val >> 32);
+            }
+            return ret?Ok:Err;
+#else
+		if((addr==arch::time || addr==arch::timeh)){
+			uint64_t time_val = owner->mtime_i.read();
+			if (addr == iss::arch::time) {
+				val = static_cast<reg_t>(time_val);
+			} else if (addr == iss::arch::timeh) {
+				if (sizeof(reg_t) != 4) return iss::Err;
+				val = static_cast<reg_t>(time_val >> 32);
+			}
+			return Ok;
+#endif
+        } else {
+            return PLAT::read_csr(addr, val);
+        }
+    }
+
+    void wait_until(uint64_t flags) override {
+        SCCDEBUG(owner->name()) << "Sleeping until interrupt";
+        while(this->reg.pending_trap == 0 && (this->csr[arch::mip] & this->csr[arch::mie]) == 0) {
+            sc_core::wait(wfi_evt);
+        }
+        PLAT::wait_until(flags);
+    }
+
+    void local_irq(short id, bool value) {
+        reg_t mask = 0;
+        switch (id) {
+        case 3: // SW
+            mask = 1 << 3;
+            break;
+        case 7: // timer
+            mask = 1 << 7;
+            break;
+        case 11: // external
+            mask = 1 << 11;
+            break;
+        default:
+            if(id>15) mask = 1 << id;
+            break;
+        }
+        if (value) {
+            this->csr[arch::mip] |= mask;
+            wfi_evt.notify();
+        } else
+            this->csr[arch::mip] &= ~mask;
+        this->check_interrupt();
+        if(value)
+            SCCTRACE(owner->name()) << "Triggering interrupt " << id << " Pending trap: " << this->reg.pending_trap;
+    }
+
+private:
+    core_complex *const owner;
+    sc_event wfi_evt;
+};
+
+int cmd_sysc(int argc, char *argv[], debugger::out_func of, debugger::data_func df,
+             debugger::target_adapter_if *tgt_adapter) {
     if (argc > 1) {
         if (strcasecmp(argv[1], "print_time") == 0) {
             std::string t = sc_time_stamp().to_string();
@@ -125,15 +250,11 @@ using vm_ptr = std::unique_ptr<iss::vm_if>;
 
 class core_wrapper {
 public:
-    core_wrapper(core_complex* owner)
+    core_wrapper(core_complex *owner) : owner(owner) { }
-    : owner(owner) {}
 
     void reset(uint64_t addr){vm->reset(addr);}
-    inline void start(bool dump = false) { vm->start(std::numeric_limits<uint64_t>::max(), dump); }
+    inline void start(){vm->start();}
-    inline std::pair<uint64_t, bool> load_file(std::string const& name) {
+    inline std::pair<uint64_t, bool> load_file(std::string const& name){ return cpu->load_file(name);};
-        iss::arch_if* cc = cpu->get_arch_if();
-        return cc->load_file(name);
-    };
 
     std::function<unsigned(void)> get_mode;
     std::function<uint64_t(void)> get_state;
@@ -141,49 +262,58 @@ public:
     std::function<void(bool)> set_interrupt_execution;
     std::function<void(short, bool)> local_irq;
 
-    void create_cpu(std::string const& type, std::string const& backend, unsigned gdb_port, uint32_t hart_id) {
+    template<typename PLAT>
-        auto& f = sysc::iss_factory::instance();
+    std::tuple<cpu_ptr, vm_ptr> create_core(std::string const& backend, unsigned gdb_port, uint32_t hart_id){
-        if(type.size() == 0 || type == "?") {
+        auto* lcpu = new core_wrapper_t<PLAT>(owner);
-            std::cout << "Available cores: " << util::join(f.get_names(), ", ") << std::endl;
+        lcpu->set_mhartid(hart_id);
-            sc_core::sc_stop();
+        get_mode = [lcpu]() { return lcpu->get_mode(); };
-        } else if(type.find('|') != std::string::npos) {
+        get_state = [lcpu]() { return lcpu->get_state().mstatus.backing.val; };
-            std::tie(cpu, vm) = f.create(type + "|" + backend);
+        get_interrupt_execution = [lcpu]() { return lcpu->get_interrupt_execution(); };
-        } else {
+        set_interrupt_execution = [lcpu](bool b) { return lcpu->set_interrupt_execution(b); };
-            auto base_isa = type.substr(0, 5);
+        local_irq = [lcpu](short s, bool b) { return lcpu->local_irq(s, b); };
-            if(base_isa == "tgc5d" || base_isa == "tgc5e") {
+        if(backend == "interp")
-                std::tie(cpu, vm) = f.create(type + "|mu_p_clic_pmp|" + backend, gdb_port, owner);
+            return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(static_cast<typename PLAT::core*>(lcpu), gdb_port)}};
-            } else {
+#ifdef WITH_LLVM
-                std::tie(cpu, vm) = f.create(type + "|m_p|" + backend, gdb_port, owner);
+        if(backend == "llvm")
+            return {cpu_ptr{lcpu}, vm_ptr{iss::llvm::create(lcpu, gdb_port)}};
+#endif
+#ifdef WITH_TCC
+        if(backend == "tcc")
+    s        return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
+#endif
+        return {nullptr, nullptr};
     }
-        }
-        if(!cpu) {
-            SCCFATAL() << "Could not create cpu for isa " << type << " and backend " << backend;
-        }
-        if(!vm) {
-            SCCFATAL() << "Could not create vm for isa " << type << " and backend " << backend;
-        }
-        auto* sc_cpu_if = reinterpret_cast<sc_core_adapter_if*>(cpu.get());
-        sc_cpu_if->set_mhartid(hart_id);
-        get_mode = [sc_cpu_if]() { return sc_cpu_if->get_mode(); };
-        get_state = [sc_cpu_if]() { return sc_cpu_if->get_state(); };
-        get_interrupt_execution = [sc_cpu_if]() { return sc_cpu_if->get_interrupt_execution(); };
-        set_interrupt_execution = [sc_cpu_if](bool b) { return sc_cpu_if->set_interrupt_execution(b); };
-        local_irq = [sc_cpu_if](short s, bool b) { return sc_cpu_if->local_irq(s, b); };
 
+    void create_cpu(std::string const& type, std::string const& backend, unsigned gdb_port, uint32_t hart_id){
+        CREATE_CORE(tgc_c)
+#ifdef CORE_TGC_B
+        CREATE_CORE(tgc_b)
+#endif
+#ifdef CORE_TGC_D
+        CREATE_CORE(tgc_d)
+#endif
+#ifdef CORE_TGC_D_XRB_MAC
+        CREATE_CORE(tgc_d_xrb_mac)
+#endif
+#ifdef CORE_TGC_D_XRB_NN
+        CREATE_CORE(tgc_d_xrb_nn)
+#endif
+        {
+            LOG(ERR) << "Illegal argument value for core type: " << type << std::endl;
+        }
         auto *srv = debugger::server<debugger::gdb_session>::get();
-        if(srv)
+        if (srv) tgt_adapter = srv->get_target();
-            tgt_adapter = srv->get_target();
         if (tgt_adapter)
-            tgt_adapter->add_custom_command({"sysc",
+            tgt_adapter->add_custom_command(
-                                             [this](int argc, char* argv[], debugger::out_func of, debugger::data_func df) -> int {
+                {"sysc", [this](int argc, char *argv[], debugger::out_func of,
-                                                 return cmd_sysc(argc, argv, of, df, tgt_adapter);
+                                debugger::data_func df) -> int { return cmd_sysc(argc, argv, of, df, tgt_adapter); },
-                                             },
                  "SystemC sub-commands: break <time>, print_time"});
+
     }
 
     core_complex * const owner;
     vm_ptr vm{nullptr};
-    sc_cpu_ptr cpu{nullptr};
+    cpu_ptr cpu{nullptr};
     iss::debugger::target_adapter_if *tgt_adapter{nullptr};
 };
 
@@ -203,7 +333,8 @@ core_complex::core_complex(sc_module_name const& name)
 : sc_module(name)
 , fetch_lut(tlm_dmi_ext())
 , read_lut(tlm_dmi_ext())
-, write_lut(tlm_dmi_ext()) {
+, write_lut(tlm_dmi_ext())
+{
 	init();
 }
 #endif
@@ -286,6 +417,10 @@ void core_complex::before_end_of_elaboration() {
                 auto *plugin = new iss::plugin::cycle_estimate(filename);
                 cpu->vm->register_plugin(*plugin);
                 plugin_list.push_back(plugin);
+            } else if (plugin_name == "pctrace") {
+                auto *plugin = new iss::plugin::pctrace(filename);
+                cpu->vm->register_plugin(*plugin);
+                plugin_list.push_back(plugin);
             } else {
 #ifndef WIN32
                 std::array<char const*, 1> a{{filename.c_str()}};
@@ -300,6 +435,7 @@ void core_complex::before_end_of_elaboration() {
             }
         }
     }
+
 }
 
 void core_complex::start_of_simulation() {
@@ -326,10 +462,8 @@ void core_complex::start_of_simulation() {
 }
 
 bool core_complex::disass_output(uint64_t pc, const std::string instr_str) {
-    if(trc->m_db == nullptr)
+    if (trc->m_db == nullptr) return false;
-        return false;
+    if (trc->tr_handle.is_active()) trc->tr_handle.end_transaction();
-    if(trc->tr_handle.is_active())
-        trc->tr_handle.end_transaction();
     trc->tr_handle = trc->instr_tr_handle->begin_transaction();
     trc->tr_handle.record_attribute("PC", pc);
     trc->tr_handle.record_attribute("INSTR", instr_str);
@@ -350,13 +484,11 @@ void core_complex::forward() {
 
 void core_complex::set_clock_period(sc_core::sc_time period) {
 	curr_clk = period;
-    if(period == SC_ZERO_TIME)
+    if (period == SC_ZERO_TIME) cpu->set_interrupt_execution(true);
-        cpu->set_interrupt_execution(true);
 }
 
 void core_complex::rst_cb() {
-    if(rst_i.read())
+    if (rst_i.read()) cpu->set_interrupt_execution(true);
-        cpu->set_interrupt_execution(true);
 }
 
 void core_complex::sw_irq_cb() { cpu->local_irq(3, sw_irq_i.read()); }
@@ -386,7 +518,7 @@ void core_complex::run() {
         }
         quantum_keeper.reset();
         cpu->set_interrupt_execution(false);
-        cpu->start(dump_ir);
+        cpu->start();
     } while (cpu->get_interrupt_execution());
     sc_stop();
 }
@@ -397,10 +529,7 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t* const data,
     if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && addr + length <= lut_entry.get_end_address() + 1) {
         auto offset = addr - lut_entry.get_start_address();
         std::copy(lut_entry.get_dmi_ptr() + offset, lut_entry.get_dmi_ptr() + offset + length, data);
-        if(is_fetch)
+        quantum_keeper.inc(lut_entry.get_read_latency());
-            ibus_inc += lut_entry.get_read_latency() / curr_clk;
-        else
-            dbus_inc += lut_entry.get_read_latency() / curr_clk;
         return true;
     } else {
         auto& sckt = is_fetch? ibus : dbus;
@@ -418,29 +547,24 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t* const data,
             auto preExt = new tlm::scc::scv::tlm_recording_extension(trc->tr_handle, this);
             gp.set_extension(preExt);
         }
-        auto pre_delay = delay;
+        sckt->b_transport(gp, delay);
-        dbus->b_transport(gp, delay);
+        auto incr = delay-quantum_keeper.get_local_time();
-        if(pre_delay > delay) {
-            quantum_keeper.reset();
-        } else {
-            auto incr = (delay - quantum_keeper.get_local_time()) / curr_clk;
         if(is_fetch)
             ibus_inc+=incr;
         else
             dbus_inc+=incr;
-        }
+        SCCTRACE(this->name()) << "[local time: "<<delay<<"]: finish read_mem(0x" << std::hex << addr << ") : 0x" << (length==4?*(uint32_t*)data:length==2?*(uint16_t*)data:(unsigned)*data);
-        SCCTRACE(this->name()) << "[local time: " << delay << "]: finish read_mem(0x" << std::hex << addr << ") : 0x"
-                               << (length == 4 ? *(uint32_t*)data : length == 2 ? *(uint16_t*)data : (unsigned)*data);
         if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
             return false;
         }
-        if(gp.is_dmi_allowed() && !GET_PROP_VALUE(disable_dmi)) {
+        if (gp.is_dmi_allowed()) {
             gp.set_command(tlm::TLM_READ_COMMAND);
             gp.set_address(addr);
             tlm_dmi_ext dmi_data;
             if (sckt->get_direct_mem_ptr(gp, dmi_data)) {
                 if (dmi_data.is_read_allowed())
-                    dmi_lut.addEntry(dmi_data, dmi_data.get_start_address(), dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
+                    dmi_lut.addEntry(dmi_data, dmi_data.get_start_address(),
+                                      dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
             }
         }
         return true;
@@ -449,10 +573,11 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t* const data,
 
 bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *const data) {
     auto lut_entry = write_lut.getEntry(addr);
-    if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && addr + length <= lut_entry.get_end_address() + 1) {
+    if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
+        addr + length <= lut_entry.get_end_address() + 1) {
         auto offset = addr - lut_entry.get_start_address();
         std::copy(data, data + length, lut_entry.get_dmi_ptr() + offset);
-        dbus_inc += lut_entry.get_write_latency() / curr_clk;
+        quantum_keeper.inc(lut_entry.get_read_latency());
         return true;
     } else {
         write_buf.resize(length);
@@ -468,18 +593,13 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t* cons
             auto preExt = new tlm::scc::scv::tlm_recording_extension(trc->tr_handle, this);
             gp.set_extension(preExt);
         }
-        auto pre_delay = delay;
         dbus->b_transport(gp, delay);
-        if(pre_delay > delay)
+        dbus_inc+=delay-quantum_keeper.get_local_time();
-            quantum_keeper.reset();
+        SCCTRACE() << "[local time: "<<delay<<"]: finish write_mem(0x" << std::hex << addr << ") : 0x" << (length==4?*(uint32_t*)data:length==2?*(uint16_t*)data:(unsigned)*data);
-        else
-            dbus_inc += (delay - quantum_keeper.get_local_time()) / curr_clk;
-        SCCTRACE() << "[local time: " << delay << "]: finish write_mem(0x" << std::hex << addr << ") : 0x"
-                   << (length == 4 ? *(uint32_t*)data : length == 2 ? *(uint16_t*)data : (unsigned)*data);
         if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
             return false;
         }
-        if(gp.is_dmi_allowed() && !GET_PROP_VALUE(disable_dmi)) {
+        if (gp.is_dmi_allowed()) {
             gp.set_command(tlm::TLM_READ_COMMAND);
             gp.set_address(addr);
             tlm_dmi_ext dmi_data;
@@ -514,5 +634,5 @@ bool core_complex::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t*
     gp.set_streaming_width(length);
     return dbus->transport_dbg(gp) == length;
 }
-} /* namespace tgfs */
+} /* namespace SiFive */
 } /* namespace sysc */

src/sysc/core_complex.h

@@ -33,10 +33,10 @@
 #ifndef _SYSC_CORE_COMPLEX_H_
 #define _SYSC_CORE_COMPLEX_H_
 
-#include <scc/tick2time.h>
-#include <scc/traceable.h>
-#include <scc/utilities.h>
 #include <tlm/scc/initiator_mixin.h>
+#include <scc/traceable.h>
+#include <scc/tick2time.h>
+#include <scc/utilities.h>
 #include <tlm/scc/scv/tlm_rec_initiator_socket.h>
 #ifdef CWR_SYSTEMC
 #include <scmlinc/scml_property.h>
@@ -45,10 +45,10 @@
 #include <cci_configuration>
 #define SOCKET_WIDTH scc::LT
 #endif
-#include <memory>
 #include <tlm>
 #include <tlm_utils/tlm_quantumkeeper.h>
 #include <util/range_lut.h>
+#include <memory>
 
 namespace iss {
     class vm_plugin;
@@ -58,8 +58,8 @@ namespace sysc {
 class tlm_dmi_ext : public tlm::tlm_dmi {
 public:
     bool operator==(const tlm_dmi_ext &o) const {
-        return this->get_granted_access() == o.get_granted_access() && this->get_start_address() == o.get_start_address() &&
+        return this->get_granted_access() == o.get_granted_access() &&
-               this->get_end_address() == o.get_end_address();
+               this->get_start_address() == o.get_start_address() && this->get_end_address() == o.get_end_address();
     }
 
     bool operator!=(const tlm_dmi_ext &o) const { return !operator==(o); }
@@ -94,11 +94,9 @@ public:
 
     cci::cci_param<bool> enable_disass{"enable_disass", false};
 
-    cci::cci_param<bool> disable_dmi{"disable_dmi", false};
-
     cci::cci_param<uint64_t> reset_address{"reset_address", 0ULL};
 
-    cci::cci_param<std::string> core_type{"core_type", "tgc5c"};
+    cci::cci_param<std::string> core_type{"core_type", "tgc_c"};
 
     cci::cci_param<std::string> backend{"backend", "interp"};
 
@@ -121,11 +119,9 @@ public:
 
     scml_property<bool> enable_disass{"enable_disass", false};
 
-    scml_property<bool> disable_dmi{"disable_dmi", false};
-
     scml_property<unsigned long long> reset_address{"reset_address", 0ULL};
 
-    scml_property<std::string> core_type{"core_type", "tgc5c"};
+    scml_property<std::string> core_type{"core_type", "tgc_c"};
 
     scml_property<std::string> backend{"backend", "interp"};
 
@@ -143,7 +139,7 @@ public:
     , elf_file{"elf_file", ""}
     , enable_disass{"enable_disass", false}
     , reset_address{"reset_address", 0ULL}
-    , core_type{"core_type", "tgc5c"}
+    , core_type{"core_type", "tgc_c"}
     , backend{"backend", "interp"}
     , gdb_server_port{"gdb_server_port", 0}
     , dump_ir{"dump_ir", false}
@@ -151,7 +147,8 @@ public:
     , plugins{"plugins", ""}
     , fetch_lut(tlm_dmi_ext())
     , read_lut(tlm_dmi_ext())
-    , write_lut(tlm_dmi_ext()) {
+    , write_lut(tlm_dmi_ext())
+    {
     	init();
     }
 
@@ -159,20 +156,17 @@ public:
 
     ~core_complex();
 
-    inline unsigned get_last_bus_cycles() {
-        auto mem_incr = std::max(ibus_inc, dbus_inc);
-        ibus_inc = dbus_inc = 0;
-        return mem_incr > 1 ? mem_incr : 1;
-    }
-
     inline void sync(uint64_t cycle) {
         auto core_inc = curr_clk * (cycle - last_sync_cycle);
-        quantum_keeper.inc(core_inc);
+        auto incr = std::max(core_inc, std::max(ibus_inc, dbus_inc));
+        quantum_keeper.inc(incr);
         if (quantum_keeper.need_sync()) {
             wait(quantum_keeper.get_local_time());
             quantum_keeper.reset();
         }
         last_sync_cycle = cycle;
+        ibus_inc = sc_core::SC_ZERO_TIME;
+        dbus_inc = sc_core::SC_ZERO_TIME;
     }
 
     bool read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch);
@@ -188,7 +182,6 @@ public:
     bool disass_output(uint64_t pc, const std::string instr);
 
     void set_clock_period(sc_core::sc_time period);
-
 protected:
     void before_end_of_elaboration() override;
     void start_of_simulation() override;
@@ -205,13 +198,13 @@ protected:
     std::vector<uint8_t> write_buf;
     core_wrapper* cpu{nullptr};
     sc_core::sc_signal<sc_core::sc_time> curr_clk;
-    uint64_t ibus_inc{0}, dbus_inc{0};
+    sc_core::sc_time ibus_inc, dbus_inc;
     core_trace* trc{nullptr};
     std::unique_ptr<scc::tick2time> t2t;
-
 private:
     void init();
     std::vector<iss::vm_plugin *> plugin_list;
+
 };
 } /* namespace tgfs */
 } /* namespace sysc */

src/sysc/register_tgc_c.cpp

@@ -1,110 +1,33 @@
-/*******************************************************************************
+/*
- * Copyright (C) 2023 MINRES Technologies GmbH
+ * register_tgc_c.cpp
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
+ *  Created on: Jul 5, 2023
- * modification, are permitted provided that the following conditions are met:
+ *      Author: eyck
- *
+ */
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
 
-// clang-format off
+
-#include "iss_factory.h"
+
-#include <iss/arch/tgc5c.h>
+
+#include <iss/factory.h>
+#include <iss/arch/tgc_c.h>
 #include <iss/arch/riscv_hart_m_p.h>
 #include <iss/arch/riscv_hart_mu_p.h>
 #include "sc_core_adapter.h"
 #include "core_complex.h"
-#include <array>
-// clang-format on
 
 namespace iss {
-namespace interp {
+namespace {
-using namespace sysc;
+volatile std::array<bool, 2> dummy = {
-volatile std::array<bool, 2> tgc_init = {
+        core_factory::instance().register_creator("tgc_c|m_p|interp", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
-    iss_factory::instance().register_creator("tgc5c|m_p|interp",
-                                             [](unsigned gdb_port, void* data) -> iss_factory::base_t {
             auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-                                                 auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
+            arch::tgc_c* lcpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc_c>>(cc);
-                                                 return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
+            return {cpu_ptr{lcpu}, vm_ptr{interp::create(lcpu, gdb_port)}};
         }),
-    iss_factory::instance().register_creator("tgc5c|mu_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+        core_factory::instance().register_creator("tgc_c|mu_p|interp", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
             auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-        auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
+            arch::tgc_c* lcpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc_c>>(cc);
-        return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
+            return {cpu_ptr{lcpu}, vm_ptr{interp::create(lcpu, gdb_port)}};
-    })};
+        })
-} // namespace interp
+};
-#if defined(WITH_LLVM)
+}
-namespace llvm {
+}
-using namespace sysc;
-volatile std::array<bool, 2> tgc_init = {
-    iss_factory::instance().register_creator("tgc5c|m_p|llvm",
-                                             [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-                                                 auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-                                                 auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
-                                                 return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
-                                             }),
-    iss_factory::instance().register_creator("tgc5c|mu_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-        auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-        auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
-        return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
-    })};
-} // namespace llvm
-#endif
-#if defined(WITH_TCC)
-namespace tcc {
-using namespace sysc;
-volatile std::array<bool, 2> tgc_init = {
-    iss_factory::instance().register_creator("tgc5c|m_p|tcc",
-                                             [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-                                                 auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-                                                 auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
-                                                 return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
-                                             }),
-    iss_factory::instance().register_creator("tgc5c|mu_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-        auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-        auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
-        return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
-    })};
-} // namespace tcc
-#endif
-#if defined(WITH_ASMJIT)
-namespace asmjit {
-using namespace sysc;
-volatile std::array<bool, 2> tgc_init = {
-    iss_factory::instance().register_creator("tgc5c|m_p|asmjit",
-                                             [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-                                                 auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-                                                 auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
-                                                 return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
-                                             }),
-    iss_factory::instance().register_creator("tgc5c|mu_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-        auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-        auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
-        return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
-    })};
-} // namespace asmjit
-#endif
-} // namespace iss

src/sysc/sc_core_adapter.h

@@ -8,15 +8,17 @@
 #ifndef _SYSC_SC_CORE_ADAPTER_H_
 #define _SYSC_SC_CORE_ADAPTER_H_
 
-#include "sc_core_adapter_if.h"
+
-#include <iostream>
-#include <iss/iss.h>
-#include <iss/vm_types.h>
 #include <scc/report.h>
 #include <util/ities.h>
+#include "core_complex.h"
+#include <iss/iss.h>
+#include <iss/vm_types.h>
+#include <iostream>
 
-namespace sysc {
+
-template <typename PLAT> class sc_core_adapter : public PLAT, public sc_core_adapter_if {
+template<typename PLAT>
+class sc_core_adapter : public PLAT {
 public:
     using reg_t       = typename iss::arch::traits<typename PLAT::core>::reg_t;
     using phys_addr_t = typename iss::arch::traits<typename PLAT::core>::phys_addr_t;
@@ -24,27 +26,18 @@ public:
     sc_core_adapter(sysc::tgfs::core_complex *owner)
     : owner(owner) { }
 
-    iss::arch_if* get_arch_if() override { return this; }
+    uint32_t get_mode() { return this->reg.PRIV; }
 
-    void set_mhartid(unsigned id) override { PLAT::set_mhartid(id); }
+    inline void set_interrupt_execution(bool v) { this->interrupt_sim = v?1:0; }
 
-    uint32_t get_mode() override { return this->reg.PRIV; }
+    inline bool get_interrupt_execution() { return this->interrupt_sim; }
 
-    void set_interrupt_execution(bool v) override { this->interrupt_sim = v ? 1 : 0; }
+    heart_state_t &get_state() { return this->state; }
-
-    bool get_interrupt_execution() override { return this->interrupt_sim; }
-
-    uint64_t get_state() override { return this->state.mstatus.backing.val; }
 
     void notify_phase(iss::arch_if::exec_phase p) override {
-        if(p == iss::arch_if::ISTART && !first) {
+        if (p == iss::arch_if::ISTART)
-            auto cycle_incr = owner->get_last_bus_cycles();
-            if(cycle_incr > 1)
-                this->instr_if.update_last_instr_cycles(cycle_incr);
             owner->sync(this->instr_if.get_total_cycles());
     }
-        first = false;
-    }
 
     iss::sync_type needed_sync() const override { return iss::PRE_SYNC; }
 
@@ -52,8 +45,9 @@ public:
         static constexpr std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
         if (!owner->disass_output(pc, instr)) {
             std::stringstream s;
-            s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0') << std::setw(sizeof(reg_t) * 2)
+            s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0')
-              << (reg_t)this->state.mstatus << std::dec << ";c:" << this->reg.icount + this->cycle_offset << "]";
+              << std::setw(sizeof(reg_t) * 2) << (reg_t)this->state.mstatus << std::dec << ";c:"
+              << this->reg.icount + this->cycle_offset << "]";
             SCCDEBUG(owner->name())<<"disass: "
                 << "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
                 << std::setfill(' ') << std::left << instr << s.str();
@@ -72,44 +66,16 @@ public:
         if (addr.access && iss::access_type::DEBUG)
             return owner->write_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
         else {
-            auto tohost_upper = (sizeof(reg_t) == 4 && addr.val == (this->tohost + 4)) || (sizeof(reg_t) == 8 && addr.val == this->tohost);
-            auto tohost_lower = (sizeof(reg_t) == 4 && addr.val == this->tohost) || (sizeof(reg_t) == 64 && addr.val == this->tohost);
-            if(tohost_lower || tohost_upper) {
-                if(tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) {
-                    switch(hostvar >> 48) {
-                    case 0:
-                        if(hostvar != 0x1) {
-                            SCCINFO(owner->name())
-                                << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation";
-                        } else {
-                            SCCINFO(owner->name())
-                                << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation";
-                        }
-                        this->reg.trap_state = std::numeric_limits<uint32_t>::max();
-                        this->interrupt_sim = hostvar;
-#ifndef WITH_TCC
-                        throw(iss::simulation_stopped(hostvar));
-#endif
-                        break;
-                    default:
-                        break;
-                    }
-                } else if(tohost_lower)
-                    to_host_wr_cnt++;
-                return iss::Ok;
-            } else {
             auto res = owner->write_mem(addr.val, length, data) ? iss::Ok : iss::Err;
             // clear MTIP on mtimecmp write
             if (addr.val == 0x2004000) {
                 reg_t val;
                 this->read_csr(iss::arch::mip, val);
-                    if(val & (1ULL << 7))
+                if (val & (1ULL << 7)) this->write_csr(iss::arch::mip, val & ~(1ULL << 7));
-                        this->write_csr(iss::arch::mip, val & ~(1ULL << 7));
             }
             return res;
         }
     }
-    }
 
     iss::status read_csr(unsigned addr, reg_t &val) override {
 #ifndef CWR_SYSTEMC
@@ -119,8 +85,7 @@ public:
             if (addr == iss::arch::time) {
                 val = static_cast<reg_t>(time_val);
             } else if (addr == iss::arch::timeh) {
-                if(sizeof(reg_t) != 4)
+                if (sizeof(reg_t) != 4) return iss::Err;
-                    return iss::Err;
                 val = static_cast<reg_t>(time_val >> 32);
             }
             return ret?iss::Ok:iss::Err;
@@ -130,8 +95,7 @@ public:
             if (addr == iss::arch::time) {
                 val = static_cast<reg_t>(time_val);
             } else if (addr == iss::arch::timeh) {
-                if(sizeof(reg_t) != 4)
+                if (sizeof(reg_t) != 4) return iss::Err;
-                    return iss::Err;
                 val = static_cast<reg_t>(time_val >> 32);
             }
             return iss::Ok;
@@ -149,7 +113,7 @@ public:
         PLAT::wait_until(flags);
     }
 
-    void local_irq(short id, bool value) override {
+    void local_irq(short id, bool value) {
         reg_t mask = 0;
         switch (id) {
         case 3: // SW
@@ -162,8 +126,7 @@ public:
             mask = 1 << 11;
             break;
         default:
-            if(id > 15)
+            if(id>15) mask = 1 << id;
-                mask = 1 << id;
             break;
         }
         if (value) {
@@ -179,9 +142,7 @@ public:
 private:
     sysc::tgfs::core_complex *const owner;
     sc_core::sc_event wfi_evt;
-    uint64_t hostvar{std::numeric_limits<uint64_t>::max()};
-    unsigned to_host_wr_cnt = 0;
-    bool first{true};
 };
-} // namespace sysc
+
+
 #endif /* _SYSC_SC_CORE_ADAPTER_H_ */

src/sysc/sc_core_adapter_if.h

@@ -1,30 +0,0 @@
-/*
- * sc_core_adapter.h
- *
- *  Created on: Jul 5, 2023
- *      Author: eyck
- */
-
-#ifndef _SYSC_SC_CORE_ADAPTER_IF_H_
-#define _SYSC_SC_CORE_ADAPTER_IF_H_
-
-#include "core_complex.h"
-#include <iostream>
-#include <iss/iss.h>
-#include <iss/vm_types.h>
-#include <scc/report.h>
-#include <util/ities.h>
-
-namespace sysc {
-struct sc_core_adapter_if {
-    virtual iss::arch_if* get_arch_if() = 0;
-    virtual void set_mhartid(unsigned) = 0;
-    virtual uint32_t get_mode() = 0;
-    virtual uint64_t get_state() = 0;
-    virtual bool get_interrupt_execution() = 0;
-    virtual void set_interrupt_execution(bool v) = 0;
-    virtual void local_irq(short id, bool value) = 0;
-    virtual ~sc_core_adapter_if() = default;
-};
-} // namespace sysc
-#endif /* _SYSC_SC_CORE_ADAPTER_IF_H_ */

src/vm/asmjit/helper_func.h

@@ -1,537 +0,0 @@
-
-
-x86::Mem get_reg_ptr(jit_holder& jh, unsigned idx) {
-
-    x86::Gp tmp_ptr = jh.cc.newUIntPtr("tmp_ptr");
-    jh.cc.mov(tmp_ptr, jh.regs_base_ptr);
-    jh.cc.add(tmp_ptr, traits::reg_byte_offsets[idx]);
-    switch(traits::reg_bit_widths[idx]) {
-    case 8:
-        return x86::ptr_8(tmp_ptr);
-    case 16:
-        return x86::ptr_16(tmp_ptr);
-    case 32:
-        return x86::ptr_32(tmp_ptr);
-    case 64:
-        return x86::ptr_64(tmp_ptr);
-    default:
-        throw std::runtime_error("Invalid reg size in get_reg_ptr");
-    }
-}
-x86::Gp get_reg_for(jit_holder& jh, unsigned idx) {
-    // TODO can check for regs in jh and return them instead of creating new ones
-    switch(traits::reg_bit_widths[idx]) {
-    case 8:
-        return jh.cc.newInt8();
-    case 16:
-        return jh.cc.newInt16();
-    case 32:
-        return jh.cc.newInt32();
-    case 64:
-        return jh.cc.newInt64();
-    default:
-        throw std::runtime_error("Invalid reg size in get_reg_ptr");
-    }
-}
-x86::Gp get_reg_for(jit_holder& jh, unsigned size, bool is_signed) {
-    if(is_signed)
-        switch(size) {
-        case 8:
-            return jh.cc.newInt8();
-        case 16:
-            return jh.cc.newInt16();
-        case 32:
-            return jh.cc.newInt32();
-        case 64:
-            return jh.cc.newInt64();
-        default:
-            throw std::runtime_error("Invalid reg size in get_reg_ptr");
-        }
-    else
-        switch(size) {
-        case 8:
-            return jh.cc.newUInt8();
-        case 16:
-            return jh.cc.newUInt16();
-        case 32:
-            return jh.cc.newUInt32();
-        case 64:
-            return jh.cc.newUInt64();
-        default:
-            throw std::runtime_error("Invalid reg size in get_reg_ptr");
-        }
-}
-inline x86::Gp load_reg_from_mem(jit_holder& jh, unsigned idx) {
-    auto ptr = get_reg_ptr(jh, idx);
-    auto reg = get_reg_for(jh, idx);
-    jh.cc.mov(reg, ptr);
-    return reg;
-}
-inline void write_reg_to_mem(jit_holder& jh, x86::Gp reg, unsigned idx) {
-    auto ptr = get_reg_ptr(jh, idx);
-    jh.cc.mov(ptr, reg);
-}
-
-void gen_instr_prologue(jit_holder& jh, addr_t pc) {
-    auto& cc = jh.cc;
-
-    cc.comment("\n//(*icount)++;");
-    cc.inc(get_reg_ptr(jh, traits::ICOUNT));
-
-    cc.comment("\n//*pc=*next_pc;");
-    cc.mov(get_reg_ptr(jh, traits::PC), jh.next_pc);
-
-    cc.comment("\n//*trap_state=*pending_trap;");
-    x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE);
-    cc.mov(current_trap_state, get_reg_ptr(jh, traits::TRAP_STATE));
-    cc.mov(get_reg_ptr(jh, traits::PENDING_TRAP), current_trap_state);
-
-    cc.comment("\n//increment *next_pc");
-    cc.mov(jh.next_pc, pc);
-}
-void gen_instr_epilogue(jit_holder& jh) {
-    auto& cc = jh.cc;
-
-    cc.comment("\n//if(*trap_state!=0) goto trap_entry;");
-    x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE);
-    cc.mov(current_trap_state, get_reg_ptr(jh, traits::TRAP_STATE));
-    cc.cmp(current_trap_state, 0);
-    cc.jne(jh.trap_entry);
-
-    // TODO: Does not need to be done for every instruction, only when needed
-    cc.comment("\n//write back regs to mem");
-    write_reg_to_mem(jh, jh.pc, traits::PC);
-    write_reg_to_mem(jh, jh.next_pc, traits::NEXT_PC);
-}
-void gen_block_prologue(jit_holder& jh) override {
-
-    jh.pc = load_reg_from_mem(jh, traits::PC);
-    jh.next_pc = load_reg_from_mem(jh, traits::NEXT_PC);
-}
-void gen_block_epilogue(jit_holder& jh) override {
-    x86::Compiler& cc = jh.cc;
-    cc.comment("\n//return *next_pc;");
-    cc.ret(jh.next_pc);
-
-    cc.bind(jh.trap_entry);
-    cc.comment("\n//Prepare for enter_trap;");
-    // Make sure cached values are written back
-    cc.comment("\n//write back regs to mem");
-    write_reg_to_mem(jh, jh.pc, traits::PC);
-    write_reg_to_mem(jh, jh.next_pc, traits::NEXT_PC);
-    this->gen_sync(jh, POST_SYNC, -1);
-
-    x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE);
-    cc.mov(current_trap_state, get_reg_ptr(jh, traits::TRAP_STATE));
-
-    x86::Gp current_pc = get_reg_for(jh, traits::PC);
-    cc.mov(current_pc, get_reg_ptr(jh, traits::PC));
-
-    x86::Gp instr = cc.newInt32("instr");
-    cc.mov(instr, 0); // this is not correct
-    cc.comment("\n//enter trap call;");
-    InvokeNode* call_enter_trap;
-    cc.invoke(&call_enter_trap, &enter_trap, FuncSignatureT<uint64_t, void*, uint64_t, uint64_t, uint64_t>());
-    call_enter_trap->setArg(0, jh.arch_if_ptr);
-    call_enter_trap->setArg(1, current_trap_state);
-    call_enter_trap->setArg(2, current_pc);
-    call_enter_trap->setArg(3, instr);
-
-    x86::Gp current_next_pc = get_reg_for(jh, traits::NEXT_PC);
-    cc.mov(current_next_pc, get_reg_ptr(jh, traits::NEXT_PC));
-    cc.mov(jh.next_pc, current_next_pc);
-
-    cc.comment("\n//*last_branch = std::numeric_limits<uint32_t>::max();");
-    cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), std::numeric_limits<uint32_t>::max());
-    cc.comment("\n//return *next_pc;");
-    cc.ret(jh.next_pc);
-}
-/*
-    inline void raise(uint16_t trap_id, uint16_t cause){
-        auto trap_val =  0x80ULL << 24 | (cause << 16) | trap_id;
-        this->core.reg.trap_state = trap_val;
-        this->template get_reg<uint32_t>(traits::NEXT_PC) = std::numeric_limits<uint32_t>::max();
-    }
-*/
-inline void gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause) {
-    auto& cc = jh.cc;
-    cc.comment("//gen_raise");
-    auto tmp1 = get_reg_for(jh, traits::TRAP_STATE);
-    cc.mov(tmp1, 0x80ULL << 24 | (cause << 16) | trap_id);
-    cc.mov(get_reg_ptr(jh, traits::TRAP_STATE), tmp1);
-    auto tmp2 = get_reg_for(jh, traits::NEXT_PC);
-    cc.mov(tmp2, std::numeric_limits<uint32_t>::max());
-    cc.mov(get_reg_ptr(jh, traits::NEXT_PC), tmp2);
-}
-inline void gen_wait(jit_holder& jh, unsigned type) { jh.cc.comment("//gen_wait"); }
-inline void gen_leave(jit_holder& jh, unsigned lvl) { jh.cc.comment("//gen_leave"); }
-
-enum operation { add, sub, band, bor, bxor, shl, sar, shr };
-
-template <typename T, typename = std::enable_if_t<std::is_integral<T>::value || std::is_same<T, x86::Gp>::value>>
-x86::Gp gen_operation(jit_holder& jh, operation op, x86::Gp a, T b) {
-    x86::Compiler& cc = jh.cc;
-    switch(op) {
-    case add: {
-        cc.add(a, b);
-        break;
-    }
-    case sub: {
-        cc.sub(a, b);
-        break;
-    }
-    case band: {
-        cc.and_(a, b);
-        break;
-    }
-    case bor: {
-        cc.or_(a, b);
-        break;
-    }
-    case bxor: {
-        cc.xor_(a, b);
-        break;
-    }
-    case shl: {
-        cc.shl(a, b);
-        break;
-    }
-    case sar: {
-        cc.sar(a, b);
-        break;
-    }
-    case shr: {
-        cc.shr(a, b);
-        break;
-    }
-    default:
-        throw std::runtime_error(fmt::format("Current operation {} not supported in gen_operation (operation)", op));
-    }
-    return a;
-}
-
-enum three_operand_operation { imul, mul, idiv, div, srem, urem };
-
-x86::Gp gen_operation(jit_holder& jh, three_operand_operation op, x86::Gp a, x86::Gp b) {
-    x86::Compiler& cc = jh.cc;
-    switch(op) {
-    case imul: {
-        x86::Gp dummy = cc.newInt64();
-        cc.imul(dummy, a.r64(), b.r64());
-        return a;
-    }
-    case mul: {
-        x86::Gp dummy = cc.newInt64();
-        cc.mul(dummy, a.r64(), b.r64());
-        return a;
-    }
-    case idiv: {
-        x86::Gp dummy = cc.newInt64();
-        cc.mov(dummy, 0);
-        cc.idiv(dummy, a.r64(), b.r64());
-        return a;
-    }
-    case div: {
-        x86::Gp dummy = cc.newInt64();
-        cc.mov(dummy, 0);
-        cc.div(dummy, a.r64(), b.r64());
-        return a;
-    }
-    case srem: {
-        x86::Gp rem = cc.newInt32();
-        cc.mov(rem, 0);
-        auto a_reg = cc.newInt32();
-        cc.mov(a_reg, a.r32());
-        cc.idiv(rem, a_reg, b.r32());
-        return rem;
-    }
-    case urem: {
-        x86::Gp rem = cc.newInt32();
-        cc.mov(rem, 0);
-        auto a_reg = cc.newInt32();
-        cc.mov(a_reg, a.r32());
-        cc.div(rem, a_reg, b.r32());
-        return rem;
-    }
-
-    default:
-        throw std::runtime_error(fmt::format("Current operation {} not supported in gen_operation (three_operand)", op));
-    }
-    return a;
-}
-template <typename T, typename = std::enable_if_t<std::is_integral<T>::value>>
-x86::Gp gen_operation(jit_holder& jh, three_operand_operation op, x86::Gp a, T b) {
-    x86::Gp b_reg = jh.cc.newInt32();
-    /*     switch(a.size()){
-            case 1: b_reg = jh.cc.newInt8(); break;
-            case 2: b_reg = jh.cc.newInt16(); break;
-            case 4: b_reg = jh.cc.newInt32(); break;
-            case 8: b_reg = jh.cc.newInt64(); break;
-            default: throw std::runtime_error(fmt::format("Invalid size ({}) in gen operation", a.size()));
-        } */
-    jh.cc.mov(b_reg, b);
-    return gen_operation(jh, op, a, b_reg);
-}
-enum comparison_operation { land, lor, eq, ne, lt, ltu, gt, gtu, lte, lteu, gte, gteu };
-
-template <typename T, typename = std::enable_if_t<std::is_integral<T>::value || std::is_same<T, x86::Gp>::value>>
-x86::Gp gen_operation(jit_holder& jh, comparison_operation op, x86::Gp a, T b) {
-    x86::Compiler& cc = jh.cc;
-    x86::Gp tmp = cc.newInt8();
-    cc.mov(tmp, 1);
-    Label label_then = cc.newLabel();
-    cc.cmp(a, b);
-    switch(op) {
-    case eq:
-        cc.je(label_then);
-        break;
-    case ne:
-        cc.jne(label_then);
-        break;
-    case lt:
-        cc.jl(label_then);
-        break;
-    case ltu:
-        cc.jb(label_then);
-        break;
-    case gt:
-        cc.jg(label_then);
-        break;
-    case gtu:
-        cc.ja(label_then);
-        break;
-    case lte:
-        cc.jle(label_then);
-        break;
-    case lteu:
-        cc.jbe(label_then);
-        break;
-    case gte:
-        cc.jge(label_then);
-        break;
-    case gteu:
-        cc.jae(label_then);
-        break;
-    case land: {
-        Label label_false = cc.newLabel();
-        cc.cmp(a, 0);
-        cc.je(label_false);
-        auto b_reg = cc.newInt8();
-        cc.mov(b_reg, b);
-        cc.cmp(b_reg, 0);
-        cc.je(label_false);
-        cc.jmp(label_then);
-        cc.bind(label_false);
-        break;
-    }
-    case lor: {
-        cc.cmp(a, 0);
-        cc.jne(label_then);
-        auto b_reg = cc.newInt8();
-        cc.mov(b_reg, b);
-        cc.cmp(b_reg, 0);
-        cc.jne(label_then);
-        break;
-    }
-    default:
-        throw std::runtime_error(fmt::format("Current operation {} not supported in gen_operation (comparison)", op));
-    }
-    cc.mov(tmp, 0);
-    cc.bind(label_then);
-    return tmp;
-}
-enum binary_operation { lnot, inc, dec, bnot, neg };
-
-x86::Gp gen_operation(jit_holder& jh, binary_operation op, x86::Gp a) {
-    x86::Compiler& cc = jh.cc;
-    switch(op) {
-    case lnot:
-        throw std::runtime_error("Current operation not supported in gen_operation(lnot)");
-    case inc: {
-        cc.inc(a);
-        break;
-    }
-    case dec: {
-        cc.dec(a);
-        break;
-    }
-    case bnot: {
-        cc.not_(a);
-        break;
-    }
-    case neg: {
-        cc.neg(a);
-        break;
-    }
-    default:
-        throw std::runtime_error(fmt::format("Current operation {} not supported in gen_operation (unary)", op));
-    }
-    return a;
-}
-
-template <typename T, typename = std::enable_if_t<std::is_integral<T>::value>>
-inline x86::Gp gen_ext(jit_holder& jh, T val, unsigned size, bool is_signed) {
-    auto val_reg = get_reg_for(jh, sizeof(val) * 8, is_signed);
-    jh.cc.mov(val_reg, val);
-    return gen_ext(jh, val_reg, size, is_signed);
-}
-inline x86::Gp gen_ext(jit_holder& jh, x86::Gp val, unsigned size, bool is_signed) {
-    auto& cc = jh.cc;
-    if(is_signed) {
-        switch(val.size()) {
-        case 1:
-            cc.cbw(val);
-            break;
-        case 2:
-            cc.cwde(val);
-            break;
-        case 4:
-            cc.cdqe(val);
-            break;
-        case 8:
-            break;
-        default:
-            throw std::runtime_error("Invalid register size in gen_ext");
-        }
-    }
-    switch(size) {
-    case 8:
-        cc.and_(val, std::numeric_limits<uint8_t>::max());
-        return val.r8();
-    case 16:
-        cc.and_(val, std::numeric_limits<uint16_t>::max());
-        return val.r16();
-    case 32:
-        cc.and_(val, std::numeric_limits<uint32_t>::max());
-        return val.r32();
-    case 64:
-        cc.and_(val, std::numeric_limits<uint64_t>::max());
-        return val.r64();
-    case 128:
-        return val.r64();
-    default:
-        throw std::runtime_error("Invalid size in gen_ext");
-    }
-}
-inline x86::Gp gen_read_mem(jit_holder& jh, mem_type_e type, x86::Gp addr, uint32_t length) {
-    x86::Compiler& cc = jh.cc;
-    auto ret_reg = cc.newInt32();
-
-    auto mem_type_reg = cc.newInt32();
-    cc.mov(mem_type_reg, type);
-
-    auto space_reg = cc.newInt32();
-    cc.mov(space_reg, static_cast<uint16_t>(iss::address_type::VIRTUAL));
-
-    auto val_ptr = cc.newUIntPtr();
-    cc.mov(val_ptr, read_mem_buf);
-
-    InvokeNode* invokeNode;
-    uint64_t mask = 0;
-    x86::Gp val_reg = cc.newInt64();
-
-    switch(length) {
-    case 1: {
-        cc.invoke(&invokeNode, &read_mem1, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uintptr_t>());
-        mask = std::numeric_limits<uint8_t>::max();
-        break;
-    }
-    case 2: {
-        cc.invoke(&invokeNode, &read_mem2, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uintptr_t>());
-        mask = std::numeric_limits<uint16_t>::max();
-        break;
-    }
-    case 4: {
-        cc.invoke(&invokeNode, &read_mem4, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uintptr_t>());
-        mask = std::numeric_limits<uint32_t>::max();
-        break;
-    }
-    case 8: {
-        cc.invoke(&invokeNode, &read_mem8, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uintptr_t>());
-        mask = std::numeric_limits<uint64_t>::max();
-        break;
-    }
-    default:
-        throw std::runtime_error(fmt::format("Invalid length ({}) in gen_read_mem", length));
-    }
-
-    invokeNode->setRet(0, ret_reg);
-    invokeNode->setArg(0, jh.arch_if_ptr);
-    invokeNode->setArg(1, space_reg);
-    invokeNode->setArg(2, mem_type_reg);
-    invokeNode->setArg(3, addr);
-    invokeNode->setArg(4, val_ptr);
-    cc.cmp(ret_reg, 0);
-    cc.jne(jh.trap_entry);
-
-    cc.mov(val_reg, x86::ptr_64(val_ptr));
-    cc.and_(val_reg, mask);
-    return val_reg;
-}
-inline x86::Gp gen_read_mem(jit_holder& jh, mem_type_e type, x86::Gp addr, x86::Gp length) {
-    throw std::runtime_error("Invalid gen_read_mem");
-}
-inline x86::Gp gen_read_mem(jit_holder& jh, mem_type_e type, uint64_t addr, x86::Gp length) {
-    throw std::runtime_error("Invalid gen_read_mem");
-}
-inline x86::Gp gen_read_mem(jit_holder& jh, mem_type_e type, uint64_t addr, uint32_t length) {
-    auto addr_reg = jh.cc.newInt64();
-    jh.cc.mov(addr_reg, addr);
-
-    return gen_read_mem(jh, type, addr_reg, length);
-}
-inline void gen_write_mem(jit_holder& jh, mem_type_e type, x86::Gp addr, int64_t val, uint32_t length) {
-    auto val_reg = get_reg_for(jh, length * 8, true);
-    jh.cc.mov(val_reg, val);
-    gen_write_mem(jh, type, addr, val_reg, length);
-}
-inline void gen_write_mem(jit_holder& jh, mem_type_e type, x86::Gp addr, x86::Gp val, uint32_t length) {
-    x86::Compiler& cc = jh.cc;
-    assert(val.size() == length);
-    auto mem_type_reg = cc.newInt32();
-    jh.cc.mov(mem_type_reg, type);
-    auto space_reg = cc.newInt32();
-    jh.cc.mov(space_reg, static_cast<uint16_t>(iss::address_type::VIRTUAL));
-    auto ret_reg = cc.newInt32();
-    InvokeNode* invokeNode;
-    switch(length) {
-    case 1:
-        cc.invoke(&invokeNode, &write_mem1, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uint8_t>());
-
-        break;
-    case 2:
-        cc.invoke(&invokeNode, &write_mem2, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uint16_t>());
-        break;
-    case 4:
-        cc.invoke(&invokeNode, &write_mem4, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uint32_t>());
-        break;
-    case 8:
-        cc.invoke(&invokeNode, &write_mem8, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uint64_t>());
-
-        break;
-    default:
-        throw std::runtime_error("Invalid register size in gen_ext");
-    }
-    invokeNode->setRet(0, ret_reg);
-    invokeNode->setArg(0, jh.arch_if_ptr);
-    invokeNode->setArg(1, space_reg);
-    invokeNode->setArg(2, mem_type_reg);
-    invokeNode->setArg(3, addr);
-    invokeNode->setArg(4, val);
-
-    cc.cmp(ret_reg, 0);
-    cc.jne(jh.trap_entry);
-}
-inline void gen_write_mem(jit_holder& jh, mem_type_e type, uint64_t addr, x86::Gp val, uint32_t length) {
-    auto addr_reg = jh.cc.newUInt64();
-    jh.cc.mov(addr_reg, addr);
-    gen_write_mem(jh, type, addr_reg, val, length);
-}
-inline void gen_write_mem(jit_holder& jh, mem_type_e type, uint64_t addr, int64_t val, uint32_t length) {
-    auto val_reg = get_reg_for(jh, length * 8, true);
-    jh.cc.mov(val_reg, val);
-
-    auto addr_reg = jh.cc.newUInt64();
-    jh.cc.mov(addr_reg, addr);
-    gen_write_mem(jh, type, addr_reg, val_reg, length);
-}

src/vm/fp_functions.cpp

@@ -35,24 +35,32 @@
 #include "fp_functions.h"
 
 extern "C" {
+#include <softfloat.h>
 #include "internals.h"
 #include "specialize.h"
-#include <softfloat.h>
 }
 
 #include <limits>
 
 using this_t = uint8_t *;
 const uint8_t rmm_map[] = {
-    softfloat_round_near_even /*RNE*/,   softfloat_round_minMag /*RTZ*/, softfloat_round_min /*RDN*/, softfloat_round_max /*RUP?*/,
+        softfloat_round_near_even /*RNE*/,
-    softfloat_round_near_maxMag /*RMM*/, softfloat_round_max /*RTZ*/,    softfloat_round_max /*RTZ*/, softfloat_round_max /*RTZ*/,
+        softfloat_round_minMag/*RTZ*/,
+        softfloat_round_min/*RDN*/,
+        softfloat_round_max/*RUP?*/,
+        softfloat_round_near_maxMag /*RMM*/,
+        softfloat_round_max/*RTZ*/,
+        softfloat_round_max/*RTZ*/,
+        softfloat_round_max/*RTZ*/,
 };
 
 const uint32_t quiet_nan32=0x7fC00000;
 
 extern "C" {
 
-uint32_t fget_flags() { return softfloat_exceptionFlags & 0x1f; }
+uint32_t fget_flags(){
+    return softfloat_exceptionFlags&0x1f;
+}
 
 uint32_t fadd_s(uint32_t v1, uint32_t v2, uint8_t mode) {
     float32_t v1f{v1},v2f{v2};
@@ -102,8 +110,7 @@ uint32_t fcmp_s(uint32_t v1, uint32_t v2, uint32_t op) {
     switch(op){
     case 0:
         if(nan | snan){
-            if(snan)
+            if(snan) softfloat_raiseFlags(softfloat_flag_invalid);
-                softfloat_raiseFlags(softfloat_flag_invalid);
             return 0;
         } else
             return f32_eq(v1f,v2f )?1:0;
@@ -153,8 +160,7 @@ uint32_t fmadd_s(uint32_t v1, uint32_t v2, uint32_t v3, uint32_t op, uint8_t mod
     softfloat_roundingMode=rmm_map[mode&0x7];
     softfloat_exceptionFlags=0;
     float32_t res = softfloat_mulAddF32(v1, v2, v3, op&0x1);
-    if(op > 1)
+    if(op>1) res.v ^= 1ULL<<31;
-        res.v ^= 1ULL << 31;
     return res.v;
 }
 
@@ -164,11 +170,11 @@ uint32_t fsel_s(uint32_t v1, uint32_t v2, uint32_t op) {
     bool v2_nan = (v2 & defaultNaNF32UI) == defaultNaNF32UI;
     bool v1_snan = softfloat_isSigNaNF32UI(v1);
     bool v2_snan = softfloat_isSigNaNF32UI(v2);
-    if(v1_snan || v2_snan)
+    if (v1_snan || v2_snan) softfloat_raiseFlags(softfloat_flag_invalid);
-        softfloat_raiseFlags(softfloat_flag_invalid);
     if (v1_nan || v1_snan)
         return (v2_nan || v2_snan) ? defaultNaNF32UI : v2;
-    else if(v2_nan || v2_snan)
+    else
+        if (v2_nan || v2_snan)
             return v1;
         else {
             if ((v1 & 0x7fffffff) == 0 && (v2 & 0x7fffffff) == 0) {
@@ -196,10 +202,17 @@ uint32_t fclass_s(uint32_t v1) {
     bool isNaN = isNaNF32UI( uiA );
     bool isSNaN = softfloat_isSigNaNF32UI( uiA );
 
-    return (sign && infOrNaN && fracZero) << 0 | (sign && !infOrNaN && !subnormalOrZero) << 1 |
+    return
-           (sign && subnormalOrZero && !fracZero) << 2 | (sign && subnormalOrZero && fracZero) << 3 | (!sign && infOrNaN && fracZero) << 7 |
+        (  sign && infOrNaN && fracZero )          << 0 |
-           (!sign && !infOrNaN && !subnormalOrZero) << 6 | (!sign && subnormalOrZero && !fracZero) << 5 |
+        (  sign && !infOrNaN && !subnormalOrZero ) << 1 |
-           (!sign && subnormalOrZero && fracZero) << 4 | (isNaN && isSNaN) << 8 | (isNaN && !isSNaN) << 9;
+        (  sign && subnormalOrZero && !fracZero )  << 2 |
+        (  sign && subnormalOrZero && fracZero )   << 3 |
+        ( !sign && infOrNaN && fracZero )          << 7 |
+        ( !sign && !infOrNaN && !subnormalOrZero ) << 6 |
+        ( !sign && subnormalOrZero && !fracZero )  << 5 |
+        ( !sign && subnormalOrZero && fracZero )   << 4 |
+        ( isNaN &&  isSNaN )                       << 8 |
+        ( isNaN && !isSNaN )                       << 9;
 }
 
 uint32_t fconv_d2f(uint64_t v1, uint8_t mode){
@@ -274,8 +287,7 @@ uint64_t fcmp_d(uint64_t v1, uint64_t v2, uint32_t op) {
     switch(op){
     case 0:
         if(nan | snan){
-            if(snan)
+            if(snan) softfloat_raiseFlags(softfloat_flag_invalid);
-                softfloat_raiseFlags(softfloat_flag_invalid);
             return 0;
         } else
             return f64_eq(v1f,v2f )?1:0;
@@ -325,8 +337,7 @@ uint64_t fmadd_d(uint64_t v1, uint64_t v2, uint64_t v3, uint32_t op, uint8_t mod
     softfloat_roundingMode=rmm_map[mode&0x7];
     softfloat_exceptionFlags=0;
     float64_t res = softfloat_mulAddF64(v1, v2, v3, op&0x1);
-    if(op > 1)
+    if(op>1) res.v ^= 1ULL<<63;
-        res.v ^= 1ULL << 63;
     return res.v;
 }
 
@@ -336,19 +347,22 @@ uint64_t fsel_d(uint64_t v1, uint64_t v2, uint32_t op) {
     bool v2_nan = (v2 & defaultNaNF64UI) == defaultNaNF64UI;
     bool v1_snan = softfloat_isSigNaNF64UI(v1);
     bool v2_snan = softfloat_isSigNaNF64UI(v2);
-    if(v1_snan || v2_snan)
+    if (v1_snan || v2_snan) softfloat_raiseFlags(softfloat_flag_invalid);
-        softfloat_raiseFlags(softfloat_flag_invalid);
     if (v1_nan || v1_snan)
         return (v2_nan || v2_snan) ? defaultNaNF64UI : v2;
-    else if(v2_nan || v2_snan)
+    else
+        if (v2_nan || v2_snan)
             return v1;
         else {
             if ((v1 & std::numeric_limits<int64_t>::max()) == 0 && (v2 & std::numeric_limits<int64_t>::max()) == 0) {
-            return op == 0 ? ((v1 & std::numeric_limits<int64_t>::min()) ? v1 : v2)
+                return op == 0 ?
-                           : ((v1 & std::numeric_limits<int64_t>::min()) ? v2 : v1);
+                        ((v1 & std::numeric_limits<int64_t>::min()) ? v1 : v2) :
+                        ((v1 & std::numeric_limits<int64_t>::min()) ? v2 : v1);
             } else {
                 float64_t v1f{ v1 }, v2f{ v2 };
-            return op == 0 ? (f64_lt(v1f, v2f) ? v1 : v2) : (f64_lt(v1f, v2f) ? v2 : v1);
+                return op == 0 ?
+                        (f64_lt(v1f, v2f) ? v1 : v2) :
+                        (f64_lt(v1f, v2f) ? v2 : v1);
             }
         }
 }
@@ -369,10 +383,17 @@ uint64_t fclass_d(uint64_t v1) {
     bool isNaN = isNaNF64UI( uiA );
     bool isSNaN = softfloat_isSigNaNF64UI( uiA );
 
-    return (sign && infOrNaN && fracZero) << 0 | (sign && !infOrNaN && !subnormalOrZero) << 1 |
+    return
-           (sign && subnormalOrZero && !fracZero) << 2 | (sign && subnormalOrZero && fracZero) << 3 | (!sign && infOrNaN && fracZero) << 7 |
+        (  sign && infOrNaN && fracZero )          << 0 |
-           (!sign && !infOrNaN && !subnormalOrZero) << 6 | (!sign && subnormalOrZero && !fracZero) << 5 |
+        (  sign && !infOrNaN && !subnormalOrZero ) << 1 |
-           (!sign && subnormalOrZero && fracZero) << 4 | (isNaN && isSNaN) << 8 | (isNaN && !isSNaN) << 9;
+        (  sign && subnormalOrZero && !fracZero )  << 2 |
+        (  sign && subnormalOrZero && fracZero )   << 3 |
+        ( !sign && infOrNaN && fracZero )          << 7 |
+        ( !sign && !infOrNaN && !subnormalOrZero ) << 6 |
+        ( !sign && subnormalOrZero && !fracZero )  << 5 |
+        ( !sign && subnormalOrZero && fracZero )   << 4 |
+        ( isNaN &&  isSNaN )                       << 8 |
+        ( isNaN && !isSNaN )                       << 9;
 }
 
 uint64_t fcvt_32_64(uint32_t v1, uint32_t op, uint8_t mode) {
@@ -424,3 +445,4 @@ uint32_t unbox_s(uint64_t v) {
         return v & std::numeric_limits<uint32_t>::max();
 }
 }
+

src/vm/llvm/fp_impl.cpp

@@ -36,9 +36,9 @@
 #include <iss/llvm/vm_base.h>
 
 extern "C" {
+#include <softfloat.h>
 #include "internals.h"
 #include "specialize.h"
-#include <softfloat.h>
 }
 
 #include <limits>
@@ -69,6 +69,7 @@ using namespace ::llvm;
     FunctionType *NAME##_type = FunctionType::get(RET, NAME##_args, false);                                      \
     mod->getOrInsertFunction(#NAME, NAME##_type);
 
+
 void add_fp_functions_2_module(Module *mod, uint32_t flen, uint32_t xlen) {
     if(flen){
         FDECL(fget_flags, INT_TYPE(32));
@@ -98,10 +99,11 @@ void add_fp_functions_2_module(Module* mod, uint32_t flen, uint32_t xlen) {
             FDECL(fsel_d,     INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(32));
             FDECL(fclass_d,   INT_TYPE(64), INT_TYPE(64));
             FDECL(unbox_s,      INT_TYPE(32), INT_TYPE(64));
+
         }
     }
 }
 
-} // namespace fp_impl
+}
-} // namespace llvm
+}
-} // namespace iss
+}