fixes missing braces

src/iss/arch/riscv_hart_m_p.h

@@ -448,9 +448,10 @@ riscv_hart_m_p<BASE, FEAT, LOGCAT>::riscv_hart_m_p(feature_config cfg)
     csr[mimpid] = 1;
 
     uart_buf.str("");
-    if(traits<BASE>::FLEN > 0)
+    if(traits<BASE>::FLEN > 0) {
         csr_rd_cb[fcsr] = &this_class::read_fcsr;
         csr_wr_cb[fcsr] = &this_class::write_fcsr;
+    }
     for(unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr) {
         csr_rd_cb[addr] = &this_class::read_null;
         csr_wr_cb[addr] = &this_class::write_plain;

src/iss/arch/riscv_hart_mu_p.h

@@ -478,9 +478,10 @@ riscv_hart_mu_p<BASE, FEAT, LOGCAT>::riscv_hart_mu_p(feature_config cfg)
     csr[mimpid] = 1;
 
     uart_buf.str("");
-    if(traits<BASE>::FLEN > 0)
+    if(traits<BASE>::FLEN > 0) {
         csr_rd_cb[fcsr] = &this_class::read_fcsr;
         csr_wr_cb[fcsr] = &this_class::write_fcsr;
+    }
     for(unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr) {
         csr_rd_cb[addr] = &this_class::read_null;
         csr_wr_cb[addr] = &this_class::write_plain;