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base: DBT-RISE:42efced1eb0b2efbc3b8ed0c5e2a7171a9215f6b
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DBT-RISE:main DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter
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compare: DBT-RISE:edf456c59f9e5a7f69966e4ea6f2583d16ca3719
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DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:main DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter

1 Commits
42efced1eb ... edf456c59f

Author SHA1 Message Date
Eyck Jentzsch
edf456c59f fixes missing braces 2024-08-02 10:33:15 +02:00
2 changed files with 6 additions and 4 deletions
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5
src/iss/arch/riscv_hart_m_p.h
View File

@ -448,9 +448,10 @@ riscv_hart_m_p<BASE, FEAT, LOGCAT>::riscv_hart_m_p(feature_config cfg)
csr[mimpid] = 1; csr[mimpid] = 1;
uart_buf.str(""); uart_buf.str("");
if(traits<BASE>::FLEN > 0) if(traits<BASE>::FLEN > 0) {
csr_rd_cb[fcsr] = &this_class::read_fcsr; csr_rd_cb[fcsr] = &this_class::read_fcsr;
csr_wr_cb[fcsr] = &this_class::write_fcsr; csr_wr_cb[fcsr] = &this_class::write_fcsr;
}
for(unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr) { for(unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr) {
csr_rd_cb[addr] = &this_class::read_null; csr_rd_cb[addr] = &this_class::read_null;
csr_wr_cb[addr] = &this_class::write_plain; csr_wr_cb[addr] = &this_class::write_plain;

5
src/iss/arch/riscv_hart_mu_p.h
View File

@ -478,9 +478,10 @@ riscv_hart_mu_p<BASE, FEAT, LOGCAT>::riscv_hart_mu_p(feature_config cfg)
csr[mimpid] = 1; csr[mimpid] = 1;
uart_buf.str(""); uart_buf.str("");
if(traits<BASE>::FLEN > 0) if(traits<BASE>::FLEN > 0) {
csr_rd_cb[fcsr] = &this_class::read_fcsr; csr_rd_cb[fcsr] = &this_class::read_fcsr;
csr_wr_cb[fcsr] = &this_class::write_fcsr; csr_wr_cb[fcsr] = &this_class::write_fcsr;
}
for(unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr) { for(unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr) {
csr_rd_cb[addr] = &this_class::read_null; csr_rd_cb[addr] = &this_class::read_null;
csr_wr_cb[addr] = &this_class::write_plain; csr_wr_cb[addr] = &this_class::write_plain;