DBT-RISE/DBT-RISE-TGC
12
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

Compare commits

base: DBT-RISE:40db74ce02821b8504db45370438ca2dd18e428e
Branches Tags
DBT-RISE:main DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter
...
compare: DBT-RISE:hotfix/latest_scc
Branches Tags
DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:main DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter

5 Commits
40db74ce02 ... hotfix/lat

Author SHA1 Message Date
Stas
66dc28c239 scc update: scv4tlm -> scv 2021-03-30 11:13:04 +02:00
Stas
40470445f4 fix scv4tlm namespace hierarchy 2021-03-26 21:51:35 +01:00
Stanislaw Kaushanski
ea3ff3c0cd build with SCV lib 2021-03-23 11:57:47 +01:00
Stanislaw Kaushanski
c941890901 SCC refactoring 2021-03-22 14:50:53 +01:00
Stas
b7c0fb2b1c fix bitfield structure 2021-03-10 12:40:06 +01:00
4 changed files with 9 additions and 9 deletions
Expand all files Collapse all files

2
CMakeLists.txt
View File

@ -52,7 +52,7 @@ endif()
add_library(riscv SHARED ${LIB_SOURCES}) add_library(riscv SHARED ${LIB_SOURCES})
target_compile_options(riscv PRIVATE -Wno-shift-count-overflow) target_compile_options(riscv PRIVATE -Wno-shift-count-overflow)
target_include_directories(riscv PUBLIC incl ../external/elfio) target_include_directories(riscv PUBLIC incl ../external/elfio)
target_link_libraries(riscv PUBLIC softfloat scc-util) target_link_libraries(riscv PUBLIC softfloat scc-util jsoncpp)
target_link_libraries(riscv PUBLIC -Wl,--whole-archive dbt-core -Wl,--no-whole-archive) target_link_libraries(riscv PUBLIC -Wl,--whole-archive dbt-core -Wl,--no-whole-archive)
set_target_properties(riscv PROPERTIES set_target_properties(riscv PROPERTIES
VERSION ${PROJECT_VERSION} VERSION ${PROJECT_VERSION}

2
incl/iss/arch/riscv_hart_m_p.h
View File

@ -302,7 +302,7 @@ public:
void write_mstatus(T val) { void write_mstatus(T val) {
auto mask = get_mask(); auto mask = get_mask();
auto new_val = (mstatus.st.value & ~mask) | (val & mask); auto new_val = (mstatus.backing.val & ~mask) | (val & mask);
mstatus = new_val; mstatus = new_val;
} }

6
incl/sysc/core_complex.h
View File

@ -33,10 +33,10 @@
#ifndef _SYSC_SIFIVE_FE310_H_ #ifndef _SYSC_SIFIVE_FE310_H_
#define _SYSC_SIFIVE_FE310_H_ #define _SYSC_SIFIVE_FE310_H_
#include "scc/initiator_mixin.h" #include <tlm/scc/scv/tlm_rec_initiator_socket.h>
#include "tlm/scc/initiator_mixin.h"
#include "scc/traceable.h" #include "scc/traceable.h"
#include "scc/utilities.h" #include "scc/utilities.h"
#include "scv4tlm/tlm_rec_initiator_socket.h"
#include <cci_configuration> #include <cci_configuration>
#include <tlm> #include <tlm>
#include <tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_core_ifs.h> #include <tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_core_ifs.h>
@ -75,7 +75,7 @@ class core_wrapper;
class core_complex : public sc_core::sc_module, public scc::traceable { class core_complex : public sc_core::sc_module, public scc::traceable {
public: public:
scc::initiator_mixin<scv4tlm::tlm_rec_initiator_socket<32>> initiator{"intor"}; tlm::scc::initiator_mixin<tlm::scc::scv::tlm_rec_initiator_socket<32>> initiator{"intor"};
sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"}; sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};

6
src/sysc/core_complex.cpp
View File

@ -331,7 +331,7 @@ void core_complex::disass_output(uint64_t pc, const std::string instr_str) {
tr_handle.record_attribute("PC", pc); tr_handle.record_attribute("PC", pc);
tr_handle.record_attribute("INSTR", instr_str); tr_handle.record_attribute("INSTR", instr_str);
tr_handle.record_attribute("MODE", lvl[cpu->get_mode()]); tr_handle.record_attribute("MODE", lvl[cpu->get_mode()]);
tr_handle.record_attribute("MSTATUS", cpu->get_state().mstatus.st.value); tr_handle.record_attribute("MSTATUS", cpu->get_state().mstatus.backing.val);
tr_handle.record_attribute("LTIME_START", quantum_keeper.get_current_time().value() / 1000); tr_handle.record_attribute("LTIME_START", quantum_keeper.get_current_time().value() / 1000);
#endif #endif
} }
@ -388,7 +388,7 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data,
if (is_fetch && tr_handle.is_active()) { if (is_fetch && tr_handle.is_active()) {
tr_handle.end_transaction(); tr_handle.end_transaction();
} }
auto preExt = new scv4tlm::tlm_recording_extension(tr_handle, this); auto preExt = new tlm::scc::scv4tlm::tlm_recording_extension(tr_handle, this);
gp.set_extension(preExt); gp.set_extension(preExt);
} }
#endif #endif
@ -434,7 +434,7 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
sc_time delay{quantum_keeper.get_local_time()}; sc_time delay{quantum_keeper.get_local_time()};
#ifdef WITH_SCV #ifdef WITH_SCV
if (m_db != nullptr && tr_handle.is_valid()) { if (m_db != nullptr && tr_handle.is_valid()) {
auto preExt = new scv4tlm::tlm_recording_extension(tr_handle, this); auto preExt = new tlm::scc::scv4tlm::tlm_recording_extension(tr_handle, this);
gp.set_extension(preExt); gp.set_extension(preExt);
} }
#endif #endif