remove deprecated functions

gen_input/TGC_B.core_desc

@@ -2,7 +2,7 @@ import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
 import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
 import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
 
-Core TGC_B provides RV32I {
+Core TGC_B provides RV32I, Zicsr, Zifencei {
 	architectural_state {
         XLEN=32;
         // definitions for the architecture wrapper

gen_input/TGC_C.core_desc

@@ -2,7 +2,7 @@ import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
 import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
 import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
 
-Core TGC_C provides RV32I, RV32M, RV32IC {
+Core TGC_C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
     architectural_state {
         XLEN=32;
         // definitions for the architecture wrapper

gen_input/TGC_D.core_desc

@@ -2,7 +2,7 @@ import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
 import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
 import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
 
-Core TGC_D provides RV32I, RV32M, RV32IC {
+Core TGC_D provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
     architectural_state {
         XLEN=32;
         // definitions for the architecture wrapper

gen_input/TGC_D_XRB_MAC.core_desc

@@ -62,7 +62,7 @@ InstructionSet X_RB_MAC extends RISCVBase {
   }
 }
 
-Core TGC_D_XRB_MAC provides RV32I, RV32M, RV32IC, X_RB_MAC {
+Core TGC_D_XRB_MAC provides RV32I, Zicsr, Zifencei, RV32M, RV32IC, X_RB_MAC {
     architectural_state {
         XLEN=32;
         // definitions for the architecture wrapper

gen_input/templates/CORENAME.cpp.gtl

@@ -58,7 +58,9 @@ ${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
 ${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
 
 void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
-    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
+    auto base_ptr = reinterpret_cast<traits<${coreDef.name.toLowerCase()}>::reg_t*>(get_regs_base_ptr());
+    for(size_t i=0; i<traits<tgc_c>::NUM_REGS; ++i)
+        *(base_ptr+i)=0;
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
     reg.PRIV=0x3;

gen_input/templates/CORENAME.h.gtl

@@ -140,14 +140,6 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
     void reset(uint64_t address=0) override;
 
     uint8_t* get_regs_base_ptr() override;
-    /// deprecated
-    void get_reg(short idx, std::vector<uint8_t>& value) override {}
-    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
-    /// deprecated
-    bool get_flag(int flag) override {return false;}
-    void set_flag(int, bool value) override {};
-    /// deprecated
-    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
 
     inline uint64_t get_icount() { return reg.icount; }
 

incl/iss/arch/tgc_c.h

@@ -139,44 +139,45 @@ template <> struct traits<tgc_c> {
         CSRRWI = 47,
         CSRRSI = 48,
         CSRRCI = 49,
-        MUL = 50,
+        FENCE_I = 50,
-        MULH = 51,
+        MUL = 51,
-        MULHSU = 52,
+        MULH = 52,
-        MULHU = 53,
+        MULHSU = 53,
-        DIV = 54,
+        MULHU = 54,
-        DIVU = 55,
+        DIV = 55,
-        REM = 56,
+        DIVU = 56,
-        REMU = 57,
+        REM = 57,
-        CADDI4SPN = 58,
+        REMU = 58,
-        CLW = 59,
+        CADDI4SPN = 59,
-        CSW = 60,
+        CLW = 60,
-        CADDI = 61,
+        CSW = 61,
-        CNOP = 62,
+        CADDI = 62,
-        CJAL = 63,
+        CNOP = 63,
-        CLI = 64,
+        CJAL = 64,
-        CLUI = 65,
+        CLI = 65,
-        CADDI16SP = 66,
+        CLUI = 66,
-        __reserved_clui = 67,
+        CADDI16SP = 67,
-        CSRLI = 68,
+        __reserved_clui = 68,
-        CSRAI = 69,
+        CSRLI = 69,
-        CANDI = 70,
+        CSRAI = 70,
-        CSUB = 71,
+        CANDI = 71,
-        CXOR = 72,
+        CSUB = 72,
-        COR = 73,
+        CXOR = 73,
-        CAND = 74,
+        COR = 74,
-        CJ = 75,
+        CAND = 75,
-        CBEQZ = 76,
+        CJ = 76,
-        CBNEZ = 77,
+        CBEQZ = 77,
-        CSLLI = 78,
+        CBNEZ = 78,
-        CLWSP = 79,
+        CSLLI = 79,
-        CMV = 80,
+        CLWSP = 80,
-        CJR = 81,
+        CMV = 81,
-        __reserved_cmv = 82,
+        CJR = 82,
-        CADD = 83,
+        __reserved_cmv = 83,
-        CJALR = 84,
+        CADD = 84,
-        CEBREAK = 85,
+        CJALR = 85,
-        CSWSP = 86,
+        CEBREAK = 86,
-        DII = 87,
+        CSWSP = 87,
+        DII = 88,
         MAX_OPCODE
     };
 };
@@ -194,14 +195,6 @@ struct tgc_c: public arch_if {
     void reset(uint64_t address=0) override;
 
     uint8_t* get_regs_base_ptr() override;
-    /// deprecated
-    void get_reg(short idx, std::vector<uint8_t>& value) override {}
-    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
-    /// deprecated
-    bool get_flag(int flag) override {return false;}
-    void set_flag(int, bool value) override {};
-    /// deprecated
-    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
 
     inline uint64_t get_icount() { return reg.icount; }
 

src/iss/tgc_c.cpp

@@ -51,7 +51,9 @@ tgc_c::tgc_c() {
 tgc_c::~tgc_c() = default;
 
 void tgc_c::reset(uint64_t address) {
-    for(size_t i=0; i<traits<tgc_c>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<tgc_c>::reg_t),0));
+    auto base_ptr = reinterpret_cast<traits<tgc_c>::reg_t*>(get_regs_base_ptr());
+    for(size_t i=0; i<traits<tgc_c>::NUM_REGS; ++i)
+        *(base_ptr+i)=0;
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
     reg.PRIV=0x3;