DBT-RISE/DBT-RISE-TGC
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base: DBT-RISE:2e670c4d0300d2b17d3f0e62217873971554a65e
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DBT-RISE:main DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter
...
compare: DBT-RISE:d91f5f9df42779bcb4ce6f5ae95b6e1096c89e25
Branches Tags
DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:main DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter

2 Commits
2e670c4d03 ... d91f5f9df4

Author SHA1 Message Date
Eyck Jentzsch
d91f5f9df4 fix compiler warning for reduced number of registers 2022-03-14 15:38:05 +01:00
Stanislaw Kaushanski
5ec457c76b build pctrace plugin only if RapidJSON target is availble 2022-03-08 11:23:07 +01:00
4 changed files with 142 additions and 129 deletions
Expand all files Collapse all files

5
CMakeLists.txt
View File

@ -6,7 +6,7 @@ project(dbt-rise-tgc VERSION 1.0.0)
include(GNUInstallDirs)
find_package(elfio)
find_package(elfio QUIET)
find_package(Boost COMPONENTS coroutine)
if(WITH_LLVM)
@ -35,13 +35,12 @@ FILE(GLOB TGC_VM_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src/vm/interp/vm_*.cpp)
set(LIB_SOURCES
src/vm/fp_functions.cpp
src/plugin/instruction_count.cpp
src/plugin/pctrace.cpp
${TGC_SOURCES}
${TGC_VM_SOURCES}
)
if(TARGET RapidJSON)
list(APPEND LIB_SOURCES src/plugin/cycle_estimate.cpp)
list(APPEND LIB_SOURCES src/plugin/cycle_estimate.cpp src/plugin/pctrace.cpp)
endif()
if(WITH_LLVM)

2
incl/iss/arch/tgc_c.h
View File

@ -53,7 +53,7 @@ template <> struct traits<tgc_c> {
static constexpr std::array<const char*, 36> reg_aliases{
{"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV", "DPC"}};
enum constants {MISA_VAL=0b01000000000000000001000100000100, MARCHID_VAL=0x80000003, XLEN=32, CSR_SIZE=4096, INSTR_ALIGNMENT=2, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
enum constants {MISA_VAL=0b01000000000000000001000100000100, MARCHID_VAL=0x80000003, RFS=32, XLEN=32, CSR_SIZE=4096, INSTR_ALIGNMENT=2, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
constexpr static unsigned FP_REGS_SIZE = 0;

14
incl/iss/debugger/riscv_target_adapter.h
View File

@ -214,13 +214,27 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(cons
auto start_reg=arch::traits<ARCH>::X0;
auto *reg_base = core->get_regs_base_ptr();
auto iter = data.data();
bool e_ext = arch::traits<ARCH>::PC<32;
for (size_t reg_no = 0; reg_no < start_reg+33/*arch::traits<ARCH>::NUM_REGS*/; ++reg_no) {
if(e_ext && reg_no>15){
if(reg_no==32){
auto reg_width = arch::traits<ARCH>::reg_bit_widths[arch::traits<ARCH>::PC] / 8;
auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
std::copy(iter, iter + reg_width, reg_base);
} else {
const uint64_t zero_val=0;
auto reg_width = arch::traits<ARCH>::reg_bit_widths[15] / 8;
auto iter = (uint8_t*)&zero_val;
std::copy(iter, iter + reg_width, reg_base);
}
} else {
auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
std::copy(iter, iter + reg_width, reg_base);
iter += 4;
reg_base += offset;
}
}
return Ok;
}

186
src/vm/interp/vm_tgc_c.cpp
View File

@ -397,7 +397,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 4;
// execute instruction
try {
if(rd != 0) *(X+rd) = (int32_t)imm;
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = (int32_t)imm;
} catch(...){}
}
break;
@ -417,7 +417,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 4;
// execute instruction
try {
if(rd != 0) *(X+rd) = *PC + (int32_t)imm;
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *PC + (int32_t)imm;
} catch(...){}
}
break;
@ -442,7 +442,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 0);
}
else {
if(rd != 0) *(X+rd) = *PC + 4;
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *PC + 4;
pc_assign(*NEXT_PC) = *PC + (int32_t)sext<21>(imm);
}
}
@ -467,12 +467,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
int32_t new_pc = (*(X+rs1) + (int16_t)sext<12>(imm)) & ~ 1;
int32_t new_pc = (*(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm)) & ~ 1;
if(new_pc % traits::INSTR_ALIGNMENT) {
raise(0, 0);
}
else {
if(rd != 0) *(X+rd) = *PC + 4;
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *PC + 4;
pc_assign(*NEXT_PC) = new_pc & ~ 0x1;
}
}
@ -497,7 +497,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
if(*(X+rs1) == *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
if(*(X+rs1 % traits::RFS) == *(X+rs2 % traits::RFS)) if(imm % traits::INSTR_ALIGNMENT) {
raise(0, 0);
}
else {
@ -525,7 +525,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
if(*(X+rs1) != *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
if(*(X+rs1 % traits::RFS) != *(X+rs2 % traits::RFS)) if(imm % traits::INSTR_ALIGNMENT) {
raise(0, 0);
}
else {
@ -553,7 +553,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
if((int32_t)*(X+rs1 % traits::RFS) < (int32_t)*(X+rs2 % traits::RFS)) if(imm % traits::INSTR_ALIGNMENT) {
raise(0, 0);
}
else {
@ -581,7 +581,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
if((int32_t)*(X+rs1 % traits::RFS) >= (int32_t)*(X+rs2 % traits::RFS)) if(imm % traits::INSTR_ALIGNMENT) {
raise(0, 0);
}
else {
@ -609,7 +609,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
if(*(X+rs1) < *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
if(*(X+rs1 % traits::RFS) < *(X+rs2 % traits::RFS)) if(imm % traits::INSTR_ALIGNMENT) {
raise(0, 0);
}
else {
@ -637,7 +637,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
if(*(X+rs1) >= *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
if(*(X+rs1 % traits::RFS) >= *(X+rs2 % traits::RFS)) if(imm % traits::INSTR_ALIGNMENT) {
raise(0, 0);
}
else {
@ -665,8 +665,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
int8_t res = (int8_t)readSpace1(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm));
if(rd != 0) *(X+rd) = res;
int8_t res = (int8_t)readSpace1(traits::MEM, *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm));
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = res;
}
} catch(...){}
}
@ -689,9 +689,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
uint32_t load_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm);
int16_t res = (int16_t)readSpace2(traits::MEM, load_address);
if(rd != 0) *(X+rd) = res;
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = res;
}
} catch(...){}
}
@ -714,9 +714,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
uint32_t load_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm);
int32_t res = (int32_t)readSpace4(traits::MEM, load_address);
if(rd != 0) *(X+rd) = (uint32_t)res;
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = (uint32_t)res;
}
} catch(...){}
}
@ -739,8 +739,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
uint8_t res = (uint8_t)readSpace1(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm));
if(rd != 0) *(X+rd) = res;
uint8_t res = (uint8_t)readSpace1(traits::MEM, *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm));
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = res;
}
} catch(...){}
}
@ -763,9 +763,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
uint32_t load_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm);
uint16_t res = (uint16_t)readSpace2(traits::MEM, load_address);
if(rd != 0) *(X+rd) = res;
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = res;
}
} catch(...){}
}
@ -787,7 +787,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 4;
// execute instruction
try {
writeSpace1(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm), (int8_t)*(X+rs2));
writeSpace1(traits::MEM, *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm), (int8_t)*(X+rs2 % traits::RFS));
} catch(...){}
}
break;
@ -809,8 +809,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
writeSpace2(traits::MEM, store_address, (int16_t)*(X+rs2));
uint32_t store_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm);
writeSpace2(traits::MEM, store_address, (int16_t)*(X+rs2 % traits::RFS));
}
} catch(...){}
}
@ -833,8 +833,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
writeSpace4(traits::MEM, store_address, *(X+rs2));
uint32_t store_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm);
writeSpace4(traits::MEM, store_address, *(X+rs2 % traits::RFS));
}
} catch(...){}
}
@ -856,7 +856,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 4;
// execute instruction
try {
if(rd != 0) *(X+rd) = *(X+rs1) + (int16_t)sext<12>(imm);
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm);
} catch(...){}
}
break;
@ -877,7 +877,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 4;
// execute instruction
try {
if(rd != 0) *(X+rd) = (int32_t)*(X+rs1) < (int16_t)sext<12>(imm)? 1 : 0;
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = (int32_t)*(X+rs1 % traits::RFS) < (int16_t)sext<12>(imm)? 1 : 0;
} catch(...){}
}
break;
@ -898,7 +898,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 4;
// execute instruction
try {
if(rd != 0) *(X+rd) = (*(X+rs1) < (uint32_t)((int16_t)sext<12>(imm)))? 1 : 0;
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = (*(X+rs1 % traits::RFS) < (uint32_t)((int16_t)sext<12>(imm)))? 1 : 0;
} catch(...){}
}
break;
@ -919,7 +919,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 4;
// execute instruction
try {
if(rd != 0) *(X+rd) = *(X+rs1) ^ (int16_t)sext<12>(imm);
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) ^ (int16_t)sext<12>(imm);
} catch(...){}
}
break;
@ -940,7 +940,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 4;
// execute instruction
try {
if(rd != 0) *(X+rd) = *(X+rs1) | (int16_t)sext<12>(imm);
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) | (int16_t)sext<12>(imm);
} catch(...){}
}
break;
@ -961,7 +961,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 4;
// execute instruction
try {
if(rd != 0) *(X+rd) = *(X+rs1) & (int16_t)sext<12>(imm);
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) & (int16_t)sext<12>(imm);
} catch(...){}
}
break;
@ -986,7 +986,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 0);
}
else {
if(rd != 0) *(X+rd) = *(X+rs1) << shamt;
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) << shamt;
}
} catch(...){}
}
@ -1012,7 +1012,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 0);
}
else {
if(rd != 0) *(X+rd) = *(X+rs1) >> shamt;
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) >> shamt;
}
} catch(...){}
}
@ -1038,7 +1038,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 0);
}
else {
if(rd != 0) *(X+rd) = (int32_t)*(X+rs1) >> shamt;
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = (int32_t)*(X+rs1 % traits::RFS) >> shamt;
}
} catch(...){}
}
@ -1060,7 +1060,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 4;
// execute instruction
try {
if(rd != 0) *(X+rd) = *(X+rs1) + *(X+rs2);
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) + *(X+rs2 % traits::RFS);
} catch(...){}
}
break;
@ -1081,7 +1081,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 4;
// execute instruction
try {
if(rd != 0) *(X+rd) = *(X+rs1) - *(X+rs2);
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) - *(X+rs2 % traits::RFS);
} catch(...){}
}
break;
@ -1102,7 +1102,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 4;
// execute instruction
try {
if(rd != 0) *(X+rd) = *(X+rs1) << (*(X+rs2) & (traits::XLEN - 1));
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) << (*(X+rs2 % traits::RFS) & (traits::XLEN - 1));
} catch(...){}
}
break;
@ -1123,7 +1123,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 4;
// execute instruction
try {
if(rd != 0) *(X+rd) = (int32_t)*(X+rs1) < (int32_t)*(X+rs2)? 1 : 0;
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = (int32_t)*(X+rs1 % traits::RFS) < (int32_t)*(X+rs2 % traits::RFS)? 1 : 0;
} catch(...){}
}
break;
@ -1144,7 +1144,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 4;
// execute instruction
try {
if(rd != 0) *(X+rd) = (uint32_t)*(X+rs1) < (uint32_t)*(X+rs2)? 1 : 0;
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = (uint32_t)*(X+rs1 % traits::RFS) < (uint32_t)*(X+rs2 % traits::RFS)? 1 : 0;
} catch(...){}
}
break;
@ -1165,7 +1165,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 4;
// execute instruction
try {
if(rd != 0) *(X+rd) = *(X+rs1) ^ *(X+rs2);
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) ^ *(X+rs2 % traits::RFS);
} catch(...){}
}
break;
@ -1186,7 +1186,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 4;
// execute instruction
try {
if(rd != 0) *(X+rd) = *(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1));
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) >> (*(X+rs2 % traits::RFS) & (traits::XLEN - 1));
} catch(...){}
}
break;
@ -1207,7 +1207,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 4;
// execute instruction
try {
if(rd != 0) *(X+rd) = (int32_t)*(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1));
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = (int32_t)*(X+rs1 % traits::RFS) >> (*(X+rs2 % traits::RFS) & (traits::XLEN - 1));
} catch(...){}
}
break;
@ -1228,7 +1228,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 4;
// execute instruction
try {
if(rd != 0) *(X+rd) = *(X+rs1) | *(X+rs2);
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) | *(X+rs2 % traits::RFS);
} catch(...){}
}
break;
@ -1249,7 +1249,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 4;
// execute instruction
try {
if(rd != 0) *(X+rd) = *(X+rs1) & *(X+rs2);
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) & *(X+rs2 % traits::RFS);
} catch(...){}
}
break;
@ -1401,11 +1401,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
uint32_t xrs1 = *(X+rs1);
if(rd != 0) {
uint32_t xrs1 = *(X+rs1 % traits::RFS);
if((rd % traits::RFS) != 0) {
uint32_t xrd = readSpace4(traits::CSR, csr);
writeSpace4(traits::CSR, csr, xrs1);
*(X+rd) = xrd;
*(X+rd % traits::RFS) = xrd;
}
else {
writeSpace4(traits::CSR, csr, xrs1);
@ -1433,9 +1433,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
try {
{
uint32_t xrd = readSpace4(traits::CSR, csr);
uint32_t xrs1 = *(X+rs1);
uint32_t xrs1 = *(X+rs1 % traits::RFS);
if(rs1 != 0) writeSpace4(traits::CSR, csr, xrd | xrs1);
if(rd != 0) *(X+rd) = xrd;
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = xrd;
}
} catch(...){}
}
@ -1459,9 +1459,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
try {
{
uint32_t xrd = readSpace4(traits::CSR, csr);
uint32_t xrs1 = *(X+rs1);
uint32_t xrs1 = *(X+rs1 % traits::RFS);
if(rs1 != 0) writeSpace4(traits::CSR, csr, xrd & ~ xrs1);
if(rd != 0) *(X+rd) = xrd;
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = xrd;
}
} catch(...){}
}
@ -1486,7 +1486,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
{
uint32_t xrd = readSpace4(traits::CSR, csr);
writeSpace4(traits::CSR, csr, (uint32_t)zimm);
if(rd != 0) *(X+rd) = xrd;
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = xrd;
}
} catch(...){}
}
@ -1511,7 +1511,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
{
uint32_t xrd = readSpace4(traits::CSR, csr);
if(zimm != 0) writeSpace4(traits::CSR, csr, xrd | (uint32_t)zimm);
if(rd != 0) *(X+rd) = xrd;
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = xrd;
}
} catch(...){}
}
@ -1536,7 +1536,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
{
uint32_t xrd = readSpace4(traits::CSR, csr);
if(zimm != 0) writeSpace4(traits::CSR, csr, xrd & ~ ((uint32_t)zimm));
if(rd != 0) *(X+rd) = xrd;
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = xrd;
}
} catch(...){}
}
@ -1579,9 +1579,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
if(rd != 0) {
int64_t res = (int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2);
*(X+rd) = (uint32_t)res;
if((rd % traits::RFS) != 0) {
int64_t res = (int64_t)(int32_t)*(X+rs1 % traits::RFS) * (int64_t)(int32_t)*(X+rs2 % traits::RFS);
*(X+rd % traits::RFS) = (uint32_t)res;
}
}
} catch(...){}
@ -1605,9 +1605,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
if(rd != 0) {
int64_t res = (int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2);
*(X+rd) = (uint32_t)(res >> traits::XLEN);
if((rd % traits::RFS) != 0) {
int64_t res = (int64_t)(int32_t)*(X+rs1 % traits::RFS) * (int64_t)(int32_t)*(X+rs2 % traits::RFS);
*(X+rd % traits::RFS) = (uint32_t)(res >> traits::XLEN);
}
}
} catch(...){}
@ -1631,9 +1631,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
if(rd != 0) {
int64_t res = (int64_t)(int32_t)*(X+rs1) * (uint64_t)*(X+rs2);
*(X+rd) = (uint32_t)(res >> traits::XLEN);
if((rd % traits::RFS) != 0) {
int64_t res = (int64_t)(int32_t)*(X+rs1 % traits::RFS) * (uint64_t)*(X+rs2 % traits::RFS);
*(X+rd % traits::RFS) = (uint32_t)(res >> traits::XLEN);
}
}
} catch(...){}
@ -1657,9 +1657,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
if(rd != 0) {
uint64_t res = (uint64_t)*(X+rs1) * (uint64_t)*(X+rs2);
*(X+rd) = (uint32_t)(res >> traits::XLEN);
if((rd % traits::RFS) != 0) {
uint64_t res = (uint64_t)*(X+rs1 % traits::RFS) * (uint64_t)*(X+rs2 % traits::RFS);
*(X+rd % traits::RFS) = (uint32_t)(res >> traits::XLEN);
}
}
} catch(...){}
@ -1683,13 +1683,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
if(rd != 0) {
if(*(X+rs2) != 0) {
if((rd % traits::RFS) != 0) {
if(*(X+rs2 % traits::RFS) != 0) {
uint32_t MMIN = 1 << (traits::XLEN - 1);
if(*(X+rs1) == MMIN && (int32_t)*(X+rs2) == - 1) *(X+rd) = MMIN;
else *(X+rd) = (int32_t)*(X+rs1) / (int32_t)*(X+rs2);
if(*(X+rs1 % traits::RFS) == MMIN && (int32_t)*(X+rs2 % traits::RFS) == - 1) *(X+rd % traits::RFS) = MMIN;
else *(X+rd % traits::RFS) = (int32_t)*(X+rs1 % traits::RFS) / (int32_t)*(X+rs2 % traits::RFS);
}
else *(X+rd) = - 1;
else *(X+rd % traits::RFS) = - 1;
}
}
} catch(...){}
@ -1713,9 +1713,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
if(rd != 0) {
if(*(X+rs2) != 0) *(X+rd) = *(X+rs1) / *(X+rs2);
else *(X+rd) = - 1;
if((rd % traits::RFS) != 0) {
if(*(X+rs2 % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) / *(X+rs2 % traits::RFS);
else *(X+rd % traits::RFS) = - 1;
}
}
} catch(...){}
@ -1739,13 +1739,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
if(rd != 0) {
if(*(X+rs2) != 0) {
if((rd % traits::RFS) != 0) {
if(*(X+rs2 % traits::RFS) != 0) {
uint32_t MMIN = 1 << (traits::XLEN - 1);
if(*(X+rs1) == MMIN && (int32_t)*(X+rs2) == - 1) *(X+rd) = 0;
else *(X+rd) = (int32_t)*(X+rs1) % (int32_t)*(X+rs2);
if(*(X+rs1 % traits::RFS) == MMIN && (int32_t)*(X+rs2 % traits::RFS) == - 1) *(X+rd % traits::RFS) = 0;
else *(X+rd % traits::RFS) = (int32_t)*(X+rs1 % traits::RFS) % (int32_t)*(X+rs2 % traits::RFS);
}
else *(X+rd) = *(X+rs1);
else *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS);
}
}
} catch(...){}
@ -1769,9 +1769,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
if(rd != 0) {
if(*(X+rs2) != 0) *(X+rd) = *(X+rs1) % *(X+rs2);
else *(X+rd) = *(X+rs1);
if((rd % traits::RFS) != 0) {
if(*(X+rs2 % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) % *(X+rs2 % traits::RFS);
else *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS);
}
}
} catch(...){}
@ -1862,7 +1862,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 2;
// execute instruction
try {
*(X+rs1) = *(X+rs1) + (int8_t)sext<6>(imm);
*(X+rs1 % traits::RFS) = *(X+rs1 % traits::RFS) + (int8_t)sext<6>(imm);
} catch(...){}
}
break;
@ -1921,7 +1921,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
if(rd != 0) *(X+rd) = (uint32_t)(int32_t)sext<6>(imm);
if((rd % traits::RFS) != 0) *(X+rd) = (uint32_t)(int32_t)sext<6>(imm);
}
} catch(...){}
}
@ -1944,7 +1944,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
try {
{
if(imm == 0) raise(0, 2);
if(rd != 0) *(X+rd) = (int32_t)sext<18>(imm);
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = (int32_t)sext<18>(imm);
}
} catch(...){}
}
@ -2223,7 +2223,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 2;
// execute instruction
try {
if(nzuimm) *(X+rs1) = *(X+rs1) << nzuimm;
if(nzuimm) *(X+rs1 % traits::RFS) = *(X+rs1 % traits::RFS) << nzuimm;
} catch(...){}
}
break;
@ -2245,7 +2245,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
try {
if(rd) {
uint32_t offs = *(X+2) + uimm;
*(X+rd) = (int32_t)readSpace4(traits::MEM, offs);
*(X+rd % traits::RFS) = (int32_t)readSpace4(traits::MEM, offs);
}
else raise(0, 2);
} catch(...){}
@ -2267,7 +2267,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 2;
// execute instruction
try {
if(rd != 0) *(X+rd) = *(X+rs2);
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs2 % traits::RFS);
} catch(...){}
}
break;
@ -2286,7 +2286,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 2;
// execute instruction
try {
if(rs1) pc_assign(*NEXT_PC) = *(X+rs1) & ~ 0x1;
if(rs1) pc_assign(*NEXT_PC) = *(X+rs1 % traits::RFS) & ~ 0x1;
else raise(0, 2);
} catch(...){}
}
@ -2321,7 +2321,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 2;
// execute instruction
try {
if(rd != 0) *(X+rd) = *(X+rd) + *(X+rs2);
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rd % traits::RFS) + *(X+rs2 % traits::RFS);
} catch(...){}
}
break;
@ -2341,7 +2341,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
int32_t new_pc = *(X+rs1);
int32_t new_pc = *(X+rs1 % traits::RFS);
*(X+1) = *PC + 2;
pc_assign(*NEXT_PC) = new_pc & ~ 0x1;
}
@ -2380,7 +2380,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
try {
{
uint32_t offs = *(X+2) + uimm;
writeSpace4(traits::MEM, offs, (uint32_t)*(X+rs2));
writeSpace4(traits::MEM, offs, (uint32_t)*(X+rs2 % traits::RFS));
}
} catch(...){}
}