DBT-RISE/DBT-RISE-TGC
9
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

Compare commits

base: DBT-RISE:1a0fc4bd5d544dc6809979ab4829daefc321d2e2
Branches Tags
DBT-RISE:main DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter
...
compare: DBT-RISE:7113683ee0fc96dc99a252f6aed63df7dd73ddf1
Branches Tags
DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:main DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter

1 Commits
1a0fc4bd5d ... 7113683ee0

Author SHA1 Message Date
Eyck Jentzsch
7113683ee0 moves pending interrupt check before handling trap thus saving 1 cycle 2022-10-15 10:47:35 +02:00
2 changed files with 4 additions and 2 deletions
Expand all files Collapse all files

3
gen_input/templates/interp/CORENAME.cpp.gtl
View File

@@ -289,6 +289,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// post execution stuff // post execution stuff
process_spawn_blocks(); process_spawn_blocks();
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id)); if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
if(!this->core.trap_state) // update trap state if there is a pending interrupt
this->core.trap_state = this->core.pending_trap;
// trap check // trap check
if(trap_state!=0){ if(trap_state!=0){
super::core.enter_trap(trap_state, pc.val, instr); super::core.enter_trap(trap_state, pc.val, instr);
@@ -299,7 +301,6 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
cycle++; cycle++;
pc.val=*NEXT_PC; pc.val=*NEXT_PC;
this->core.reg.PC = this->core.reg.NEXT_PC; this->core.reg.PC = this->core.reg.NEXT_PC;
this->core.trap_state = this->core.pending_trap;
} }
} }
return pc; return pc;

3
src/vm/interp/vm_tgc_c.cpp
View File

@@ -2318,6 +2318,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// post execution stuff // post execution stuff
process_spawn_blocks(); process_spawn_blocks();
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id)); if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
if(!this->core.trap_state) // update trap state if there is a pending interrupt
this->core.trap_state = this->core.pending_trap;
// trap check // trap check
if(trap_state!=0){ if(trap_state!=0){
super::core.enter_trap(trap_state, pc.val, instr); super::core.enter_trap(trap_state, pc.val, instr);
@@ -2328,7 +2330,6 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
cycle++; cycle++;
pc.val=*NEXT_PC; pc.val=*NEXT_PC;
this->core.reg.PC = this->core.reg.NEXT_PC; this->core.reg.PC = this->core.reg.NEXT_PC;
this->core.trap_state = this->core.pending_trap;
} }
} }
return pc; return pc;