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base: DBT-RISE:039746112bcfb7e447fe09091501a3a454220b6a
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DBT-RISE:main DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter
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compare: DBT-RISE:459794b863c8707071f72667a33a10d7dd1f7c76
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DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:main DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter

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039746112b ... 459794b863

Author SHA1 Message Date
Eyck Jentzsch
459794b863 add proper handling of store access fault (hart_mu_p) 2021-11-06 13:29:11 +01:00
1 changed files with 1 additions and 0 deletions
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incl/iss/arch/riscv_hart_mu_p.h
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@@ -1235,6 +1235,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
break; break;
case 4: case 4:
case 6: case 6:
case 7:
csr[utval | (new_priv << 8)] = fault_data; csr[utval | (new_priv << 8)] = fault_data;
break; break;
default: default: