removes decoder again as there is some issue
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18f33b4a68
commit
feaa49d367
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@ -37,7 +37,6 @@ FILE(GLOB GEN_SOURCES
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set(LIB_SOURCES
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src/iss/plugin/instruction_count.cpp
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src/iss/arch/tgc_c.cpp
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src/iss/arch/tgc_c_decoder.cpp
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src/vm/interp/vm_tgc_c.cpp
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src/vm/fp_functions.cpp
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${GEN_SOURCES}
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@ -69,7 +69,6 @@ def getCString(def val){
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#include <array>
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#include <iss/arch/traits.h>
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#include <iss/arch_if.h>
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#include <iss/arch/instruction_decoder.h>
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#include <iss/vm_if.h>
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namespace iss {
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@ -121,8 +120,6 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
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${instr.instruction.name} = ${index},<%}%>
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MAX_OPCODE
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};
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static std::unique_ptr<instruction_decoder<${coreDef.name.toLowerCase()}>> get_decoder();
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};
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struct ${coreDef.name.toLowerCase()}: public arch_if {
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@ -95,6 +95,7 @@ protected:
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inline const char *name(size_t index){return traits::reg_aliases.at(index);}
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typename arch::traits<ARCH>::opcode_e decode_inst_id(code_word_t instr);
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virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;
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// some compile time constants
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@ -111,7 +112,13 @@ protected:
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std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
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std::array<compile_func, LUT_SIZE> lut_11;
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std::unique_ptr<instruction_decoder<ARCH>> decoder;
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struct instruction_pattern {
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uint32_t value;
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uint32_t mask;
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typename arch::traits<ARCH>::opcode_e id;
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};
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std::array<std::vector<instruction_pattern>, 4> qlut;
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inline void raise(uint16_t trap_id, uint16_t cause){
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auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id;
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@ -133,7 +140,42 @@ protected:
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template<typename T>
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T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;}
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inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){
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auto ret = super::template read_mem<uint8_t>(space, addr);
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if(this->core.trap_state) throw 0;
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return ret;
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}
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inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){
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auto ret = super::template read_mem<uint16_t>(space, addr);
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if(this->core.trap_state) throw 0;
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return ret;
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}
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inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){
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auto ret = super::template read_mem<uint32_t>(space, addr);
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if(this->core.trap_state) throw 0;
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return ret;
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}
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inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){
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auto ret = super::template read_mem<uint64_t>(space, addr);
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if(this->core.trap_state) throw 0;
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return ret;
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}
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inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){
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super::write_mem(space, addr, data);
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if(this->core.trap_state) throw 0;
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}
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inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){
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super::write_mem(space, addr, data);
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if(this->core.trap_state) throw 0;
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}
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inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){
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super::write_mem(space, addr, data);
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if(this->core.trap_state) throw 0;
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}
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inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){
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super::write_mem(space, addr, data);
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if(this->core.trap_state) throw 0;
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}
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template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
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inline S sext(U from) {
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auto mask = (1ULL<<W) - 1;
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@ -153,6 +195,20 @@ protected:
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${it}<%}%>
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<%}%>
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private:
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/****************************************************************************
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* start opcode definitions
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****************************************************************************/
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struct InstructionDesriptor {
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size_t length;
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uint32_t value;
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uint32_t mask;
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typename arch::traits<ARCH>::opcode_e op;
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};
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const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
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/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
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{${instr.length}, ${instr.encoding}, ${instr.mask}, arch::traits<ARCH>::opcode_e::${instr.instruction.name}},<%}%>
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}};
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//static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK;
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iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
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@ -192,7 +248,16 @@ constexpr size_t bit_count(uint32_t u) {
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template <typename ARCH>
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vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
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: vm_base<ARCH>(core, core_id, cluster_id) {
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decoder = traits::get_decoder();
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unsigned id=0;
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for (auto instr : instr_descr) {
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auto quadrant = instr.value & 0x3;
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qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
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}
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for(auto& lut: qlut){
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std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
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return bit_count(a.mask) > bit_count(b.mask);
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});
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}
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}
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inline bool is_count_limit_enabled(finish_cond_e cond){
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@ -203,11 +268,19 @@ inline bool is_jump_to_self_enabled(finish_cond_e cond){
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return (cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF;
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}
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template <typename ARCH>
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typename arch::traits<ARCH>::opcode_e vm_impl<ARCH>::decode_inst_id(code_word_t instr){
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for(auto& e: qlut[instr&0x3]){
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if(!((instr&e.mask) ^ e.value )) return e.id;
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}
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return arch::traits<ARCH>::opcode_e::MAX_OPCODE;
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}
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template <typename ARCH>
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typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
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auto pc=start;
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auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::PC]);
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auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::NEXT_PC]);
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auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
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auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
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auto& trap_state = this->core.trap_state;
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auto& icount = this->core.icount;
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auto& cycle = this->core.cycle;
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@ -224,11 +297,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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} else {
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if (is_jump_to_self_enabled(cond) &&
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(instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
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auto inst_id = static_cast<opcode_e>(decoder->decode_instruction(instr));
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auto inst_id = decode_inst_id(instr);
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// pre execution stuff
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if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
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switch(inst_id){<%instructions.eachWithIndex{instr, idx -> %>
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case opcode_e::${instr.name}: {
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case arch::traits<ARCH>::opcode_e::${instr.name}: {
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<%instr.fields.eachLine{%>${it}
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<%}%>if(this->disass_enabled){
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/* generate console output when executing the command */<%instr.disass.eachLine{%>
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@ -236,8 +309,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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}
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// used registers<%instr.usedVariables.each{ k,v->
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if(v.isArray) {%>
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auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::${k}0]);<% }else{ %>
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auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::${k}]);
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auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %>
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auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
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<%}}%>// calculate next pc value
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*NEXT_PC = *PC + ${instr.length/8};
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// execute instruction<%instr.behavior.eachLine{%>
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@ -36,7 +36,6 @@
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#include <array>
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#include <iss/arch/traits.h>
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#include <iss/arch_if.h>
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#include <iss/arch/instruction_decoder.h>
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#include <iss/vm_if.h>
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namespace iss {
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@ -177,8 +176,6 @@ template <> struct traits<tgc_c> {
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DII = 89,
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MAX_OPCODE
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};
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static std::unique_ptr<instruction_decoder<tgc_c>> get_decoder();
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};
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struct tgc_c: public arch_if {
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