diff --git a/CMakeLists.txt b/CMakeLists.txt
index 5ae4f32..775afc0 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -37,7 +37,6 @@ FILE(GLOB GEN_SOURCES
 set(LIB_SOURCES 
     src/iss/plugin/instruction_count.cpp
 	src/iss/arch/tgc_c.cpp
-    src/iss/arch/tgc_c_decoder.cpp
 	src/vm/interp/vm_tgc_c.cpp
 	src/vm/fp_functions.cpp
     ${GEN_SOURCES}
diff --git a/gen_input/templates/CORENAME.h.gtl b/gen_input/templates/CORENAME.h.gtl
index bd42664..1765fde 100644
--- a/gen_input/templates/CORENAME.h.gtl
+++ b/gen_input/templates/CORENAME.h.gtl
@@ -69,7 +69,6 @@ def getCString(def val){
 #include <array>
 #include <iss/arch/traits.h>
 #include <iss/arch_if.h>
-#include <iss/arch/instruction_decoder.h>
 #include <iss/vm_if.h>
 
 namespace iss {
@@ -121,8 +120,6 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
         ${instr.instruction.name} = ${index},<%}%>
         MAX_OPCODE
     };
-
-    static std::unique_ptr<instruction_decoder<${coreDef.name.toLowerCase()}>> get_decoder();
 };
 
 struct ${coreDef.name.toLowerCase()}: public arch_if {
diff --git a/gen_input/templates/interp/CORENAME.cpp.gtl b/gen_input/templates/interp/CORENAME.cpp.gtl
index 1566f55..1fd65a4 100644
--- a/gen_input/templates/interp/CORENAME.cpp.gtl
+++ b/gen_input/templates/interp/CORENAME.cpp.gtl
@@ -95,6 +95,7 @@ protected:
 
     inline const char *name(size_t index){return traits::reg_aliases.at(index);}
 
+    typename arch::traits<ARCH>::opcode_e decode_inst_id(code_word_t instr);
     virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;
 
     // some compile time constants
@@ -111,7 +112,13 @@ protected:
     std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
     std::array<compile_func, LUT_SIZE> lut_11;
 
-    std::unique_ptr<instruction_decoder<ARCH>> decoder;
+    struct instruction_pattern {
+        uint32_t value;
+        uint32_t mask;
+        typename arch::traits<ARCH>::opcode_e id;
+    };
+
+    std::array<std::vector<instruction_pattern>, 4> qlut;
 
     inline void raise(uint16_t trap_id, uint16_t cause){
         auto trap_val =  0x80ULL << 24 | (cause << 16) | trap_id;
@@ -133,7 +140,42 @@ protected:
 
     template<typename T>
     T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;}
-
+    inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){
+        auto ret = super::template read_mem<uint8_t>(space, addr);
+        if(this->core.trap_state) throw 0;
+        return ret;
+    }
+    inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){
+        auto ret = super::template read_mem<uint16_t>(space, addr);
+        if(this->core.trap_state) throw 0;
+        return ret;
+    }
+    inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){
+        auto ret = super::template read_mem<uint32_t>(space, addr);
+        if(this->core.trap_state) throw 0;
+        return ret;
+    }
+    inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){
+        auto ret = super::template read_mem<uint64_t>(space, addr);
+        if(this->core.trap_state) throw 0;
+        return ret;
+    }
+    inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){
+        super::write_mem(space, addr, data);
+        if(this->core.trap_state) throw 0;
+    }
+    inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){
+        super::write_mem(space, addr, data);
+        if(this->core.trap_state) throw 0;
+    }
+    inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){
+        super::write_mem(space, addr, data);
+        if(this->core.trap_state) throw 0;
+    }
+    inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){
+        super::write_mem(space, addr, data);
+        if(this->core.trap_state) throw 0;
+    }
     template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
     inline S sext(U from) {
         auto mask = (1ULL<<W) - 1;
@@ -153,6 +195,20 @@ protected:
     ${it}<%}%>
 <%}%>
 private:
+    /****************************************************************************
+     * start opcode definitions
+     ****************************************************************************/
+    struct InstructionDesriptor {
+        size_t length;
+        uint32_t value;
+        uint32_t mask;
+        typename arch::traits<ARCH>::opcode_e op;
+    };
+
+    const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
+         /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
+        {${instr.length}, ${instr.encoding}, ${instr.mask}, arch::traits<ARCH>::opcode_e::${instr.instruction.name}},<%}%>
+    }};
 
     //static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK;
     iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
@@ -192,7 +248,16 @@ constexpr size_t bit_count(uint32_t u) {
 template <typename ARCH>
 vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
 : vm_base<ARCH>(core, core_id, cluster_id) {
-    decoder = traits::get_decoder();
+    unsigned id=0;
+    for (auto instr : instr_descr) {
+        auto quadrant = instr.value & 0x3;
+        qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
+    }
+    for(auto& lut: qlut){
+        std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
+            return bit_count(a.mask) > bit_count(b.mask);
+        });
+    }
 }
 
 inline bool is_count_limit_enabled(finish_cond_e cond){
@@ -203,11 +268,19 @@ inline bool is_jump_to_self_enabled(finish_cond_e cond){
     return (cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF;
 }
 
+template <typename ARCH>
+typename arch::traits<ARCH>::opcode_e vm_impl<ARCH>::decode_inst_id(code_word_t instr){
+    for(auto& e: qlut[instr&0x3]){
+        if(!((instr&e.mask) ^ e.value )) return e.id;
+    }
+    return arch::traits<ARCH>::opcode_e::MAX_OPCODE;
+}
+
 template <typename ARCH>
 typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
     auto pc=start;
-    auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::PC]);
-    auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::NEXT_PC]);
+    auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
+    auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
     auto& trap_state = this->core.trap_state;
     auto& icount = this->core.icount;
     auto& cycle = this->core.cycle;
@@ -224,11 +297,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
         } else {
             if (is_jump_to_self_enabled(cond) &&
                     (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
-            auto inst_id = static_cast<opcode_e>(decoder->decode_instruction(instr));
+            auto inst_id = decode_inst_id(instr);
             // pre execution stuff
             if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
             switch(inst_id){<%instructions.eachWithIndex{instr, idx -> %>
-            case opcode_e::${instr.name}: {
+            case arch::traits<ARCH>::opcode_e::${instr.name}: {
                 <%instr.fields.eachLine{%>${it}
                 <%}%>if(this->disass_enabled){
                     /* generate console output when executing the command */<%instr.disass.eachLine{%>
@@ -236,8 +309,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 // used registers<%instr.usedVariables.each{ k,v->
                 if(v.isArray) {%>
-                auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::${k}0]);<% }else{ %> 
-                auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::${k}]);
+                auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %> 
+                auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
                 <%}}%>// calculate next pc value
                 *NEXT_PC = *PC + ${instr.length/8};
                 // execute instruction<%instr.behavior.eachLine{%>
diff --git a/src/iss/arch/tgc_c.h b/src/iss/arch/tgc_c.h
index 02b09b6..8e2ae8a 100644
--- a/src/iss/arch/tgc_c.h
+++ b/src/iss/arch/tgc_c.h
@@ -36,7 +36,6 @@
 #include <array>
 #include <iss/arch/traits.h>
 #include <iss/arch_if.h>
-#include <iss/arch/instruction_decoder.h>
 #include <iss/vm_if.h>
 
 namespace iss {
@@ -177,8 +176,6 @@ template <> struct traits<tgc_c> {
         DII = 89,
         MAX_OPCODE
     };
-
-    static std::unique_ptr<instruction_decoder<tgc_c>> get_decoder();
 };
 
 struct tgc_c: public arch_if {
diff --git a/src/vm/interp/vm_tgc_c.cpp b/src/vm/interp/vm_tgc_c.cpp
index af51eed..2f31d63 100644
--- a/src/vm/interp/vm_tgc_c.cpp
+++ b/src/vm/interp/vm_tgc_c.cpp
@@ -89,6 +89,7 @@ protected:
 
     inline const char *name(size_t index){return traits::reg_aliases.at(index);}
 
+    typename arch::traits<ARCH>::opcode_e decode_inst_id(code_word_t instr);
     virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;
 
     // some compile time constants
@@ -105,7 +106,13 @@ protected:
     std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
     std::array<compile_func, LUT_SIZE> lut_11;
 
-    std::unique_ptr<instruction_decoder<ARCH>> decoder;
+    struct instruction_pattern {
+        uint32_t value;
+        uint32_t mask;
+        typename arch::traits<ARCH>::opcode_e id;
+    };
+
+    std::array<std::vector<instruction_pattern>, 4> qlut;
 
     inline void raise(uint16_t trap_id, uint16_t cause){
         auto trap_val =  0x80ULL << 24 | (cause << 16) | trap_id;
@@ -127,7 +134,42 @@ protected:
 
     template<typename T>
     T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;}
-
+    inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){
+        auto ret = super::template read_mem<uint8_t>(space, addr);
+        if(this->core.trap_state) throw 0;
+        return ret;
+    }
+    inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){
+        auto ret = super::template read_mem<uint16_t>(space, addr);
+        if(this->core.trap_state) throw 0;
+        return ret;
+    }
+    inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){
+        auto ret = super::template read_mem<uint32_t>(space, addr);
+        if(this->core.trap_state) throw 0;
+        return ret;
+    }
+    inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){
+        auto ret = super::template read_mem<uint64_t>(space, addr);
+        if(this->core.trap_state) throw 0;
+        return ret;
+    }
+    inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){
+        super::write_mem(space, addr, data);
+        if(this->core.trap_state) throw 0;
+    }
+    inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){
+        super::write_mem(space, addr, data);
+        if(this->core.trap_state) throw 0;
+    }
+    inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){
+        super::write_mem(space, addr, data);
+        if(this->core.trap_state) throw 0;
+    }
+    inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){
+        super::write_mem(space, addr, data);
+        if(this->core.trap_state) throw 0;
+    }
     template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
     inline S sext(U from) {
         auto mask = (1ULL<<W) - 1;
@@ -145,6 +187,109 @@ protected:
     }
 
 private:
+    /****************************************************************************
+     * start opcode definitions
+     ****************************************************************************/
+    struct InstructionDesriptor {
+        size_t length;
+        uint32_t value;
+        uint32_t mask;
+        typename arch::traits<ARCH>::opcode_e op;
+    };
+
+    const std::array<InstructionDesriptor, 90> instr_descr = {{
+         /* entries are: size, valid value, valid mask, function ptr */
+        {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, arch::traits<ARCH>::opcode_e::LUI},
+        {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, arch::traits<ARCH>::opcode_e::AUIPC},
+        {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, arch::traits<ARCH>::opcode_e::JAL},
+        {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::JALR},
+        {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::BEQ},
+        {32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::BNE},
+        {32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::BLT},
+        {32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::BGE},
+        {32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::BLTU},
+        {32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::BGEU},
+        {32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::LB},
+        {32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::LH},
+        {32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::LW},
+        {32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::LBU},
+        {32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::LHU},
+        {32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::SB},
+        {32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::SH},
+        {32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::SW},
+        {32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::ADDI},
+        {32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::SLTI},
+        {32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::SLTIU},
+        {32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::XORI},
+        {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::ORI},
+        {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::ANDI},
+        {32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::SLLI},
+        {32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::SRLI},
+        {32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::SRAI},
+        {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::ADD},
+        {32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::SUB},
+        {32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::SLL},
+        {32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::SLT},
+        {32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::SLTU},
+        {32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::XOR},
+        {32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::SRL},
+        {32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::SRA},
+        {32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::OR},
+        {32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::AND},
+        {32, 0b00000000000000000000000000001111, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::FENCE},
+        {32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, arch::traits<ARCH>::opcode_e::ECALL},
+        {32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, arch::traits<ARCH>::opcode_e::EBREAK},
+        {32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, arch::traits<ARCH>::opcode_e::URET},
+        {32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, arch::traits<ARCH>::opcode_e::SRET},
+        {32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, arch::traits<ARCH>::opcode_e::MRET},
+        {32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, arch::traits<ARCH>::opcode_e::WFI},
+        {32, 0b01111011001000000000000001110011, 0b11111111111111111111111111111111, arch::traits<ARCH>::opcode_e::DRET},
+        {32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::CSRRW},
+        {32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::CSRRS},
+        {32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::CSRRC},
+        {32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::CSRRWI},
+        {32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::CSRRSI},
+        {32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::CSRRCI},
+        {32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::FENCE_I},
+        {32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::MUL},
+        {32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::MULH},
+        {32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::MULHSU},
+        {32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::MULHU},
+        {32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::DIV},
+        {32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::DIVU},
+        {32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::REM},
+        {32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::REMU},
+        {16, 0b0000000000000000, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CADDI4SPN},
+        {16, 0b0100000000000000, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CLW},
+        {16, 0b1100000000000000, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CSW},
+        {16, 0b0000000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CADDI},
+        {16, 0b0000000000000001, 0b1110111110000011, arch::traits<ARCH>::opcode_e::CNOP},
+        {16, 0b0010000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CJAL},
+        {16, 0b0100000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CLI},
+        {16, 0b0110000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CLUI},
+        {16, 0b0110000100000001, 0b1110111110000011, arch::traits<ARCH>::opcode_e::CADDI16SP},
+        {16, 0b0110000000000001, 0b1111000001111111, arch::traits<ARCH>::opcode_e::__reserved_clui},
+        {16, 0b1000000000000001, 0b1111110000000011, arch::traits<ARCH>::opcode_e::CSRLI},
+        {16, 0b1000010000000001, 0b1111110000000011, arch::traits<ARCH>::opcode_e::CSRAI},
+        {16, 0b1000100000000001, 0b1110110000000011, arch::traits<ARCH>::opcode_e::CANDI},
+        {16, 0b1000110000000001, 0b1111110001100011, arch::traits<ARCH>::opcode_e::CSUB},
+        {16, 0b1000110000100001, 0b1111110001100011, arch::traits<ARCH>::opcode_e::CXOR},
+        {16, 0b1000110001000001, 0b1111110001100011, arch::traits<ARCH>::opcode_e::COR},
+        {16, 0b1000110001100001, 0b1111110001100011, arch::traits<ARCH>::opcode_e::CAND},
+        {16, 0b1010000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CJ},
+        {16, 0b1100000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CBEQZ},
+        {16, 0b1110000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CBNEZ},
+        {16, 0b0000000000000010, 0b1111000000000011, arch::traits<ARCH>::opcode_e::CSLLI},
+        {16, 0b0100000000000010, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CLWSP},
+        {16, 0b1000000000000010, 0b1111000000000011, arch::traits<ARCH>::opcode_e::CMV},
+        {16, 0b1000000000000010, 0b1111000001111111, arch::traits<ARCH>::opcode_e::CJR},
+        {16, 0b1000000000000010, 0b1111111111111111, arch::traits<ARCH>::opcode_e::__reserved_cmv},
+        {16, 0b1001000000000010, 0b1111000000000011, arch::traits<ARCH>::opcode_e::CADD},
+        {16, 0b1001000000000010, 0b1111000001111111, arch::traits<ARCH>::opcode_e::CJALR},
+        {16, 0b1001000000000010, 0b1111111111111111, arch::traits<ARCH>::opcode_e::CEBREAK},
+        {16, 0b1100000000000010, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CSWSP},
+        {16, 0b0000000000000000, 0b1111111111111111, arch::traits<ARCH>::opcode_e::DII},
+    }};
 
     //static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK;
     iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
@@ -184,7 +329,16 @@ constexpr size_t bit_count(uint32_t u) {
 template <typename ARCH>
 vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
 : vm_base<ARCH>(core, core_id, cluster_id) {
-    decoder = traits::get_decoder();
+    unsigned id=0;
+    for (auto instr : instr_descr) {
+        auto quadrant = instr.value & 0x3;
+        qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
+    }
+    for(auto& lut: qlut){
+        std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
+            return bit_count(a.mask) > bit_count(b.mask);
+        });
+    }
 }
 
 inline bool is_count_limit_enabled(finish_cond_e cond){
@@ -195,11 +349,19 @@ inline bool is_jump_to_self_enabled(finish_cond_e cond){
     return (cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF;
 }
 
+template <typename ARCH>
+typename arch::traits<ARCH>::opcode_e vm_impl<ARCH>::decode_inst_id(code_word_t instr){
+    for(auto& e: qlut[instr&0x3]){
+        if(!((instr&e.mask) ^ e.value )) return e.id;
+    }
+    return arch::traits<ARCH>::opcode_e::MAX_OPCODE;
+}
+
 template <typename ARCH>
 typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
     auto pc=start;
-    auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::PC]);
-    auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::NEXT_PC]);
+    auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
+    auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
     auto& trap_state = this->core.trap_state;
     auto& icount = this->core.icount;
     auto& cycle = this->core.cycle;
@@ -216,11 +378,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
         } else {
             if (is_jump_to_self_enabled(cond) &&
                     (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
-            auto inst_id = static_cast<opcode_e>(decoder->decode_instruction(instr));
+            auto inst_id = decode_inst_id(instr);
             // pre execution stuff
             if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
             switch(inst_id){
-            case opcode_e::LUI: {
+            case arch::traits<ARCH>::opcode_e::LUI: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint32_t imm = ((bit_sub<12,20>(instr) << 12));
                 if(this->disass_enabled){
@@ -231,7 +393,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -241,7 +403,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_LUI:break;
             }// @suppress("No break at end of case")
-            case opcode_e::AUIPC: {
+            case arch::traits<ARCH>::opcode_e::AUIPC: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint32_t imm = ((bit_sub<12,20>(instr) << 12));
                 if(this->disass_enabled){
@@ -252,7 +414,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -262,7 +424,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_AUIPC:break;
             }// @suppress("No break at end of case")
-            case opcode_e::JAL: {
+            case arch::traits<ARCH>::opcode_e::JAL: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint32_t imm = ((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20));
                 if(this->disass_enabled){
@@ -273,7 +435,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -290,7 +452,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_JAL:break;
             }// @suppress("No break at end of case")
-            case opcode_e::JALR: {
+            case arch::traits<ARCH>::opcode_e::JALR: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint16_t imm = ((bit_sub<20,12>(instr)));
@@ -302,7 +464,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -320,7 +482,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_JALR:break;
             }// @suppress("No break at end of case")
-            case opcode_e::BEQ: {
+            case arch::traits<ARCH>::opcode_e::BEQ: {
                 uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -332,7 +494,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -348,7 +510,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_BEQ:break;
             }// @suppress("No break at end of case")
-            case opcode_e::BNE: {
+            case arch::traits<ARCH>::opcode_e::BNE: {
                 uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -360,7 +522,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -376,7 +538,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_BNE:break;
             }// @suppress("No break at end of case")
-            case opcode_e::BLT: {
+            case arch::traits<ARCH>::opcode_e::BLT: {
                 uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -388,7 +550,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -404,7 +566,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_BLT:break;
             }// @suppress("No break at end of case")
-            case opcode_e::BGE: {
+            case arch::traits<ARCH>::opcode_e::BGE: {
                 uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -416,7 +578,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -432,7 +594,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_BGE:break;
             }// @suppress("No break at end of case")
-            case opcode_e::BLTU: {
+            case arch::traits<ARCH>::opcode_e::BLTU: {
                 uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -444,7 +606,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -460,7 +622,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_BLTU:break;
             }// @suppress("No break at end of case")
-            case opcode_e::BGEU: {
+            case arch::traits<ARCH>::opcode_e::BGEU: {
                 uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -472,7 +634,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -488,7 +650,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_BGEU:break;
             }// @suppress("No break at end of case")
-            case opcode_e::LB: {
+            case arch::traits<ARCH>::opcode_e::LB: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint16_t imm = ((bit_sub<20,12>(instr)));
@@ -500,7 +662,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -513,7 +675,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_LB:break;
             }// @suppress("No break at end of case")
-            case opcode_e::LH: {
+            case arch::traits<ARCH>::opcode_e::LH: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint16_t imm = ((bit_sub<20,12>(instr)));
@@ -525,7 +687,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -539,7 +701,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_LH:break;
             }// @suppress("No break at end of case")
-            case opcode_e::LW: {
+            case arch::traits<ARCH>::opcode_e::LW: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint16_t imm = ((bit_sub<20,12>(instr)));
@@ -551,7 +713,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -565,7 +727,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_LW:break;
             }// @suppress("No break at end of case")
-            case opcode_e::LBU: {
+            case arch::traits<ARCH>::opcode_e::LBU: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint16_t imm = ((bit_sub<20,12>(instr)));
@@ -577,7 +739,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -590,7 +752,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_LBU:break;
             }// @suppress("No break at end of case")
-            case opcode_e::LHU: {
+            case arch::traits<ARCH>::opcode_e::LHU: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint16_t imm = ((bit_sub<20,12>(instr)));
@@ -602,7 +764,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -616,7 +778,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_LHU:break;
             }// @suppress("No break at end of case")
-            case opcode_e::SB: {
+            case arch::traits<ARCH>::opcode_e::SB: {
                 uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -628,7 +790,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -637,7 +799,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_SB:break;
             }// @suppress("No break at end of case")
-            case opcode_e::SH: {
+            case arch::traits<ARCH>::opcode_e::SH: {
                 uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -649,7 +811,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -659,7 +821,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_SH:break;
             }// @suppress("No break at end of case")
-            case opcode_e::SW: {
+            case arch::traits<ARCH>::opcode_e::SW: {
                 uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -671,7 +833,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -681,7 +843,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_SW:break;
             }// @suppress("No break at end of case")
-            case opcode_e::ADDI: {
+            case arch::traits<ARCH>::opcode_e::ADDI: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint16_t imm = ((bit_sub<20,12>(instr)));
@@ -693,7 +855,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -703,7 +865,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_ADDI:break;
             }// @suppress("No break at end of case")
-            case opcode_e::SLTI: {
+            case arch::traits<ARCH>::opcode_e::SLTI: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint16_t imm = ((bit_sub<20,12>(instr)));
@@ -715,7 +877,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -725,7 +887,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_SLTI:break;
             }// @suppress("No break at end of case")
-            case opcode_e::SLTIU: {
+            case arch::traits<ARCH>::opcode_e::SLTIU: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint16_t imm = ((bit_sub<20,12>(instr)));
@@ -737,7 +899,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -747,7 +909,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_SLTIU:break;
             }// @suppress("No break at end of case")
-            case opcode_e::XORI: {
+            case arch::traits<ARCH>::opcode_e::XORI: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint16_t imm = ((bit_sub<20,12>(instr)));
@@ -759,7 +921,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -769,7 +931,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_XORI:break;
             }// @suppress("No break at end of case")
-            case opcode_e::ORI: {
+            case arch::traits<ARCH>::opcode_e::ORI: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint16_t imm = ((bit_sub<20,12>(instr)));
@@ -781,7 +943,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -791,7 +953,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_ORI:break;
             }// @suppress("No break at end of case")
-            case opcode_e::ANDI: {
+            case arch::traits<ARCH>::opcode_e::ANDI: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint16_t imm = ((bit_sub<20,12>(instr)));
@@ -803,7 +965,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -813,7 +975,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_ANDI:break;
             }// @suppress("No break at end of case")
-            case opcode_e::SLLI: {
+            case arch::traits<ARCH>::opcode_e::SLLI: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t shamt = ((bit_sub<20,5>(instr)));
@@ -825,7 +987,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -840,7 +1002,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_SLLI:break;
             }// @suppress("No break at end of case")
-            case opcode_e::SRLI: {
+            case arch::traits<ARCH>::opcode_e::SRLI: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t shamt = ((bit_sub<20,5>(instr)));
@@ -852,7 +1014,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -867,7 +1029,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_SRLI:break;
             }// @suppress("No break at end of case")
-            case opcode_e::SRAI: {
+            case arch::traits<ARCH>::opcode_e::SRAI: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t shamt = ((bit_sub<20,5>(instr)));
@@ -879,7 +1041,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -894,7 +1056,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_SRAI:break;
             }// @suppress("No break at end of case")
-            case opcode_e::ADD: {
+            case arch::traits<ARCH>::opcode_e::ADD: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -906,7 +1068,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -916,7 +1078,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_ADD:break;
             }// @suppress("No break at end of case")
-            case opcode_e::SUB: {
+            case arch::traits<ARCH>::opcode_e::SUB: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -928,7 +1090,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -938,7 +1100,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_SUB:break;
             }// @suppress("No break at end of case")
-            case opcode_e::SLL: {
+            case arch::traits<ARCH>::opcode_e::SLL: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -950,7 +1112,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -960,7 +1122,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_SLL:break;
             }// @suppress("No break at end of case")
-            case opcode_e::SLT: {
+            case arch::traits<ARCH>::opcode_e::SLT: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -972,7 +1134,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -982,7 +1144,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_SLT:break;
             }// @suppress("No break at end of case")
-            case opcode_e::SLTU: {
+            case arch::traits<ARCH>::opcode_e::SLTU: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -994,7 +1156,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -1004,7 +1166,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_SLTU:break;
             }// @suppress("No break at end of case")
-            case opcode_e::XOR: {
+            case arch::traits<ARCH>::opcode_e::XOR: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -1016,7 +1178,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -1026,7 +1188,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_XOR:break;
             }// @suppress("No break at end of case")
-            case opcode_e::SRL: {
+            case arch::traits<ARCH>::opcode_e::SRL: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -1038,7 +1200,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -1048,7 +1210,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_SRL:break;
             }// @suppress("No break at end of case")
-            case opcode_e::SRA: {
+            case arch::traits<ARCH>::opcode_e::SRA: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -1060,7 +1222,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -1070,7 +1232,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_SRA:break;
             }// @suppress("No break at end of case")
-            case opcode_e::OR: {
+            case arch::traits<ARCH>::opcode_e::OR: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -1082,7 +1244,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -1092,7 +1254,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_OR:break;
             }// @suppress("No break at end of case")
-            case opcode_e::AND: {
+            case arch::traits<ARCH>::opcode_e::AND: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -1104,7 +1266,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -1114,7 +1276,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_AND:break;
             }// @suppress("No break at end of case")
-            case opcode_e::FENCE: {
+            case arch::traits<ARCH>::opcode_e::FENCE: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t succ = ((bit_sub<20,4>(instr)));
@@ -1136,7 +1298,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_FENCE:break;
             }// @suppress("No break at end of case")
-            case opcode_e::ECALL: {
+            case arch::traits<ARCH>::opcode_e::ECALL: {
                 if(this->disass_enabled){
                     /* generate console output when executing the command */
                     this->core.disass_output(pc.val, "ecall");
@@ -1149,7 +1311,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_ECALL:break;
             }// @suppress("No break at end of case")
-            case opcode_e::EBREAK: {
+            case arch::traits<ARCH>::opcode_e::EBREAK: {
                 if(this->disass_enabled){
                     /* generate console output when executing the command */
                     this->core.disass_output(pc.val, "ebreak");
@@ -1162,7 +1324,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_EBREAK:break;
             }// @suppress("No break at end of case")
-            case opcode_e::URET: {
+            case arch::traits<ARCH>::opcode_e::URET: {
                 if(this->disass_enabled){
                     /* generate console output when executing the command */
                     this->core.disass_output(pc.val, "uret");
@@ -1175,7 +1337,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_URET:break;
             }// @suppress("No break at end of case")
-            case opcode_e::SRET: {
+            case arch::traits<ARCH>::opcode_e::SRET: {
                 if(this->disass_enabled){
                     /* generate console output when executing the command */
                     this->core.disass_output(pc.val, "sret");
@@ -1188,7 +1350,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_SRET:break;
             }// @suppress("No break at end of case")
-            case opcode_e::MRET: {
+            case arch::traits<ARCH>::opcode_e::MRET: {
                 if(this->disass_enabled){
                     /* generate console output when executing the command */
                     this->core.disass_output(pc.val, "mret");
@@ -1201,7 +1363,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_MRET:break;
             }// @suppress("No break at end of case")
-            case opcode_e::WFI: {
+            case arch::traits<ARCH>::opcode_e::WFI: {
                 if(this->disass_enabled){
                     /* generate console output when executing the command */
                     this->core.disass_output(pc.val, "wfi");
@@ -1214,15 +1376,15 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_WFI:break;
             }// @suppress("No break at end of case")
-            case opcode_e::DRET: {
+            case arch::traits<ARCH>::opcode_e::DRET: {
                 if(this->disass_enabled){
                     /* generate console output when executing the command */
                     this->core.disass_output(pc.val, "dret");
                 }
                 // used registers 
-                auto* PRIV = reinterpret_cast<uint8_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::PRIV]);
+                auto* PRIV = reinterpret_cast<uint8_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PRIV]);
                  
-                auto* DPC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::DPC]);
+                auto* DPC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::DPC]);
                 // calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
@@ -1238,7 +1400,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_DRET:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CSRRW: {
+            case arch::traits<ARCH>::opcode_e::CSRRW: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint16_t csr = ((bit_sub<20,12>(instr)));
@@ -1250,7 +1412,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -1270,7 +1432,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_CSRRW:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CSRRS: {
+            case arch::traits<ARCH>::opcode_e::CSRRS: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint16_t csr = ((bit_sub<20,12>(instr)));
@@ -1282,7 +1444,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -1300,7 +1462,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_CSRRS:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CSRRC: {
+            case arch::traits<ARCH>::opcode_e::CSRRC: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint16_t csr = ((bit_sub<20,12>(instr)));
@@ -1312,7 +1474,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -1330,7 +1492,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_CSRRC:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CSRRWI: {
+            case arch::traits<ARCH>::opcode_e::CSRRWI: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t zimm = ((bit_sub<15,5>(instr)));
                 uint16_t csr = ((bit_sub<20,12>(instr)));
@@ -1342,7 +1504,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -1357,7 +1519,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_CSRRWI:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CSRRSI: {
+            case arch::traits<ARCH>::opcode_e::CSRRSI: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t zimm = ((bit_sub<15,5>(instr)));
                 uint16_t csr = ((bit_sub<20,12>(instr)));
@@ -1369,7 +1531,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -1386,7 +1548,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_CSRRSI:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CSRRCI: {
+            case arch::traits<ARCH>::opcode_e::CSRRCI: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t zimm = ((bit_sub<15,5>(instr)));
                 uint16_t csr = ((bit_sub<20,12>(instr)));
@@ -1398,7 +1560,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -1415,7 +1577,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_CSRRCI:break;
             }// @suppress("No break at end of case")
-            case opcode_e::FENCE_I: {
+            case arch::traits<ARCH>::opcode_e::FENCE_I: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint16_t imm = ((bit_sub<20,12>(instr)));
@@ -1435,7 +1597,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_FENCE_I:break;
             }// @suppress("No break at end of case")
-            case opcode_e::MUL: {
+            case arch::traits<ARCH>::opcode_e::MUL: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -1447,7 +1609,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -1458,7 +1620,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_MUL:break;
             }// @suppress("No break at end of case")
-            case opcode_e::MULH: {
+            case arch::traits<ARCH>::opcode_e::MULH: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -1470,7 +1632,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -1481,7 +1643,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_MULH:break;
             }// @suppress("No break at end of case")
-            case opcode_e::MULHSU: {
+            case arch::traits<ARCH>::opcode_e::MULHSU: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -1493,7 +1655,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -1504,7 +1666,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_MULHSU:break;
             }// @suppress("No break at end of case")
-            case opcode_e::MULHU: {
+            case arch::traits<ARCH>::opcode_e::MULHU: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -1516,7 +1678,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -1527,7 +1689,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_MULHU:break;
             }// @suppress("No break at end of case")
-            case opcode_e::DIV: {
+            case arch::traits<ARCH>::opcode_e::DIV: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -1539,7 +1701,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -1560,7 +1722,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_DIV:break;
             }// @suppress("No break at end of case")
-            case opcode_e::DIVU: {
+            case arch::traits<ARCH>::opcode_e::DIVU: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -1572,7 +1734,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -1587,7 +1749,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_DIVU:break;
             }// @suppress("No break at end of case")
-            case opcode_e::REM: {
+            case arch::traits<ARCH>::opcode_e::REM: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -1599,7 +1761,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -1620,7 +1782,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_REM:break;
             }// @suppress("No break at end of case")
-            case opcode_e::REMU: {
+            case arch::traits<ARCH>::opcode_e::REMU: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 uint8_t rs1 = ((bit_sub<15,5>(instr)));
                 uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -1632,7 +1794,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
@@ -1647,7 +1809,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_REMU:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CADDI4SPN: {
+            case arch::traits<ARCH>::opcode_e::CADDI4SPN: {
                 uint8_t rd = ((bit_sub<2,3>(instr)));
                 uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4));
                 if(this->disass_enabled){
@@ -1658,7 +1820,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
@@ -1671,7 +1833,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_CADDI4SPN:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CLW: {
+            case arch::traits<ARCH>::opcode_e::CLW: {
                 uint8_t rd = ((bit_sub<2,3>(instr)));
                 uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3));
                 uint8_t rs1 = ((bit_sub<7,3>(instr)));
@@ -1683,7 +1845,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
@@ -1694,7 +1856,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_CLW:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CSW: {
+            case arch::traits<ARCH>::opcode_e::CSW: {
                 uint8_t rs2 = ((bit_sub<2,3>(instr)));
                 uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3));
                 uint8_t rs1 = ((bit_sub<7,3>(instr)));
@@ -1706,7 +1868,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
@@ -1716,7 +1878,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_CSW:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CADDI: {
+            case arch::traits<ARCH>::opcode_e::CADDI: {
                 uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
                 uint8_t rs1 = ((bit_sub<7,5>(instr)));
                 if(this->disass_enabled){
@@ -1727,7 +1889,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
@@ -1735,7 +1897,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_CADDI:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CNOP: {
+            case arch::traits<ARCH>::opcode_e::CNOP: {
                 uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
                 if(this->disass_enabled){
                     /* generate console output when executing the command */
@@ -1748,7 +1910,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_CNOP:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CJAL: {
+            case arch::traits<ARCH>::opcode_e::CJAL: {
                 uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11));
                 if(this->disass_enabled){
                     /* generate console output when executing the command */
@@ -1758,7 +1920,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
@@ -1768,7 +1930,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_CJAL:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CLI: {
+            case arch::traits<ARCH>::opcode_e::CLI: {
                 uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 if(this->disass_enabled){
@@ -1779,7 +1941,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
@@ -1789,7 +1951,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_CLI:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CLUI: {
+            case arch::traits<ARCH>::opcode_e::CLUI: {
                 uint32_t imm = ((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17));
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 if(this->disass_enabled){
@@ -1800,7 +1962,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
@@ -1813,7 +1975,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_CLUI:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CADDI16SP: {
+            case arch::traits<ARCH>::opcode_e::CADDI16SP: {
                 uint16_t nzimm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9));
                 if(this->disass_enabled){
                     /* generate console output when executing the command */
@@ -1823,7 +1985,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
@@ -1836,7 +1998,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_CADDI16SP:break;
             }// @suppress("No break at end of case")
-            case opcode_e::__reserved_clui: {
+            case arch::traits<ARCH>::opcode_e::__reserved_clui: {
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 if(this->disass_enabled){
                     /* generate console output when executing the command */
@@ -1850,7 +2012,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP___reserved_clui:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CSRLI: {
+            case arch::traits<ARCH>::opcode_e::CSRLI: {
                 uint8_t shamt = ((bit_sub<2,5>(instr)));
                 uint8_t rs1 = ((bit_sub<7,3>(instr)));
                 if(this->disass_enabled){
@@ -1861,7 +2023,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
@@ -1870,7 +2032,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_CSRLI:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CSRAI: {
+            case arch::traits<ARCH>::opcode_e::CSRAI: {
                 uint8_t shamt = ((bit_sub<2,5>(instr)));
                 uint8_t rs1 = ((bit_sub<7,3>(instr)));
                 if(this->disass_enabled){
@@ -1881,7 +2043,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
@@ -1898,7 +2060,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_CSRAI:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CANDI: {
+            case arch::traits<ARCH>::opcode_e::CANDI: {
                 uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
                 uint8_t rs1 = ((bit_sub<7,3>(instr)));
                 if(this->disass_enabled){
@@ -1909,7 +2071,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
@@ -1918,7 +2080,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_CANDI:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CSUB: {
+            case arch::traits<ARCH>::opcode_e::CSUB: {
                 uint8_t rs2 = ((bit_sub<2,3>(instr)));
                 uint8_t rd = ((bit_sub<7,3>(instr)));
                 if(this->disass_enabled){
@@ -1929,7 +2091,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
@@ -1938,7 +2100,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_CSUB:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CXOR: {
+            case arch::traits<ARCH>::opcode_e::CXOR: {
                 uint8_t rs2 = ((bit_sub<2,3>(instr)));
                 uint8_t rd = ((bit_sub<7,3>(instr)));
                 if(this->disass_enabled){
@@ -1949,7 +2111,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
@@ -1958,7 +2120,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_CXOR:break;
             }// @suppress("No break at end of case")
-            case opcode_e::COR: {
+            case arch::traits<ARCH>::opcode_e::COR: {
                 uint8_t rs2 = ((bit_sub<2,3>(instr)));
                 uint8_t rd = ((bit_sub<7,3>(instr)));
                 if(this->disass_enabled){
@@ -1969,7 +2131,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
@@ -1978,7 +2140,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_COR:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CAND: {
+            case arch::traits<ARCH>::opcode_e::CAND: {
                 uint8_t rs2 = ((bit_sub<2,3>(instr)));
                 uint8_t rd = ((bit_sub<7,3>(instr)));
                 if(this->disass_enabled){
@@ -1989,7 +2151,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
@@ -1998,7 +2160,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_CAND:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CJ: {
+            case arch::traits<ARCH>::opcode_e::CJ: {
                 uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11));
                 if(this->disass_enabled){
                     /* generate console output when executing the command */
@@ -2016,7 +2178,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_CJ:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CBEQZ: {
+            case arch::traits<ARCH>::opcode_e::CBEQZ: {
                 uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8));
                 uint8_t rs1 = ((bit_sub<7,3>(instr)));
                 if(this->disass_enabled){
@@ -2027,7 +2189,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
@@ -2038,7 +2200,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_CBEQZ:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CBNEZ: {
+            case arch::traits<ARCH>::opcode_e::CBNEZ: {
                 uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8));
                 uint8_t rs1 = ((bit_sub<7,3>(instr)));
                 if(this->disass_enabled){
@@ -2049,7 +2211,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
@@ -2060,7 +2222,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_CBNEZ:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CSLLI: {
+            case arch::traits<ARCH>::opcode_e::CSLLI: {
                 uint8_t nzuimm = ((bit_sub<2,5>(instr)));
                 uint8_t rs1 = ((bit_sub<7,5>(instr)));
                 if(this->disass_enabled){
@@ -2071,7 +2233,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
@@ -2081,7 +2243,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_CSLLI:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CLWSP: {
+            case arch::traits<ARCH>::opcode_e::CLWSP: {
                 uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5));
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 if(this->disass_enabled){
@@ -2092,7 +2254,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
@@ -2108,7 +2270,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_CLWSP:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CMV: {
+            case arch::traits<ARCH>::opcode_e::CMV: {
                 uint8_t rs2 = ((bit_sub<2,5>(instr)));
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 if(this->disass_enabled){
@@ -2119,7 +2281,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
@@ -2129,7 +2291,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_CMV:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CJR: {
+            case arch::traits<ARCH>::opcode_e::CJR: {
                 uint8_t rs1 = ((bit_sub<7,5>(instr)));
                 if(this->disass_enabled){
                     /* generate console output when executing the command */
@@ -2139,7 +2301,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
@@ -2153,7 +2315,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_CJR:break;
             }// @suppress("No break at end of case")
-            case opcode_e::__reserved_cmv: {
+            case arch::traits<ARCH>::opcode_e::__reserved_cmv: {
                 if(this->disass_enabled){
                     /* generate console output when executing the command */
                     this->core.disass_output(pc.val, "__reserved_cmv");
@@ -2166,7 +2328,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP___reserved_cmv:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CADD: {
+            case arch::traits<ARCH>::opcode_e::CADD: {
                 uint8_t rs2 = ((bit_sub<2,5>(instr)));
                 uint8_t rd = ((bit_sub<7,5>(instr)));
                 if(this->disass_enabled){
@@ -2177,7 +2339,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
@@ -2187,7 +2349,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_CADD:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CJALR: {
+            case arch::traits<ARCH>::opcode_e::CJALR: {
                 uint8_t rs1 = ((bit_sub<7,5>(instr)));
                 if(this->disass_enabled){
                     /* generate console output when executing the command */
@@ -2197,7 +2359,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
@@ -2208,7 +2370,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_CJALR:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CEBREAK: {
+            case arch::traits<ARCH>::opcode_e::CEBREAK: {
                 if(this->disass_enabled){
                     /* generate console output when executing the command */
                     this->core.disass_output(pc.val, "cebreak");
@@ -2221,7 +2383,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                             }
                 TRAP_CEBREAK:break;
             }// @suppress("No break at end of case")
-            case opcode_e::CSWSP: {
+            case arch::traits<ARCH>::opcode_e::CSWSP: {
                 uint8_t rs2 = ((bit_sub<2,5>(instr)));
                 uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2));
                 if(this->disass_enabled){
@@ -2232,7 +2394,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
-                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value
+                auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
@@ -2242,7 +2404,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 }
                 TRAP_CSWSP:break;
             }// @suppress("No break at end of case")
-            case opcode_e::DII: {
+            case arch::traits<ARCH>::opcode_e::DII: {
                 if(this->disass_enabled){
                     /* generate console output when executing the command */
                     this->core.disass_output(pc.val, "dii");