fixes wrong check for exception
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parent
00e02bf565
commit
fa7eda0889
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@ -629,7 +629,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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{
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uint32_t load_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm);
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int8_t read_res = super::template read_mem<int8_t>(traits::MEM, load_address);
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if(this->core.trap_state) goto TRAP_LB;
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if(this->core.trap_state>=0x80000000UL) goto TRAP_LB;
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int8_t res = (int8_t)read_res;
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if((rd % traits::RFS) != 0) {
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*(X+rd % traits::RFS) = (int32_t)res;
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@ -655,7 +655,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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{
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uint32_t load_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm);
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int16_t read_res = super::template read_mem<int16_t>(traits::MEM, load_address);
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if(this->core.trap_state) goto TRAP_LH;
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if(this->core.trap_state>=0x80000000UL) goto TRAP_LH;
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int16_t res = (int16_t)read_res;
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if((rd % traits::RFS) != 0) {
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*(X+rd % traits::RFS) = (int32_t)res;
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@ -681,7 +681,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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{
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uint32_t load_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm);
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int32_t read_res = super::template read_mem<int32_t>(traits::MEM, load_address);
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if(this->core.trap_state) goto TRAP_LW;
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if(this->core.trap_state>=0x80000000UL) goto TRAP_LW;
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int32_t res = (int32_t)read_res;
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if((rd % traits::RFS) != 0) {
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*(X+rd % traits::RFS) = (int32_t)res;
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@ -707,7 +707,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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{
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uint32_t load_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm);
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uint8_t read_res = super::template read_mem<uint8_t>(traits::MEM, load_address);
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if(this->core.trap_state) goto TRAP_LBU;
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if(this->core.trap_state>=0x80000000UL) goto TRAP_LBU;
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uint8_t res = (uint8_t)read_res;
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if((rd % traits::RFS) != 0) {
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*(X+rd % traits::RFS) = (uint32_t)res;
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@ -733,7 +733,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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{
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uint32_t load_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm);
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uint16_t read_res = super::template read_mem<uint16_t>(traits::MEM, load_address);
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if(this->core.trap_state) goto TRAP_LHU;
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if(this->core.trap_state>=0x80000000UL) goto TRAP_LHU;
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uint16_t res = (uint16_t)read_res;
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if((rd % traits::RFS) != 0) {
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*(X+rd % traits::RFS) = (uint32_t)res;
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@ -759,7 +759,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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{
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uint32_t store_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm);
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super::template write_mem<uint8_t>(traits::MEM, store_address, (int8_t)*(X+rs2 % traits::RFS));
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if(this->core.trap_state) goto TRAP_SB;
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if(this->core.trap_state>=0x80000000UL) goto TRAP_SB;
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}
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TRAP_SB:break;
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}// @suppress("No break at end of case")
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@ -781,7 +781,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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{
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uint32_t store_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm);
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super::template write_mem<uint16_t>(traits::MEM, store_address, (int16_t)*(X+rs2 % traits::RFS));
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if(this->core.trap_state) goto TRAP_SH;
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if(this->core.trap_state>=0x80000000UL) goto TRAP_SH;
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}
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TRAP_SH:break;
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}// @suppress("No break at end of case")
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@ -803,7 +803,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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{
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uint32_t store_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm);
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super::template write_mem<uint32_t>(traits::MEM, store_address, (int32_t)*(X+rs2 % traits::RFS));
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if(this->core.trap_state) goto TRAP_SW;
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if(this->core.trap_state>=0x80000000UL) goto TRAP_SW;
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}
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TRAP_SW:break;
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}// @suppress("No break at end of case")
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@ -1243,7 +1243,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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{
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super::template write_mem<uint8_t>(traits::FENCE, traits::fence, pred << 4 | succ);
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if(this->core.trap_state) goto TRAP_FENCE;
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if(this->core.trap_state>=0x80000000UL) goto TRAP_FENCE;
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}
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TRAP_FENCE:break;
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}// @suppress("No break at end of case")
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@ -1318,15 +1318,15 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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uint32_t xrs1 = *(X+rs1 % traits::RFS);
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if((rd % traits::RFS) != 0) {
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uint32_t read_res = super::template read_mem<uint32_t>(traits::CSR, csr);
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if(this->core.trap_state) goto TRAP_CSRRW;
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if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRW;
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uint32_t xrd = read_res;
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super::template write_mem<uint32_t>(traits::CSR, csr, xrs1);
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if(this->core.trap_state) goto TRAP_CSRRW;
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if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRW;
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*(X+rd % traits::RFS) = xrd;
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}
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else {
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super::template write_mem<uint32_t>(traits::CSR, csr, xrs1);
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if(this->core.trap_state) goto TRAP_CSRRW;
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if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRW;
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}
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}
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TRAP_CSRRW:break;
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@ -1348,12 +1348,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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{
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uint32_t read_res = super::template read_mem<uint32_t>(traits::CSR, csr);
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if(this->core.trap_state) goto TRAP_CSRRS;
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if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRS;
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uint32_t xrd = read_res;
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uint32_t xrs1 = *(X+rs1 % traits::RFS);
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if(rs1 != 0) {
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super::template write_mem<uint32_t>(traits::CSR, csr, xrd | xrs1);
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if(this->core.trap_state) goto TRAP_CSRRS;
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if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRS;
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}
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if((rd % traits::RFS) != 0) {
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*(X+rd % traits::RFS) = xrd;
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@ -1378,12 +1378,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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{
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uint32_t read_res = super::template read_mem<uint32_t>(traits::CSR, csr);
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if(this->core.trap_state) goto TRAP_CSRRC;
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if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRC;
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uint32_t xrd = read_res;
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uint32_t xrs1 = *(X+rs1 % traits::RFS);
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if(rs1 != 0) {
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super::template write_mem<uint32_t>(traits::CSR, csr, xrd & ~ xrs1);
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if(this->core.trap_state) goto TRAP_CSRRC;
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if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRC;
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}
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if((rd % traits::RFS) != 0) {
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*(X+rd % traits::RFS) = xrd;
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@ -1408,10 +1408,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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{
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uint32_t read_res = super::template read_mem<uint32_t>(traits::CSR, csr);
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if(this->core.trap_state) goto TRAP_CSRRWI;
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if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRWI;
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uint32_t xrd = read_res;
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super::template write_mem<uint32_t>(traits::CSR, csr, (uint32_t)zimm);
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if(this->core.trap_state) goto TRAP_CSRRWI;
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if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRWI;
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if((rd % traits::RFS) != 0) {
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*(X+rd % traits::RFS) = xrd;
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}
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@ -1435,11 +1435,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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{
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uint32_t read_res = super::template read_mem<uint32_t>(traits::CSR, csr);
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if(this->core.trap_state) goto TRAP_CSRRSI;
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if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRSI;
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uint32_t xrd = read_res;
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if(zimm != 0) {
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super::template write_mem<uint32_t>(traits::CSR, csr, xrd | (uint32_t)zimm);
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if(this->core.trap_state) goto TRAP_CSRRSI;
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if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRSI;
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}
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if((rd % traits::RFS) != 0) {
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*(X+rd % traits::RFS) = xrd;
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@ -1464,11 +1464,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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{
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uint32_t read_res = super::template read_mem<uint32_t>(traits::CSR, csr);
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if(this->core.trap_state) goto TRAP_CSRRCI;
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if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRCI;
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uint32_t xrd = read_res;
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if(zimm != 0) {
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super::template write_mem<uint32_t>(traits::CSR, csr, xrd & ~ ((uint32_t)zimm));
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if(this->core.trap_state) goto TRAP_CSRRCI;
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if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRCI;
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}
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if((rd % traits::RFS) != 0) {
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*(X+rd % traits::RFS) = xrd;
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@ -1492,7 +1492,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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{
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super::template write_mem<uint16_t>(traits::FENCE, traits::fencei, imm);
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if(this->core.trap_state) goto TRAP_FENCE_I;
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if(this->core.trap_state>=0x80000000UL) goto TRAP_FENCE_I;
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}
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TRAP_FENCE_I:break;
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}// @suppress("No break at end of case")
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@ -1750,7 +1750,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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{
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uint32_t load_address = *(X+rs1 + 8) + uimm;
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int32_t read_res = super::template read_mem<int32_t>(traits::MEM, load_address);
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if(this->core.trap_state) goto TRAP_CLW;
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if(this->core.trap_state>=0x80000000UL) goto TRAP_CLW;
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*(X+rd + 8) = (int32_t)read_res;
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}
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TRAP_CLW:break;
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@ -1773,7 +1773,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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{
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uint32_t load_address = *(X+rs1 + 8) + uimm;
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super::template write_mem<uint32_t>(traits::MEM, load_address, (int32_t)*(X+rs2 + 8));
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if(this->core.trap_state) goto TRAP_CSW;
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if(this->core.trap_state>=0x80000000UL) goto TRAP_CSW;
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}
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TRAP_CSW:break;
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}// @suppress("No break at end of case")
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@ -2153,7 +2153,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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{
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if(rd % traits::RFS) {
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int32_t read_res = super::template read_mem<int32_t>(traits::MEM, *(X+2) + uimm);
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if(this->core.trap_state) goto TRAP_CLWSP;
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if(this->core.trap_state>=0x80000000UL) goto TRAP_CLWSP;
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int32_t res = read_res;
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*(X+rd % traits::RFS) = (int32_t)res;
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}
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@ -2293,7 +2293,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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{
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uint32_t offs = *(X+2) + uimm;
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super::template write_mem<uint32_t>(traits::MEM, offs, (uint32_t)*(X+rs2 % traits::RFS));
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if(this->core.trap_state) goto TRAP_CSWSP;
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if(this->core.trap_state>=0x80000000UL) goto TRAP_CSWSP;
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}
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TRAP_CSWSP:break;
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}// @suppress("No break at end of case")
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