From fa7eda0889490ec84a446557dad876c36baea2bf Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Wed, 31 Aug 2022 11:45:53 +0200 Subject: [PATCH] fixes wrong check for exception --- src/vm/interp/vm_tgc_c.cpp | 54 +++++++++++++++++++------------------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/src/vm/interp/vm_tgc_c.cpp b/src/vm/interp/vm_tgc_c.cpp index 291eea8..a71d8c5 100644 --- a/src/vm/interp/vm_tgc_c.cpp +++ b/src/vm/interp/vm_tgc_c.cpp @@ -629,7 +629,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co { uint32_t load_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm); int8_t read_res = super::template read_mem(traits::MEM, load_address); - if(this->core.trap_state) goto TRAP_LB; + if(this->core.trap_state>=0x80000000UL) goto TRAP_LB; int8_t res = (int8_t)read_res; if((rd % traits::RFS) != 0) { *(X+rd % traits::RFS) = (int32_t)res; @@ -655,7 +655,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co { uint32_t load_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm); int16_t read_res = super::template read_mem(traits::MEM, load_address); - if(this->core.trap_state) goto TRAP_LH; + if(this->core.trap_state>=0x80000000UL) goto TRAP_LH; int16_t res = (int16_t)read_res; if((rd % traits::RFS) != 0) { *(X+rd % traits::RFS) = (int32_t)res; @@ -681,7 +681,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co { uint32_t load_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm); int32_t read_res = super::template read_mem(traits::MEM, load_address); - if(this->core.trap_state) goto TRAP_LW; + if(this->core.trap_state>=0x80000000UL) goto TRAP_LW; int32_t res = (int32_t)read_res; if((rd % traits::RFS) != 0) { *(X+rd % traits::RFS) = (int32_t)res; @@ -707,7 +707,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co { uint32_t load_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm); uint8_t read_res = super::template read_mem(traits::MEM, load_address); - if(this->core.trap_state) goto TRAP_LBU; + if(this->core.trap_state>=0x80000000UL) goto TRAP_LBU; uint8_t res = (uint8_t)read_res; if((rd % traits::RFS) != 0) { *(X+rd % traits::RFS) = (uint32_t)res; @@ -733,7 +733,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co { uint32_t load_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm); uint16_t read_res = super::template read_mem(traits::MEM, load_address); - if(this->core.trap_state) goto TRAP_LHU; + if(this->core.trap_state>=0x80000000UL) goto TRAP_LHU; uint16_t res = (uint16_t)read_res; if((rd % traits::RFS) != 0) { *(X+rd % traits::RFS) = (uint32_t)res; @@ -759,7 +759,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co { uint32_t store_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm); super::template write_mem(traits::MEM, store_address, (int8_t)*(X+rs2 % traits::RFS)); - if(this->core.trap_state) goto TRAP_SB; + if(this->core.trap_state>=0x80000000UL) goto TRAP_SB; } TRAP_SB:break; }// @suppress("No break at end of case") @@ -781,7 +781,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co { uint32_t store_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm); super::template write_mem(traits::MEM, store_address, (int16_t)*(X+rs2 % traits::RFS)); - if(this->core.trap_state) goto TRAP_SH; + if(this->core.trap_state>=0x80000000UL) goto TRAP_SH; } TRAP_SH:break; }// @suppress("No break at end of case") @@ -803,7 +803,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co { uint32_t store_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm); super::template write_mem(traits::MEM, store_address, (int32_t)*(X+rs2 % traits::RFS)); - if(this->core.trap_state) goto TRAP_SW; + if(this->core.trap_state>=0x80000000UL) goto TRAP_SW; } TRAP_SW:break; }// @suppress("No break at end of case") @@ -1243,7 +1243,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { super::template write_mem(traits::FENCE, traits::fence, pred << 4 | succ); - if(this->core.trap_state) goto TRAP_FENCE; + if(this->core.trap_state>=0x80000000UL) goto TRAP_FENCE; } TRAP_FENCE:break; }// @suppress("No break at end of case") @@ -1318,15 +1318,15 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co uint32_t xrs1 = *(X+rs1 % traits::RFS); if((rd % traits::RFS) != 0) { uint32_t read_res = super::template read_mem(traits::CSR, csr); - if(this->core.trap_state) goto TRAP_CSRRW; + if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRW; uint32_t xrd = read_res; super::template write_mem(traits::CSR, csr, xrs1); - if(this->core.trap_state) goto TRAP_CSRRW; + if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRW; *(X+rd % traits::RFS) = xrd; } else { super::template write_mem(traits::CSR, csr, xrs1); - if(this->core.trap_state) goto TRAP_CSRRW; + if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRW; } } TRAP_CSRRW:break; @@ -1348,12 +1348,12 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { uint32_t read_res = super::template read_mem(traits::CSR, csr); - if(this->core.trap_state) goto TRAP_CSRRS; + if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRS; uint32_t xrd = read_res; uint32_t xrs1 = *(X+rs1 % traits::RFS); if(rs1 != 0) { super::template write_mem(traits::CSR, csr, xrd | xrs1); - if(this->core.trap_state) goto TRAP_CSRRS; + if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRS; } if((rd % traits::RFS) != 0) { *(X+rd % traits::RFS) = xrd; @@ -1378,12 +1378,12 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { uint32_t read_res = super::template read_mem(traits::CSR, csr); - if(this->core.trap_state) goto TRAP_CSRRC; + if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRC; uint32_t xrd = read_res; uint32_t xrs1 = *(X+rs1 % traits::RFS); if(rs1 != 0) { super::template write_mem(traits::CSR, csr, xrd & ~ xrs1); - if(this->core.trap_state) goto TRAP_CSRRC; + if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRC; } if((rd % traits::RFS) != 0) { *(X+rd % traits::RFS) = xrd; @@ -1408,10 +1408,10 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { uint32_t read_res = super::template read_mem(traits::CSR, csr); - if(this->core.trap_state) goto TRAP_CSRRWI; + if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRWI; uint32_t xrd = read_res; super::template write_mem(traits::CSR, csr, (uint32_t)zimm); - if(this->core.trap_state) goto TRAP_CSRRWI; + if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRWI; if((rd % traits::RFS) != 0) { *(X+rd % traits::RFS) = xrd; } @@ -1435,11 +1435,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { uint32_t read_res = super::template read_mem(traits::CSR, csr); - if(this->core.trap_state) goto TRAP_CSRRSI; + if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRSI; uint32_t xrd = read_res; if(zimm != 0) { super::template write_mem(traits::CSR, csr, xrd | (uint32_t)zimm); - if(this->core.trap_state) goto TRAP_CSRRSI; + if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRSI; } if((rd % traits::RFS) != 0) { *(X+rd % traits::RFS) = xrd; @@ -1464,11 +1464,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { uint32_t read_res = super::template read_mem(traits::CSR, csr); - if(this->core.trap_state) goto TRAP_CSRRCI; + if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRCI; uint32_t xrd = read_res; if(zimm != 0) { super::template write_mem(traits::CSR, csr, xrd & ~ ((uint32_t)zimm)); - if(this->core.trap_state) goto TRAP_CSRRCI; + if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRCI; } if((rd % traits::RFS) != 0) { *(X+rd % traits::RFS) = xrd; @@ -1492,7 +1492,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { super::template write_mem(traits::FENCE, traits::fencei, imm); - if(this->core.trap_state) goto TRAP_FENCE_I; + if(this->core.trap_state>=0x80000000UL) goto TRAP_FENCE_I; } TRAP_FENCE_I:break; }// @suppress("No break at end of case") @@ -1750,7 +1750,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co { uint32_t load_address = *(X+rs1 + 8) + uimm; int32_t read_res = super::template read_mem(traits::MEM, load_address); - if(this->core.trap_state) goto TRAP_CLW; + if(this->core.trap_state>=0x80000000UL) goto TRAP_CLW; *(X+rd + 8) = (int32_t)read_res; } TRAP_CLW:break; @@ -1773,7 +1773,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co { uint32_t load_address = *(X+rs1 + 8) + uimm; super::template write_mem(traits::MEM, load_address, (int32_t)*(X+rs2 + 8)); - if(this->core.trap_state) goto TRAP_CSW; + if(this->core.trap_state>=0x80000000UL) goto TRAP_CSW; } TRAP_CSW:break; }// @suppress("No break at end of case") @@ -2153,7 +2153,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co { if(rd % traits::RFS) { int32_t read_res = super::template read_mem(traits::MEM, *(X+2) + uimm); - if(this->core.trap_state) goto TRAP_CLWSP; + if(this->core.trap_state>=0x80000000UL) goto TRAP_CLWSP; int32_t res = read_res; *(X+rd % traits::RFS) = (int32_t)res; } @@ -2293,7 +2293,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co { uint32_t offs = *(X+2) + uimm; super::template write_mem(traits::MEM, offs, (uint32_t)*(X+rs2 % traits::RFS)); - if(this->core.trap_state) goto TRAP_CSWSP; + if(this->core.trap_state>=0x80000000UL) goto TRAP_CSWSP; } TRAP_CSWSP:break; }// @suppress("No break at end of case")