DBT-RISE
/
DBT-RISE-TGC
11
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

applies clang-format fixes

This commit is contained in:
Eyck Jentzsch 2023-11-30 08:49:02 +01:00
parent e6aa6e5842
commit e921201f7b
3 changed files with 8 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/iss/arch/riscv_hart_m_p.h
View File

@ -417,7 +417,7 @@ protected:
std::vector<std::function<mem_write_f>> memfn_write; std::vector<std::function<mem_write_f>> memfn_write;
void insert_mem_range(uint64_t, uint64_t, std::function<mem_read_f>, std::function<mem_write_f>); void insert_mem_range(uint64_t, uint64_t, std::function<mem_read_f>, std::function<mem_write_f>);
feature_config cfg; feature_config cfg;
unsigned mcause_max_irq{(FEAT & features_e::FEAT_CLIC) ? std::max(16U,static_cast<unsigned>(traits<BASE>::CLIC_NUM_IRQ)) : 16U}; unsigned mcause_max_irq{(FEAT & features_e::FEAT_CLIC) ? std::max(16U, static_cast<unsigned>(traits<BASE>::CLIC_NUM_IRQ)) : 16U};
inline bool debug_mode_active() { return this->reg.PRIV & 0x4; } inline bool debug_mode_active() { return this->reg.PRIV & 0x4; }
std::pair<std::function<mem_read_f>, std::function<mem_write_f>> replace_mem_access(std::function<mem_read_f> rd, std::pair<std::function<mem_read_f>, std::function<mem_write_f>> replace_mem_access(std::function<mem_read_f> rd,
std::function<mem_write_f> wr) { std::function<mem_write_f> wr) {
@ -824,8 +824,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
x |= 0x80; // set pll lock upon writing x |= 0x80; // set pll lock upon writing
return iss::Ok; return iss::Ok;
} break; } break;
default: { default: {}
}
} }
} break; } break;
case traits<BASE>::CSR: { case traits<BASE>::CSR: {

9
src/iss/arch/riscv_hart_msu_vp.h
View File

@ -804,8 +804,7 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
x |= 0x80; // set pll lock upon writing x |= 0x80; // set pll lock upon writing
return iss::Ok; return iss::Ok;
} break; } break;
default: { default: {}
}
} }
} break; } break;
case traits<BASE>::CSR: { case traits<BASE>::CSR: {
@ -1228,9 +1227,9 @@ template <typename BASE> typename riscv_hart_msu_vp<BASE>::phys_addr_t riscv_har
break; break;
} else if(!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) { } else if(!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) {
break; break;
} else if(type == iss::access_type::FETCH ? !(pte & PTE_X) } else if(type == (iss::access_type::FETCH ? !(pte & PTE_X)
: type == iss::access_type::READ ? !(pte & PTE_R) && !(mxr && (pte & PTE_X)) : type == iss::access_type::READ ? !(pte & PTE_R) && !(mxr && (pte & PTE_X))
: !((pte & PTE_R) && (pte & PTE_W))) { : !((pte & PTE_R) && (pte & PTE_W)))) {
break; break;
} else if((ppn & ((reg_t(1) << ptshift) - 1)) != 0) { } else if((ppn & ((reg_t(1) << ptshift) - 1)) != 0) {
break; break;

5
src/iss/arch/riscv_hart_mu_p.h
View File

@ -447,7 +447,7 @@ protected:
std::vector<std::function<mem_write_f>> memfn_write; std::vector<std::function<mem_write_f>> memfn_write;
void insert_mem_range(uint64_t, uint64_t, std::function<mem_read_f>, std::function<mem_write_f>); void insert_mem_range(uint64_t, uint64_t, std::function<mem_read_f>, std::function<mem_write_f>);
feature_config cfg; feature_config cfg;
unsigned mcause_max_irq{(FEAT & features_e::FEAT_CLIC) ? std::max(16U,static_cast<unsigned>(traits<BASE>::CLIC_NUM_IRQ)) : 16U}; unsigned mcause_max_irq{(FEAT & features_e::FEAT_CLIC) ? std::max(16U, static_cast<unsigned>(traits<BASE>::CLIC_NUM_IRQ)) : 16U};
inline bool debug_mode_active() { return this->reg.PRIV & 0x4; } inline bool debug_mode_active() { return this->reg.PRIV & 0x4; }
std::pair<std::function<mem_read_f>, std::function<mem_write_f>> replace_mem_access(std::function<mem_read_f> rd, std::pair<std::function<mem_read_f>, std::function<mem_write_f>> replace_mem_access(std::function<mem_read_f> rd,
@ -1007,8 +1007,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
x |= 0x80; // set pll lock upon writing x |= 0x80; // set pll lock upon writing
return iss::Ok; return iss::Ok;
} break; } break;
default: { default: {}
}
} }
} break; } break;
case traits<BASE>::CSR: { case traits<BASE>::CSR: {