adaptes to changes in dbt-rise-core
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parent
8407f6287f
commit
e60fa3d5e6
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@ -85,7 +85,7 @@ public:
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corresponding bytes in avail_buf are 0, otherwise
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avail buf is 1 */
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status read_single_register(unsigned int reg_no, std::vector<uint8_t> &buf,
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std::vector<uint8_t> &avail_buf) override;
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std::vector<uint8_t> &avail_buf) override;
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/* Write one register. buf is 4-byte aligned and it is in target byte
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order */
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@ -104,7 +104,7 @@ public:
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status process_query(unsigned int &mask, const rp_thread_ref &arg, rp_thread_info &info) override;
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status thread_list_query(int first, const rp_thread_ref &arg, std::vector<rp_thread_ref> &result, size_t max_num,
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size_t &num, bool &done) override;
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size_t &num, bool &done) override;
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status current_thread_query(rp_thread_ref &thread) override;
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@ -120,12 +120,12 @@ public:
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status packetsize_query(std::string &out_buf) override;
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status add_break(int type, uint64_t addr, unsigned int length) override;
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status add_break(break_type type, uint64_t addr, unsigned int length) override;
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status remove_break(int type, uint64_t addr, unsigned int length) override;
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status remove_break(break_type type, uint64_t addr, unsigned int length) override;
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status resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
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std::function<void(unsigned)> stop_callback) override;
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std::function<void(unsigned)> stop_callback) override;
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status target_xml_query(std::string &out_buf) override;
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@ -159,8 +159,8 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::is_thread_alive(rp_t
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*/
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template <typename ARCH>
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status riscv_target_adapter<ARCH>::thread_list_query(int first, const rp_thread_ref &arg,
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std::vector<rp_thread_ref> &result, size_t max_num, size_t &num,
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bool &done) {
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std::vector<rp_thread_ref> &result, size_t max_num, size_t &num,
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bool &done) {
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if (first == 0) {
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result.clear();
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result.push_back(thread_idx);
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@ -193,20 +193,20 @@ status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t> &data, st
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}
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}
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// work around fill with F type registers
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// if (arch::traits<ARCH>::NUM_REGS < 65) {
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// auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
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// for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
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// for (size_t j = 0; j < reg_width; ++j) {
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// data.push_back(0x0);
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// avail.push_back(0x00);
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// }
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// // if(arch::traits<ARCH>::XLEN < 64)
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// // for(unsigned j=0; j<4; ++j){
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// // data.push_back(0x0);
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// // avail.push_back(0x00);
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// // }
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// }
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// }
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// if (arch::traits<ARCH>::NUM_REGS < 65) {
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// auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
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// for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
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// for (size_t j = 0; j < reg_width; ++j) {
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// data.push_back(0x0);
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// avail.push_back(0x00);
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// }
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// // if(arch::traits<ARCH>::XLEN < 64)
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// // for(unsigned j=0; j<4; ++j){
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// // data.push_back(0x0);
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// // avail.push_back(0x00);
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// // }
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// }
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// }
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return Ok;
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}
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@ -240,7 +240,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(cons
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template <typename ARCH>
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status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t> &data,
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std::vector<uint8_t> &avail) {
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std::vector<uint8_t> &avail) {
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if (reg_no < 65) {
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// auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename
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// arch::traits<ARCH>::reg_e>(reg_no))/8;
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@ -331,34 +331,46 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::packetsize_query(std
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return Ok;
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(int type, uint64_t addr, unsigned int length) {
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auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
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auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
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target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
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LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex
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<< saddr.val << std::dec;
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LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
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return Ok;
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(int type, uint64_t addr, unsigned int length) {
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auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
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unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
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if (handle) {
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LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val
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<< std::dec;
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// TODO: check length of addr range
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target_adapter_base::bp_lut.removeEntry(handle);
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template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(break_type type, uint64_t addr, unsigned int length) {
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switch(type) {
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default:
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return Err;
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case HW_EXEC: {
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auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
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auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
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target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
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LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex
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<< saddr.val << std::dec;
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LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
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return Ok;
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}
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LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
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return Err;
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}
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(break_type type, uint64_t addr, unsigned int length) {
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switch(type) {
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default:
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return Err;
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case HW_EXEC: {
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auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
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unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
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if (handle) {
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LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val
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<< std::dec;
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// TODO: check length of addr range
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target_adapter_base::bp_lut.removeEntry(handle);
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LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
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return Ok;
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}
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LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
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return Err;
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}
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}
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}
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template <typename ARCH>
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status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
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std::function<void(unsigned)> stop_callback) {
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std::function<void(unsigned)> stop_callback) {
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auto *reg_base = core->get_regs_base_ptr();
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auto reg_width = arch::traits<ARCH>::reg_bit_widths[arch::traits<ARCH>::PC] / 8;
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auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
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@ -369,42 +381,42 @@ status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t
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template <typename ARCH> status riscv_target_adapter<ARCH>::target_xml_query(std::string &out_buf) {
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const std::string res{"<?xml version=\"1.0\"?><!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
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"<target><architecture>riscv:rv32</architecture>"
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//" <feature name=\"org.gnu.gdb.riscv.rv32i\">\n"
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//" <reg name=\"x0\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x1\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x2\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x3\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x4\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x5\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x6\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x7\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x8\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x9\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x10\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x11\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x12\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x13\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x14\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x15\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x16\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x17\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x18\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x19\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x20\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x21\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x22\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x23\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x24\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x25\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x26\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x27\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x28\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x29\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x30\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x31\" bitsize=\"32\" group=\"general\"/>\n"
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//" </feature>\n"
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"</target>"};
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"<target><architecture>riscv:rv32</architecture>"
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//" <feature name=\"org.gnu.gdb.riscv.rv32i\">\n"
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//" <reg name=\"x0\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x1\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x2\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x3\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x4\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x5\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x6\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x7\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x8\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x9\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x10\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x11\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x12\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x13\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x14\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x15\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x16\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x17\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x18\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x19\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x20\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x21\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x22\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x23\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x24\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x25\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x26\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x27\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x28\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x29\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x30\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x31\" bitsize=\"32\" group=\"general\"/>\n"
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//" </feature>\n"
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"</target>"};
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out_buf = res;
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return Ok;
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}
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