From e60fa3d5e6b873742ab9e7a0130ccdb4df25f34b Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Sat, 6 Aug 2022 09:49:32 +0200 Subject: [PATCH] adaptes to changes in dbt-rise-core --- src/iss/debugger/riscv_target_adapter.h | 170 +++++++++++++----------- 1 file changed, 91 insertions(+), 79 deletions(-) diff --git a/src/iss/debugger/riscv_target_adapter.h b/src/iss/debugger/riscv_target_adapter.h index b7c3036..0c008d9 100644 --- a/src/iss/debugger/riscv_target_adapter.h +++ b/src/iss/debugger/riscv_target_adapter.h @@ -85,7 +85,7 @@ public: corresponding bytes in avail_buf are 0, otherwise avail buf is 1 */ status read_single_register(unsigned int reg_no, std::vector &buf, - std::vector &avail_buf) override; + std::vector &avail_buf) override; /* Write one register. buf is 4-byte aligned and it is in target byte order */ @@ -104,7 +104,7 @@ public: status process_query(unsigned int &mask, const rp_thread_ref &arg, rp_thread_info &info) override; status thread_list_query(int first, const rp_thread_ref &arg, std::vector &result, size_t max_num, - size_t &num, bool &done) override; + size_t &num, bool &done) override; status current_thread_query(rp_thread_ref &thread) override; @@ -120,12 +120,12 @@ public: status packetsize_query(std::string &out_buf) override; - status add_break(int type, uint64_t addr, unsigned int length) override; + status add_break(break_type type, uint64_t addr, unsigned int length) override; - status remove_break(int type, uint64_t addr, unsigned int length) override; + status remove_break(break_type type, uint64_t addr, unsigned int length) override; status resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread, - std::function stop_callback) override; + std::function stop_callback) override; status target_xml_query(std::string &out_buf) override; @@ -159,8 +159,8 @@ template status riscv_target_adapter::is_thread_alive(rp_t */ template status riscv_target_adapter::thread_list_query(int first, const rp_thread_ref &arg, - std::vector &result, size_t max_num, size_t &num, - bool &done) { + std::vector &result, size_t max_num, size_t &num, + bool &done) { if (first == 0) { result.clear(); result.push_back(thread_idx); @@ -193,20 +193,20 @@ status riscv_target_adapter::read_registers(std::vector &data, st } } // work around fill with F type registers -// if (arch::traits::NUM_REGS < 65) { -// auto reg_width = sizeof(typename arch::traits::reg_t); -// for (size_t reg_no = 0; reg_no < 33; ++reg_no) { -// for (size_t j = 0; j < reg_width; ++j) { -// data.push_back(0x0); -// avail.push_back(0x00); -// } -// // if(arch::traits::XLEN < 64) -// // for(unsigned j=0; j<4; ++j){ -// // data.push_back(0x0); -// // avail.push_back(0x00); -// // } -// } -// } + // if (arch::traits::NUM_REGS < 65) { + // auto reg_width = sizeof(typename arch::traits::reg_t); + // for (size_t reg_no = 0; reg_no < 33; ++reg_no) { + // for (size_t j = 0; j < reg_width; ++j) { + // data.push_back(0x0); + // avail.push_back(0x00); + // } + // // if(arch::traits::XLEN < 64) + // // for(unsigned j=0; j<4; ++j){ + // // data.push_back(0x0); + // // avail.push_back(0x00); + // // } + // } + // } return Ok; } @@ -240,7 +240,7 @@ template status riscv_target_adapter::write_registers(cons template status riscv_target_adapter::read_single_register(unsigned int reg_no, std::vector &data, - std::vector &avail) { + std::vector &avail) { if (reg_no < 65) { // auto reg_size = arch::traits::reg_bit_width(static_cast::reg_e>(reg_no))/8; @@ -331,34 +331,46 @@ template status riscv_target_adapter::packetsize_query(std return Ok; } -template status riscv_target_adapter::add_break(int type, uint64_t addr, unsigned int length) { - auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr}); - auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length}); - target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val); - LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex - << saddr.val << std::dec; - LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints"; - return Ok; -} - -template status riscv_target_adapter::remove_break(int type, uint64_t addr, unsigned int length) { - auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr}); - unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val); - if (handle) { - LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val - << std::dec; - // TODO: check length of addr range - target_adapter_base::bp_lut.removeEntry(handle); +template status riscv_target_adapter::add_break(break_type type, uint64_t addr, unsigned int length) { + switch(type) { + default: + return Err; + case HW_EXEC: { + auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr}); + auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length}); + target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val); + LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex + << saddr.val << std::dec; LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints"; return Ok; } - LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints"; - return Err; + } +} + +template status riscv_target_adapter::remove_break(break_type type, uint64_t addr, unsigned int length) { + switch(type) { + default: + return Err; + case HW_EXEC: { + auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr}); + unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val); + if (handle) { + LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val + << std::dec; + // TODO: check length of addr range + target_adapter_base::bp_lut.removeEntry(handle); + LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints"; + return Ok; + } + LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints"; + return Err; + } + } } template status riscv_target_adapter::resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread, - std::function stop_callback) { + std::function stop_callback) { auto *reg_base = core->get_regs_base_ptr(); auto reg_width = arch::traits::reg_bit_widths[arch::traits::PC] / 8; auto offset = traits::reg_byte_offsets[arch::traits::PC]; @@ -369,42 +381,42 @@ status riscv_target_adapter::resume_from_addr(bool step, int sig, uint64_t template status riscv_target_adapter::target_xml_query(std::string &out_buf) { const std::string res{"" - "riscv:rv32" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - ""}; + "riscv:rv32" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + ""}; out_buf = res; return Ok; }