DBT-RISE/DBT-RISE-TGC
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updates debugger hook to stop before fetching instructions

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this relates to https://github.com/Minres/DBT-RISE-RISCV/issues/8 :
Debugger loses control when trap vector fetch fails

and https://github.com/Minres/DBT-RISE-RISCV/issues/7 : Two debugger
single-steps are required at reset vector
This commit is contained in:
Eyck Jentzsch
2024-08-17 12:37:57 +02:00
parent 0473aa5344
commit de79adc50d
3 changed files with 32 additions and 18 deletions
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18
src/iss/arch/riscv_hart_m_p.h
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@ -689,8 +689,10 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read(const address_type type, co
}
return res;
} catch(trap_access& ta) {
this->reg.trap_state = (1UL << 31) | ta.id;
fault_data = ta.addr;
if( (access & access_type::DEBUG) == 0) {
this->reg.trap_state = (1UL << 31) | ta.id;
fault_data = ta.addr;
}
return iss::Err;
}
} break;
@ -717,8 +719,10 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read(const address_type type, co
}
return iss::Ok;
} catch(trap_access& ta) {
this->reg.trap_state = (1UL << 31) | ta.id;
fault_data = ta.addr;
if((access & access_type::DEBUG) == 0) {
this->reg.trap_state = (1UL << 31) | ta.id;
fault_data = ta.addr;
}
return iss::Err;
}
}
@ -848,8 +852,10 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write(const address_type type, c
}
return iss::Ok;
} catch(trap_access& ta) {
this->reg.trap_state = (1UL << 31) | ta.id;
fault_data = ta.addr;
if((access & access_type::DEBUG) == 0) {
this->reg.trap_state = (1UL << 31) | ta.id;
fault_data = ta.addr;
}
return iss::Err;
}
}