DBT-RISE
/
DBT-RISE-TGC
11
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

add clic CSRs

This commit is contained in:
Eyck Jentzsch 2021-07-27 10:47:48 +02:00
parent d0f3a120fd
commit d7bddd825c
2 changed files with 24 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
incl/iss/arch/riscv_hart_common.h
View File

@ -104,12 +104,19 @@ enum riscv_csr {
mie = 0x304, mie = 0x304,
mtvec = 0x305, mtvec = 0x305,
mcounteren = 0x306, mcounteren = 0x306,
mtvt = 0x307, //CLIC
// Machine Trap Handling // Machine Trap Handling
mscratch = 0x340, mscratch = 0x340,
mepc = 0x341, mepc = 0x341,
mcause = 0x342, mcause = 0x342,
mtval = 0x343, mtval = 0x343,
mip = 0x344, mip = 0x344,
mxnti = 0x345, //CLIC
mintstatus = 0x346, // MRW Current interrupt levels (CLIC) - addr subject to change
mscratchcsw = 0x348, // MRW Conditional scratch swap on priv mode change (CLIC)
mscratchcswl = 0x349, // MRW Conditional scratch swap on level change (CLIC)
mintthresh = 0x350, // MRW Interrupt-level threshold (CLIC) - addr subject to change
mclicbase = 0x351, // MRW Base address for CLIC memory mapped registers (CLIC) - addr subject to change
// Physical Memory Protection // Physical Memory Protection
pmpcfg0 = 0x3A0, pmpcfg0 = 0x3A0,
pmpcfg1 = 0x3A1, pmpcfg1 = 0x3A1,

18
incl/iss/arch/riscv_hart_mu_p.h
View File

@ -66,7 +66,7 @@
namespace iss { namespace iss {
namespace arch { namespace arch {
enum features_e{FEAT_NONE, FEAT_PMP, FEAT_EXT_N}; enum features_e{FEAT_NONE, FEAT_PMP, FEAT_EXT_N, FEAT_CLIC};
template <typename BASE, features_e FEAT=FEAT_NONE> class riscv_hart_mu_p : public BASE { template <typename BASE, features_e FEAT=FEAT_NONE> class riscv_hart_mu_p : public BASE {
protected: protected:
@ -406,6 +406,22 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p()
csr_rd_cb[medeleg] = &this_class::read_reg; csr_rd_cb[medeleg] = &this_class::read_reg;
csr_wr_cb[medeleg] = &this_class::write_reg; csr_wr_cb[medeleg] = &this_class::write_reg;
} }
if(FEAT & FEAT_CLIC) {
csr_rd_cb[mtvt] = &this_class::read_reg;
csr_wr_cb[mtvt] = &this_class::write_reg;
csr_rd_cb[mxnti] = &this_class::read_reg;
csr_wr_cb[mxnti] = &this_class::write_reg;
csr_rd_cb[mintstatus] = &this_class::read_reg;
csr_wr_cb[mintstatus] = &this_class::write_reg;
csr_rd_cb[mscratchcsw] = &this_class::read_reg;
csr_wr_cb[mscratchcsw] = &this_class::write_reg;
csr_rd_cb[mscratchcswl] = &this_class::read_reg;
csr_wr_cb[mscratchcswl] = &this_class::write_reg;
csr_rd_cb[mintthresh] = &this_class::read_reg;
csr_wr_cb[mintthresh] = &this_class::write_reg;
csr_rd_cb[mclicbase] = &this_class::read_reg;
csr_wr_cb[mclicbase] = &this_class::write_reg;
}
} }
template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_mu_p<BASE, FEAT>::load_file(std::string name, int type) { template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_mu_p<BASE, FEAT>::load_file(std::string name, int type) {