changes time handling at sockets
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@ -107,7 +107,8 @@ public:
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heart_state_t &get_state() { return this->state; }
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void notify_phase(iss::arch_if::exec_phase p) override {
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if (p == iss::arch_if::ISTART) owner->sync(this->icount);
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if (p == iss::arch_if::ISTART)
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owner->sync(this->instr_if.get_total_cycles());
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}
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sync_type needed_sync() const override { return PRE_SYNC; }
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@ -547,8 +548,12 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data,
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gp.set_extension(preExt);
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}
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sckt->b_transport(gp, delay);
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quantum_keeper.set(delay);
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SCCTRACE(this->name()) << "read_mem(0x" << std::hex << addr << ") : 0x" << (length==4?*(uint32_t*)data:length==2?*(uint16_t*)data:(unsigned)*data);
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auto incr = delay-quantum_keeper.get_local_time();
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if(is_fetch)
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ibus_inc+=incr;
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else
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dbus_inc+=incr;
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SCCTRACE(this->name()) << "[local time: "<<delay<<"]: finish read_mem(0x" << std::hex << addr << ") : 0x" << (length==4?*(uint32_t*)data:length==2?*(uint16_t*)data:(unsigned)*data);
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if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
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return false;
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}
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@ -589,8 +594,8 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
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gp.set_extension(preExt);
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}
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dbus->b_transport(gp, delay);
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quantum_keeper.set(delay);
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SCCTRACE() << "write_mem(0x" << std::hex << addr << ") : 0x" << (length==4?*(uint32_t*)data:length==2?*(uint16_t*)data:(unsigned)*data);
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dbus_inc+=delay-quantum_keeper.get_local_time();
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SCCTRACE() << "[local time: "<<delay<<"]: finish write_mem(0x" << std::hex << addr << ") : 0x" << (length==4?*(uint32_t*)data:length==2?*(uint16_t*)data:(unsigned)*data);
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if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
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return false;
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}
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