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DBT-RISE-TGC
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fix proper debug mode handling (#267 & #268)

This commit is contained in:
Eyck Jentzsch 2021-11-07 17:48:44 +01:00
parent 49d09a05d7
commit c42e336509
7 changed files with 386 additions and 301 deletions
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2
gen_input/CoreDSL-Instruction-Set-Description

@ -1 +1 @@
Subproject commit e7aaec6ad9336bd83b4da63dd0c96f8d11887661 Subproject commit b005607fc30c4467683b6044eaca7eb378061b53

10
gen_input/templates/interp/CORENAME.cpp.gtl
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@ -29,7 +29,13 @@
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
* *
*******************************************************************************/ *******************************************************************************/
<%
import com.minres.coredsl.util.BigIntegerWithRadix
def nativeTypeSize(int size){
if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
}
%>
#include "../fp_functions.h" #include "../fp_functions.h"
#include <iss/arch/${coreDef.name.toLowerCase()}.h> #include <iss/arch/${coreDef.name.toLowerCase()}.h>
#include <iss/arch/riscv_hart_m_p.h> #include <iss/arch/riscv_hart_m_p.h>
@ -204,8 +210,8 @@ private:
} }
// used registers<%instr.usedVariables.each{ k,v-> // used registers<%instr.usedVariables.each{ k,v->
if(v.isArray) {%> if(v.isArray) {%>
auto* ${k} = reinterpret_cast<uint${v.type.size}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %> auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %>
auto* ${k} = reinterpret_cast<uint${v.type.size}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]); auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
<%}}%>// calculate next pc value <%}}%>// calculate next pc value
*NEXT_PC = *PC + ${instr.length/8}; *NEXT_PC = *PC + ${instr.length/8};
// execute instruction // execute instruction

28
incl/iss/arch/riscv_hart_m_p.h
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@ -311,6 +311,8 @@ protected:
iss::status write_dcsr_dcsr(unsigned addr, reg_t val); iss::status write_dcsr_dcsr(unsigned addr, reg_t val);
iss::status read_dcsr_reg(unsigned addr, reg_t &val); iss::status read_dcsr_reg(unsigned addr, reg_t &val);
iss::status write_dcsr_reg(unsigned addr, reg_t val); iss::status write_dcsr_reg(unsigned addr, reg_t val);
iss::status read_dpc_reg(unsigned addr, reg_t &val);
iss::status write_dpc_reg(unsigned addr, reg_t val);
reg_t mhartid_reg{0x0}; reg_t mhartid_reg{0x0};
std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb; std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
@ -322,7 +324,7 @@ protected:
unsigned clic_num_irq{0}; unsigned clic_num_irq{0};
unsigned clic_num_trigger{0}; unsigned clic_num_trigger{0};
unsigned mcause_max_irq{16}; unsigned mcause_max_irq{16};
bool debug_mode_active{false}; inline bool debug_mode_active() {return this->reg.PRIV&0x4;}
}; };
template <typename BASE, features_e FEAT> template <typename BASE, features_e FEAT>
@ -397,8 +399,8 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p()
csr_rd_cb[dscratch0] = &this_class::read_dcsr_reg; csr_rd_cb[dscratch0] = &this_class::read_dcsr_reg;
csr_wr_cb[dscratch1] = &this_class::write_dcsr_reg; csr_wr_cb[dscratch1] = &this_class::write_dcsr_reg;
csr_rd_cb[dscratch1] = &this_class::read_dcsr_reg; csr_rd_cb[dscratch1] = &this_class::read_dcsr_reg;
csr_wr_cb[dpc] = &this_class::write_dcsr_reg; csr_wr_cb[dpc] = &this_class::write_dpc_reg;
csr_rd_cb[dpc] = &this_class::read_dcsr_reg; csr_rd_cb[dpc] = &this_class::read_dpc_reg;
csr_wr_cb[dcsr] = &this_class::write_dcsr_dcsr; csr_wr_cb[dcsr] = &this_class::write_dcsr_dcsr;
csr_rd_cb[dcsr] = &this_class::read_dcsr_reg; csr_rd_cb[dcsr] = &this_class::read_dcsr_reg;
} }
@ -815,7 +817,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
} }
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_dcsr_dcsr(unsigned addr, reg_t val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_dcsr_dcsr(unsigned addr, reg_t val) {
if(!debug_mode_active) if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data); throw illegal_instruction_fault(this->fault_data);
// +-------------- ebreakm // +-------------- ebreakm
// | +---------- stepi // | +---------- stepi
@ -826,19 +828,33 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
} }
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_dcsr_reg(unsigned addr, reg_t &val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_dcsr_reg(unsigned addr, reg_t &val) {
if(!debug_mode_active) if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data); throw illegal_instruction_fault(this->fault_data);
val = csr[addr]; val = csr[addr];
return iss::Ok; return iss::Ok;
} }
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_dcsr_reg(unsigned addr, reg_t val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_dcsr_reg(unsigned addr, reg_t val) {
if(!debug_mode_active) if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data); throw illegal_instruction_fault(this->fault_data);
csr[addr] = val; csr[addr] = val;
return iss::Ok; return iss::Ok;
} }
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_dpc_reg(unsigned addr, reg_t &val) {
if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data);
val = this->reg.DPC;
return iss::Ok;
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_dpc_reg(unsigned addr, reg_t val) {
if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data);
this->reg.DPC = val;
return iss::Ok;
}
template <typename BASE, features_e FEAT> template <typename BASE, features_e FEAT>
iss::status riscv_hart_m_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) { iss::status riscv_hart_m_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
if(mem_read_cb) return mem_read_cb(paddr, length, data); if(mem_read_cb) return mem_read_cb(paddr, length, data);

27
incl/iss/arch/riscv_hart_mu_p.h
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@ -328,6 +328,8 @@ protected:
iss::status write_dcsr_dcsr(unsigned addr, reg_t val); iss::status write_dcsr_dcsr(unsigned addr, reg_t val);
iss::status read_dcsr_reg(unsigned addr, reg_t &val); iss::status read_dcsr_reg(unsigned addr, reg_t &val);
iss::status write_dcsr_reg(unsigned addr, reg_t val); iss::status write_dcsr_reg(unsigned addr, reg_t val);
iss::status read_dpc_reg(unsigned addr, reg_t &val);
iss::status write_dpc_reg(unsigned addr, reg_t val);
reg_t mhartid_reg{0x0}; reg_t mhartid_reg{0x0};
std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb; std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
@ -339,7 +341,7 @@ protected:
unsigned clic_num_irq{0}; unsigned clic_num_irq{0};
unsigned clic_num_trigger{0}; unsigned clic_num_trigger{0};
unsigned mcause_max_irq{16}; unsigned mcause_max_irq{16};
bool debug_mode_active{false}; inline bool debug_mode_active() {return this->reg.PRIV&0x4;}
}; };
template <typename BASE, features_e FEAT> template <typename BASE, features_e FEAT>
@ -469,8 +471,8 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p()
csr_rd_cb[dscratch0] = &this_class::read_dcsr_reg; csr_rd_cb[dscratch0] = &this_class::read_dcsr_reg;
csr_wr_cb[dscratch1] = &this_class::write_dcsr_reg; csr_wr_cb[dscratch1] = &this_class::write_dcsr_reg;
csr_rd_cb[dscratch1] = &this_class::read_dcsr_reg; csr_rd_cb[dscratch1] = &this_class::read_dcsr_reg;
csr_wr_cb[dpc] = &this_class::write_dcsr_reg; csr_wr_cb[dpc] = &this_class::write_dpc_reg;
csr_rd_cb[dpc] = &this_class::read_dcsr_reg; csr_rd_cb[dpc] = &this_class::read_dpc_reg;
csr_wr_cb[dcsr] = &this_class::write_dcsr_dcsr; csr_wr_cb[dcsr] = &this_class::write_dcsr_dcsr;
csr_rd_cb[dcsr] = &this_class::read_dcsr_reg; csr_rd_cb[dcsr] = &this_class::read_dcsr_reg;
} }
@ -979,7 +981,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
} }
template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_dcsr_dcsr(unsigned addr, reg_t val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_dcsr_dcsr(unsigned addr, reg_t val) {
if(!debug_mode_active) if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data); throw illegal_instruction_fault(this->fault_data);
// +-------------- ebreakm // +-------------- ebreakm
// | +---------- stepi // | +---------- stepi
@ -990,19 +992,32 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
} }
template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_dcsr_reg(unsigned addr, reg_t &val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_dcsr_reg(unsigned addr, reg_t &val) {
if(!debug_mode_active) if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data); throw illegal_instruction_fault(this->fault_data);
val = csr[addr]; val = csr[addr];
return iss::Ok; return iss::Ok;
} }
template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_dcsr_reg(unsigned addr, reg_t val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_dcsr_reg(unsigned addr, reg_t val) {
if(!debug_mode_active) if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data); throw illegal_instruction_fault(this->fault_data);
csr[addr] = val; csr[addr] = val;
return iss::Ok; return iss::Ok;
} }
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_dpc_reg(unsigned addr, reg_t &val) {
if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data);
val = this->reg.DPC;
return iss::Ok;
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_dpc_reg(unsigned addr, reg_t val) {
if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data);
this->reg.DPC = val;
return iss::Ok;
}
template<typename BASE, features_e FEAT> template<typename BASE, features_e FEAT>
iss::status riscv_hart_mu_p<BASE, FEAT>::write_intthresh(unsigned addr, reg_t val) { iss::status riscv_hart_mu_p<BASE, FEAT>::write_intthresh(unsigned addr, reg_t val) {

110
incl/iss/arch/tgc_c.h
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@ -47,18 +47,18 @@ template <> struct traits<tgc_c> {
constexpr static char const* const core_type = "TGC_C"; constexpr static char const* const core_type = "TGC_C";
static constexpr std::array<const char*, 35> reg_names{ static constexpr std::array<const char*, 36> reg_names{
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}}; {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV", "DPC"}};
static constexpr std::array<const char*, 35> reg_aliases{ static constexpr std::array<const char*, 36> reg_aliases{
{"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV"}}; {"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV", "DPC"}};
enum constants {MISA_VAL=0b01000000000000000001000100000100, MARCHID_VAL=0x80000003, XLEN=32, CSR_SIZE=4096, INSTR_ALIGNMENT=2, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64}; enum constants {MISA_VAL=0b01000000000000000001000100000100, MARCHID_VAL=0x80000003, XLEN=32, CSR_SIZE=4096, INSTR_ALIGNMENT=2, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
constexpr static unsigned FP_REGS_SIZE = 0; constexpr static unsigned FP_REGS_SIZE = 0;
enum reg_e { enum reg_e {
X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, NUM_REGS, X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, DPC, NUM_REGS,
TRAP_STATE=NUM_REGS, TRAP_STATE=NUM_REGS,
PENDING_TRAP, PENDING_TRAP,
ICOUNT, ICOUNT,
@ -76,11 +76,11 @@ template <> struct traits<tgc_c> {
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>; using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
static constexpr std::array<const uint32_t, 40> reg_bit_widths{ static constexpr std::array<const uint32_t, 41> reg_bit_widths{
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,64,64,64}}; {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,32,64,64,64}};
static constexpr std::array<const uint32_t, 40> reg_byte_offsets{ static constexpr std::array<const uint32_t, 41> reg_byte_offsets{
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,153,161}}; {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,149,157,165}};
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1); static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
@ -133,51 +133,52 @@ template <> struct traits<tgc_c> {
SRET = 41, SRET = 41,
MRET = 42, MRET = 42,
WFI = 43, WFI = 43,
CSRRW = 44, DRET = 44,
CSRRS = 45, CSRRW = 45,
CSRRC = 46, CSRRS = 46,
CSRRWI = 47, CSRRC = 47,
CSRRSI = 48, CSRRWI = 48,
CSRRCI = 49, CSRRSI = 49,
FENCE_I = 50, CSRRCI = 50,
MUL = 51, FENCE_I = 51,
MULH = 52, MUL = 52,
MULHSU = 53, MULH = 53,
MULHU = 54, MULHSU = 54,
DIV = 55, MULHU = 55,
DIVU = 56, DIV = 56,
REM = 57, DIVU = 57,
REMU = 58, REM = 58,
CADDI4SPN = 59, REMU = 59,
CLW = 60, CADDI4SPN = 60,
CSW = 61, CLW = 61,
CADDI = 62, CSW = 62,
CNOP = 63, CADDI = 63,
CJAL = 64, CNOP = 64,
CLI = 65, CJAL = 65,
CLUI = 66, CLI = 66,
CADDI16SP = 67, CLUI = 67,
__reserved_clui = 68, CADDI16SP = 68,
CSRLI = 69, __reserved_clui = 69,
CSRAI = 70, CSRLI = 70,
CANDI = 71, CSRAI = 71,
CSUB = 72, CANDI = 72,
CXOR = 73, CSUB = 73,
COR = 74, CXOR = 74,
CAND = 75, COR = 75,
CJ = 76, CAND = 76,
CBEQZ = 77, CJ = 77,
CBNEZ = 78, CBEQZ = 78,
CSLLI = 79, CBNEZ = 79,
CLWSP = 80, CSLLI = 80,
CMV = 81, CLWSP = 81,
CJR = 82, CMV = 82,
__reserved_cmv = 83, CJR = 83,
CADD = 84, __reserved_cmv = 84,
CJALR = 85, CADD = 85,
CEBREAK = 86, CJALR = 86,
CSWSP = 87, CEBREAK = 87,
DII = 88, CSWSP = 88,
DII = 89,
MAX_OPCODE MAX_OPCODE
}; };
}; };
@ -254,6 +255,7 @@ protected:
uint32_t PC = 0; uint32_t PC = 0;
uint32_t NEXT_PC = 0; uint32_t NEXT_PC = 0;
uint8_t PRIV = 0; uint8_t PRIV = 0;
uint32_t DPC = 0;
uint32_t trap_state = 0, pending_trap = 0; uint32_t trap_state = 0, pending_trap = 0;
uint64_t icount = 0; uint64_t icount = 0;
uint64_t cycle = 0; uint64_t cycle = 0;

8
src/iss/tgc_c.cpp
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@ -39,10 +39,10 @@
using namespace iss::arch; using namespace iss::arch;
constexpr std::array<const char*, 35> iss::arch::traits<iss::arch::tgc_c>::reg_names; constexpr std::array<const char*, 36> iss::arch::traits<iss::arch::tgc_c>::reg_names;
constexpr std::array<const char*, 35> iss::arch::traits<iss::arch::tgc_c>::reg_aliases; constexpr std::array<const char*, 36> iss::arch::traits<iss::arch::tgc_c>::reg_aliases;
constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths; constexpr std::array<const uint32_t, 41> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths;
constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets; constexpr std::array<const uint32_t, 41> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets;
tgc_c::tgc_c() { tgc_c::tgc_c() {
reg.icount = 0; reg.icount = 0;

500
src/vm/interp/vm_tgc_c.cpp
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