diff --git a/gen_input/CoreDSL-Instruction-Set-Description b/gen_input/CoreDSL-Instruction-Set-Description
index e7aaec6..b005607 160000
--- a/gen_input/CoreDSL-Instruction-Set-Description
+++ b/gen_input/CoreDSL-Instruction-Set-Description
@@ -1 +1 @@
-Subproject commit e7aaec6ad9336bd83b4da63dd0c96f8d11887661
+Subproject commit b005607fc30c4467683b6044eaca7eb378061b53
diff --git a/gen_input/templates/interp/CORENAME.cpp.gtl b/gen_input/templates/interp/CORENAME.cpp.gtl
index 53cffed..7cf5c47 100644
--- a/gen_input/templates/interp/CORENAME.cpp.gtl
+++ b/gen_input/templates/interp/CORENAME.cpp.gtl
@@ -29,7 +29,13 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
+<%
+import com.minres.coredsl.util.BigIntegerWithRadix
 
+def nativeTypeSize(int size){
+    if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
+}
+%>
 #include "../fp_functions.h"
 #include <iss/arch/${coreDef.name.toLowerCase()}.h>
 #include <iss/arch/riscv_hart_m_p.h>
@@ -204,8 +210,8 @@ private:
         }
         // used registers<%instr.usedVariables.each{ k,v->
             if(v.isArray) {%>
-        auto* ${k} = reinterpret_cast<uint${v.type.size}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %> 
-        auto* ${k} = reinterpret_cast<uint${v.type.size}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
+        auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %> 
+        auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
         <%}}%>// calculate next pc value
         *NEXT_PC = *PC + ${instr.length/8};
         // execute instruction
diff --git a/incl/iss/arch/riscv_hart_m_p.h b/incl/iss/arch/riscv_hart_m_p.h
index 1d69f9a..e5dc148 100644
--- a/incl/iss/arch/riscv_hart_m_p.h
+++ b/incl/iss/arch/riscv_hart_m_p.h
@@ -311,6 +311,8 @@ protected:
     iss::status write_dcsr_dcsr(unsigned addr, reg_t val);
     iss::status read_dcsr_reg(unsigned addr, reg_t &val);
     iss::status write_dcsr_reg(unsigned addr, reg_t val);
+    iss::status read_dpc_reg(unsigned addr, reg_t &val);
+    iss::status write_dpc_reg(unsigned addr, reg_t val);
 
     reg_t mhartid_reg{0x0};
     std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
@@ -322,7 +324,7 @@ protected:
     unsigned clic_num_irq{0};
     unsigned clic_num_trigger{0};
     unsigned mcause_max_irq{16};
-    bool debug_mode_active{false};
+    inline bool debug_mode_active() {return this->reg.PRIV&0x4;}
 };
 
 template <typename BASE, features_e FEAT>
@@ -397,8 +399,8 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p()
         csr_rd_cb[dscratch0] = &this_class::read_dcsr_reg;
         csr_wr_cb[dscratch1] = &this_class::write_dcsr_reg;
         csr_rd_cb[dscratch1] = &this_class::read_dcsr_reg;
-        csr_wr_cb[dpc] = &this_class::write_dcsr_reg;
-        csr_rd_cb[dpc] = &this_class::read_dcsr_reg;
+        csr_wr_cb[dpc] = &this_class::write_dpc_reg;
+        csr_rd_cb[dpc] = &this_class::read_dpc_reg;
         csr_wr_cb[dcsr] = &this_class::write_dcsr_dcsr;
         csr_rd_cb[dcsr] = &this_class::read_dcsr_reg;
     }
@@ -815,7 +817,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
 }
 
 template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_dcsr_dcsr(unsigned addr, reg_t val) {
-    if(!debug_mode_active)
+    if(!debug_mode_active())
         throw illegal_instruction_fault(this->fault_data);
     //                  +-------------- ebreakm
     //                  |   +---------- stepi
@@ -826,19 +828,33 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
 }
 
 template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_dcsr_reg(unsigned addr, reg_t &val) {
-    if(!debug_mode_active)
+    if(!debug_mode_active())
         throw illegal_instruction_fault(this->fault_data);
     val = csr[addr];
     return iss::Ok;
 }
 
 template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_dcsr_reg(unsigned addr, reg_t val) {
-    if(!debug_mode_active)
+    if(!debug_mode_active())
         throw illegal_instruction_fault(this->fault_data);
     csr[addr] = val;
     return iss::Ok;
 }
 
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_dpc_reg(unsigned addr, reg_t &val) {
+    if(!debug_mode_active())
+        throw illegal_instruction_fault(this->fault_data);
+    val = this->reg.DPC;
+    return iss::Ok;
+}
+
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_dpc_reg(unsigned addr, reg_t val) {
+    if(!debug_mode_active())
+        throw illegal_instruction_fault(this->fault_data);
+    this->reg.DPC = val;
+    return iss::Ok;
+}
+
 template <typename BASE, features_e FEAT>
 iss::status riscv_hart_m_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
     if(mem_read_cb) return mem_read_cb(paddr, length, data);
diff --git a/incl/iss/arch/riscv_hart_mu_p.h b/incl/iss/arch/riscv_hart_mu_p.h
index 6d0537c..a0d088b 100644
--- a/incl/iss/arch/riscv_hart_mu_p.h
+++ b/incl/iss/arch/riscv_hart_mu_p.h
@@ -328,6 +328,8 @@ protected:
     iss::status write_dcsr_dcsr(unsigned addr, reg_t val);
     iss::status read_dcsr_reg(unsigned addr, reg_t &val);
     iss::status write_dcsr_reg(unsigned addr, reg_t val);
+    iss::status read_dpc_reg(unsigned addr, reg_t &val);
+    iss::status write_dpc_reg(unsigned addr, reg_t val);
 
     reg_t mhartid_reg{0x0};
     std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
@@ -339,7 +341,7 @@ protected:
     unsigned clic_num_irq{0};
     unsigned clic_num_trigger{0};
     unsigned mcause_max_irq{16};
-    bool debug_mode_active{false};
+    inline bool debug_mode_active() {return this->reg.PRIV&0x4;}
 };
 
 template <typename BASE, features_e FEAT>
@@ -469,8 +471,8 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p()
         csr_rd_cb[dscratch0] = &this_class::read_dcsr_reg;
         csr_wr_cb[dscratch1] = &this_class::write_dcsr_reg;
         csr_rd_cb[dscratch1] = &this_class::read_dcsr_reg;
-        csr_wr_cb[dpc] = &this_class::write_dcsr_reg;
-        csr_rd_cb[dpc] = &this_class::read_dcsr_reg;
+        csr_wr_cb[dpc] = &this_class::write_dpc_reg;
+        csr_rd_cb[dpc] = &this_class::read_dpc_reg;
         csr_wr_cb[dcsr] = &this_class::write_dcsr_dcsr;
         csr_rd_cb[dcsr] = &this_class::read_dcsr_reg;
     }
@@ -979,7 +981,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
 }
 
 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_dcsr_dcsr(unsigned addr, reg_t val) {
-    if(!debug_mode_active)
+    if(!debug_mode_active())
         throw illegal_instruction_fault(this->fault_data);
     //                  +-------------- ebreakm
     //                  |   +---------- stepi
@@ -990,19 +992,32 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
 }
 
 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_dcsr_reg(unsigned addr, reg_t &val) {
-    if(!debug_mode_active)
+    if(!debug_mode_active())
         throw illegal_instruction_fault(this->fault_data);
     val = csr[addr];
     return iss::Ok;
 }
 
 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_dcsr_reg(unsigned addr, reg_t val) {
-    if(!debug_mode_active)
+    if(!debug_mode_active())
         throw illegal_instruction_fault(this->fault_data);
     csr[addr] = val;
     return iss::Ok;
 }
 
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_dpc_reg(unsigned addr, reg_t &val) {
+    if(!debug_mode_active())
+        throw illegal_instruction_fault(this->fault_data);
+    val = this->reg.DPC;
+    return iss::Ok;
+}
+
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_dpc_reg(unsigned addr, reg_t val) {
+    if(!debug_mode_active())
+        throw illegal_instruction_fault(this->fault_data);
+    this->reg.DPC = val;
+    return iss::Ok;
+}
 
 template<typename BASE, features_e FEAT>
 iss::status riscv_hart_mu_p<BASE, FEAT>::write_intthresh(unsigned addr, reg_t val) {
diff --git a/incl/iss/arch/tgc_c.h b/incl/iss/arch/tgc_c.h
index e7e440a..2efcaf9 100644
--- a/incl/iss/arch/tgc_c.h
+++ b/incl/iss/arch/tgc_c.h
@@ -47,18 +47,18 @@ template <> struct traits<tgc_c> {
 
     constexpr static char const* const core_type = "TGC_C";
     
-    static constexpr std::array<const char*, 35> reg_names{
-        {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
+    static constexpr std::array<const char*, 36> reg_names{
+        {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV", "DPC"}};
  
-    static constexpr std::array<const char*, 35> reg_aliases{
-        {"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV"}};
+    static constexpr std::array<const char*, 36> reg_aliases{
+        {"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV", "DPC"}};
 
     enum constants {MISA_VAL=0b01000000000000000001000100000100, MARCHID_VAL=0x80000003, XLEN=32, CSR_SIZE=4096, INSTR_ALIGNMENT=2, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
 
     constexpr static unsigned FP_REGS_SIZE = 0;
 
     enum reg_e {
-        X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, NUM_REGS,
+        X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, DPC, NUM_REGS,
         TRAP_STATE=NUM_REGS,
         PENDING_TRAP,
         ICOUNT,
@@ -76,11 +76,11 @@ template <> struct traits<tgc_c> {
 
     using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
 
-    static constexpr std::array<const uint32_t, 40> reg_bit_widths{
-        {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,64,64,64}};
+    static constexpr std::array<const uint32_t, 41> reg_bit_widths{
+        {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,32,64,64,64}};
 
-    static constexpr std::array<const uint32_t, 40> reg_byte_offsets{
-        {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,153,161}};
+    static constexpr std::array<const uint32_t, 41> reg_byte_offsets{
+        {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,149,157,165}};
 
     static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
 
@@ -133,51 +133,52 @@ template <> struct traits<tgc_c> {
         SRET = 41,
         MRET = 42,
         WFI = 43,
-        CSRRW = 44,
-        CSRRS = 45,
-        CSRRC = 46,
-        CSRRWI = 47,
-        CSRRSI = 48,
-        CSRRCI = 49,
-        FENCE_I = 50,
-        MUL = 51,
-        MULH = 52,
-        MULHSU = 53,
-        MULHU = 54,
-        DIV = 55,
-        DIVU = 56,
-        REM = 57,
-        REMU = 58,
-        CADDI4SPN = 59,
-        CLW = 60,
-        CSW = 61,
-        CADDI = 62,
-        CNOP = 63,
-        CJAL = 64,
-        CLI = 65,
-        CLUI = 66,
-        CADDI16SP = 67,
-        __reserved_clui = 68,
-        CSRLI = 69,
-        CSRAI = 70,
-        CANDI = 71,
-        CSUB = 72,
-        CXOR = 73,
-        COR = 74,
-        CAND = 75,
-        CJ = 76,
-        CBEQZ = 77,
-        CBNEZ = 78,
-        CSLLI = 79,
-        CLWSP = 80,
-        CMV = 81,
-        CJR = 82,
-        __reserved_cmv = 83,
-        CADD = 84,
-        CJALR = 85,
-        CEBREAK = 86,
-        CSWSP = 87,
-        DII = 88,
+        DRET = 44,
+        CSRRW = 45,
+        CSRRS = 46,
+        CSRRC = 47,
+        CSRRWI = 48,
+        CSRRSI = 49,
+        CSRRCI = 50,
+        FENCE_I = 51,
+        MUL = 52,
+        MULH = 53,
+        MULHSU = 54,
+        MULHU = 55,
+        DIV = 56,
+        DIVU = 57,
+        REM = 58,
+        REMU = 59,
+        CADDI4SPN = 60,
+        CLW = 61,
+        CSW = 62,
+        CADDI = 63,
+        CNOP = 64,
+        CJAL = 65,
+        CLI = 66,
+        CLUI = 67,
+        CADDI16SP = 68,
+        __reserved_clui = 69,
+        CSRLI = 70,
+        CSRAI = 71,
+        CANDI = 72,
+        CSUB = 73,
+        CXOR = 74,
+        COR = 75,
+        CAND = 76,
+        CJ = 77,
+        CBEQZ = 78,
+        CBNEZ = 79,
+        CSLLI = 80,
+        CLWSP = 81,
+        CMV = 82,
+        CJR = 83,
+        __reserved_cmv = 84,
+        CADD = 85,
+        CJALR = 86,
+        CEBREAK = 87,
+        CSWSP = 88,
+        DII = 89,
         MAX_OPCODE
     };
 };
@@ -253,7 +254,8 @@ protected:
         uint32_t X31 = 0; 
         uint32_t PC = 0; 
         uint32_t NEXT_PC = 0; 
-        uint8_t PRIV = 0;
+        uint8_t PRIV = 0; 
+        uint32_t DPC = 0;
         uint32_t trap_state = 0, pending_trap = 0;
         uint64_t icount = 0;
         uint64_t cycle = 0;
diff --git a/src/iss/tgc_c.cpp b/src/iss/tgc_c.cpp
index 1dd9e89..b5e8fed 100644
--- a/src/iss/tgc_c.cpp
+++ b/src/iss/tgc_c.cpp
@@ -39,10 +39,10 @@
 
 using namespace iss::arch;
 
-constexpr std::array<const char*, 35>    iss::arch::traits<iss::arch::tgc_c>::reg_names;
-constexpr std::array<const char*, 35>    iss::arch::traits<iss::arch::tgc_c>::reg_aliases;
-constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths;
-constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets;
+constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc_c>::reg_names;
+constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc_c>::reg_aliases;
+constexpr std::array<const uint32_t, 41> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths;
+constexpr std::array<const uint32_t, 41> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets;
 
 tgc_c::tgc_c() {
     reg.icount = 0;
diff --git a/src/vm/interp/vm_tgc_c.cpp b/src/vm/interp/vm_tgc_c.cpp
index 7bbcf36..ad50b5a 100644
--- a/src/vm/interp/vm_tgc_c.cpp
+++ b/src/vm/interp/vm_tgc_c.cpp
@@ -180,7 +180,7 @@ private:
         compile_func op;
     };
 
-    const std::array<InstructionDesriptor, 89> instr_descr = {{
+    const std::array<InstructionDesriptor, 90> instr_descr = {{
          /* entries are: size, valid value, valid mask, function ptr */
         /* instruction LUI */
         {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui},
@@ -270,6 +270,8 @@ private:
         {32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__mret},
         /* instruction WFI */
         {32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, &this_class::__wfi},
+        /* instruction DRET */
+        {32, 0b01111011001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__dret},
         /* instruction CSRRW */
         {32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, &this_class::__csrrw},
         /* instruction CSRRS */
@@ -2209,8 +2211,8 @@ private:
         return pc;
     }
     
-    /* instruction 44: CSRRW */
-    compile_ret_t __csrrw(virt_addr_t& pc, code_word_t instr){
+    /* instruction 44: DRET */
+    compile_ret_t __dret(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
         auto NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
@@ -2218,6 +2220,50 @@ private:
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
         if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 44);
+        if(this->disass_enabled){
+            /* generate console output when executing the command */
+            this->core.disass_output(pc.val, "dret");
+            
+        }
+        // used registers 
+        auto* PRIV = reinterpret_cast<uint8_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PRIV]);
+         
+        auto* DPC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::DPC]);
+        // calculate next pc value
+        *NEXT_PC = *PC + 4;
+        // execute instruction
+        try {
+        {
+            if(*PRIV < 4) raise(0,  2); 
+            else {
+                pc_assign(*NEXT_PC) = *DPC;
+                *PRIV &=  0x3;
+            }
+        }
+        } catch(...){}
+        // post execution stuff
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 44);
+        // trap check
+        if(*trap_state!=0){
+            super::core.enter_trap(*trap_state, pc.val, instr);
+        } else {
+            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
+            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
+        }
+        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
+        pc.val=*NEXT_PC;
+        return pc;
+    }
+    
+    /* instruction 45: CSRRW */
+    compile_ret_t __csrrw(virt_addr_t& pc, code_word_t instr){
+        // pre execution stuff
+        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
+        auto NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
+        *PC=*NEXT_PC;
+        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
+        *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 45);
         uint8_t rd = ((bit_sub<7,5>(instr)));
         uint8_t rs1 = ((bit_sub<15,5>(instr)));
         uint16_t csr = ((bit_sub<20,12>(instr)));
@@ -2247,7 +2293,7 @@ private:
         }
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 44);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 45);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -2260,7 +2306,7 @@ private:
         return pc;
     }
     
-    /* instruction 45: CSRRS */
+    /* instruction 46: CSRRS */
     compile_ret_t __csrrs(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -2268,7 +2314,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 45);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 46);
         uint8_t rd = ((bit_sub<7,5>(instr)));
         uint8_t rs1 = ((bit_sub<15,5>(instr)));
         uint16_t csr = ((bit_sub<20,12>(instr)));
@@ -2293,7 +2339,7 @@ private:
         }
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 45);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 46);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -2306,7 +2352,7 @@ private:
         return pc;
     }
     
-    /* instruction 46: CSRRC */
+    /* instruction 47: CSRRC */
     compile_ret_t __csrrc(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -2314,7 +2360,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 46);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 47);
         uint8_t rd = ((bit_sub<7,5>(instr)));
         uint8_t rs1 = ((bit_sub<15,5>(instr)));
         uint16_t csr = ((bit_sub<20,12>(instr)));
@@ -2339,7 +2385,7 @@ private:
         }
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 46);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 47);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -2352,7 +2398,7 @@ private:
         return pc;
     }
     
-    /* instruction 47: CSRRWI */
+    /* instruction 48: CSRRWI */
     compile_ret_t __csrrwi(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -2360,7 +2406,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 47);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 48);
         uint8_t rd = ((bit_sub<7,5>(instr)));
         uint8_t zimm = ((bit_sub<15,5>(instr)));
         uint16_t csr = ((bit_sub<20,12>(instr)));
@@ -2384,7 +2430,7 @@ private:
         }
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 47);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 48);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -2397,7 +2443,7 @@ private:
         return pc;
     }
     
-    /* instruction 48: CSRRSI */
+    /* instruction 49: CSRRSI */
     compile_ret_t __csrrsi(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -2405,7 +2451,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 48);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 49);
         uint8_t rd = ((bit_sub<7,5>(instr)));
         uint8_t zimm = ((bit_sub<15,5>(instr)));
         uint16_t csr = ((bit_sub<20,12>(instr)));
@@ -2429,7 +2475,7 @@ private:
         }
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 48);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 49);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -2442,7 +2488,7 @@ private:
         return pc;
     }
     
-    /* instruction 49: CSRRCI */
+    /* instruction 50: CSRRCI */
     compile_ret_t __csrrci(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -2450,7 +2496,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 49);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 50);
         uint8_t rd = ((bit_sub<7,5>(instr)));
         uint8_t zimm = ((bit_sub<15,5>(instr)));
         uint16_t csr = ((bit_sub<20,12>(instr)));
@@ -2474,7 +2520,7 @@ private:
         }
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 49);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 50);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -2487,7 +2533,7 @@ private:
         return pc;
     }
     
-    /* instruction 50: FENCE_I */
+    /* instruction 51: FENCE_I */
     compile_ret_t __fence_i(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -2495,7 +2541,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 50);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 51);
         uint8_t rd = ((bit_sub<7,5>(instr)));
         uint8_t rs1 = ((bit_sub<15,5>(instr)));
         uint16_t imm = ((bit_sub<20,12>(instr)));
@@ -2514,7 +2560,7 @@ private:
         writeSpace2(traits::FENCE, traits::fencei, imm);
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 50);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 51);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -2527,7 +2573,7 @@ private:
         return pc;
     }
     
-    /* instruction 51: MUL */
+    /* instruction 52: MUL */
     compile_ret_t __mul(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -2535,7 +2581,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 51);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 52);
         uint8_t rd = ((bit_sub<7,5>(instr)));
         uint8_t rs1 = ((bit_sub<15,5>(instr)));
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -2560,7 +2606,7 @@ private:
         }
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 51);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 52);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -2573,7 +2619,7 @@ private:
         return pc;
     }
     
-    /* instruction 52: MULH */
+    /* instruction 53: MULH */
     compile_ret_t __mulh(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -2581,7 +2627,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 52);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 53);
         uint8_t rd = ((bit_sub<7,5>(instr)));
         uint8_t rs1 = ((bit_sub<15,5>(instr)));
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -2606,7 +2652,7 @@ private:
         }
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 52);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 53);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -2619,7 +2665,7 @@ private:
         return pc;
     }
     
-    /* instruction 53: MULHSU */
+    /* instruction 54: MULHSU */
     compile_ret_t __mulhsu(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -2627,7 +2673,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 53);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 54);
         uint8_t rd = ((bit_sub<7,5>(instr)));
         uint8_t rs1 = ((bit_sub<15,5>(instr)));
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -2652,7 +2698,7 @@ private:
         }
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 53);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 54);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -2665,7 +2711,7 @@ private:
         return pc;
     }
     
-    /* instruction 54: MULHU */
+    /* instruction 55: MULHU */
     compile_ret_t __mulhu(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -2673,7 +2719,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 54);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 55);
         uint8_t rd = ((bit_sub<7,5>(instr)));
         uint8_t rs1 = ((bit_sub<15,5>(instr)));
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -2698,7 +2744,7 @@ private:
         }
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 54);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 55);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -2711,7 +2757,7 @@ private:
         return pc;
     }
     
-    /* instruction 55: DIV */
+    /* instruction 56: DIV */
     compile_ret_t __div(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -2719,7 +2765,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 55);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 56);
         uint8_t rd = ((bit_sub<7,5>(instr)));
         uint8_t rs1 = ((bit_sub<15,5>(instr)));
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -2748,7 +2794,7 @@ private:
         }
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 55);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 56);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -2761,7 +2807,7 @@ private:
         return pc;
     }
     
-    /* instruction 56: DIVU */
+    /* instruction 57: DIVU */
     compile_ret_t __divu(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -2769,7 +2815,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 56);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 57);
         uint8_t rd = ((bit_sub<7,5>(instr)));
         uint8_t rs1 = ((bit_sub<15,5>(instr)));
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -2794,7 +2840,7 @@ private:
         }
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 56);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 57);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -2807,7 +2853,7 @@ private:
         return pc;
     }
     
-    /* instruction 57: REM */
+    /* instruction 58: REM */
     compile_ret_t __rem(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -2815,7 +2861,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 57);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 58);
         uint8_t rd = ((bit_sub<7,5>(instr)));
         uint8_t rs1 = ((bit_sub<15,5>(instr)));
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -2844,7 +2890,7 @@ private:
         }
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 57);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 58);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -2857,7 +2903,7 @@ private:
         return pc;
     }
     
-    /* instruction 58: REMU */
+    /* instruction 59: REMU */
     compile_ret_t __remu(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -2865,7 +2911,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 58);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 59);
         uint8_t rd = ((bit_sub<7,5>(instr)));
         uint8_t rs1 = ((bit_sub<15,5>(instr)));
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
@@ -2890,7 +2936,7 @@ private:
         }
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 58);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 59);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -2903,7 +2949,7 @@ private:
         return pc;
     }
     
-    /* instruction 59: CADDI4SPN */
+    /* instruction 60: CADDI4SPN */
     compile_ret_t __caddi4spn(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -2911,7 +2957,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 59);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 60);
         uint8_t rd = ((bit_sub<2,3>(instr)));
         uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4));
         if(this->disass_enabled){
@@ -2931,7 +2977,7 @@ private:
         else raise(0,  2);
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 59);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 60);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -2944,7 +2990,7 @@ private:
         return pc;
     }
     
-    /* instruction 60: CLW */
+    /* instruction 61: CLW */
     compile_ret_t __clw(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -2952,7 +2998,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 60);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 61);
         uint8_t rd = ((bit_sub<2,3>(instr)));
         uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3));
         uint8_t rs1 = ((bit_sub<7,3>(instr)));
@@ -2975,7 +3021,7 @@ private:
         }
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 60);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 61);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -2988,7 +3034,7 @@ private:
         return pc;
     }
     
-    /* instruction 61: CSW */
+    /* instruction 62: CSW */
     compile_ret_t __csw(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -2996,7 +3042,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 61);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 62);
         uint8_t rs2 = ((bit_sub<2,3>(instr)));
         uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3));
         uint8_t rs1 = ((bit_sub<7,3>(instr)));
@@ -3019,7 +3065,7 @@ private:
         }
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 61);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 62);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -3032,7 +3078,7 @@ private:
         return pc;
     }
     
-    /* instruction 62: CADDI */
+    /* instruction 63: CADDI */
     compile_ret_t __caddi(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -3040,7 +3086,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 62);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 63);
         uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
         uint8_t rs1 = ((bit_sub<7,5>(instr)));
         if(this->disass_enabled){
@@ -3059,7 +3105,7 @@ private:
         *(X+rs1) = *(X+rs1) + (int8_t)sext<6>(imm);
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 62);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 63);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -3072,7 +3118,7 @@ private:
         return pc;
     }
     
-    /* instruction 63: CNOP */
+    /* instruction 64: CNOP */
     compile_ret_t __cnop(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -3080,7 +3126,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 63);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 64);
         uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
         if(this->disass_enabled){
             /* generate console output when executing the command */
@@ -3095,7 +3141,7 @@ private:
         }
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 63);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 64);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -3108,7 +3154,7 @@ private:
         return pc;
     }
     
-    /* instruction 64: CJAL */
+    /* instruction 65: CJAL */
     compile_ret_t __cjal(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -3116,7 +3162,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 64);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 65);
         uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11));
         if(this->disass_enabled){
             /* generate console output when executing the command */
@@ -3137,7 +3183,7 @@ private:
         }
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 64);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 65);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -3150,7 +3196,7 @@ private:
         return pc;
     }
     
-    /* instruction 65: CLI */
+    /* instruction 66: CLI */
     compile_ret_t __cli(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -3158,7 +3204,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 65);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 66);
         uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
         uint8_t rd = ((bit_sub<7,5>(instr)));
         if(this->disass_enabled){
@@ -3179,7 +3225,7 @@ private:
         }
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 65);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 66);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -3192,7 +3238,7 @@ private:
         return pc;
     }
     
-    /* instruction 66: CLUI */
+    /* instruction 67: CLUI */
     compile_ret_t __clui(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -3200,7 +3246,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 66);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 67);
         uint32_t imm = ((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17));
         uint8_t rd = ((bit_sub<7,5>(instr)));
         if(this->disass_enabled){
@@ -3222,7 +3268,7 @@ private:
         }
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 66);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 67);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -3235,7 +3281,7 @@ private:
         return pc;
     }
     
-    /* instruction 67: CADDI16SP */
+    /* instruction 68: CADDI16SP */
     compile_ret_t __caddi16sp(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -3243,7 +3289,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 67);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 68);
         uint16_t nzimm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9));
         if(this->disass_enabled){
             /* generate console output when executing the command */
@@ -3262,41 +3308,6 @@ private:
         else raise(0,  2);
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 67);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 68: __reserved_clui */
-    compile_ret_t ____reserved_clui(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        *PC=*NEXT_PC;
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 68);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            this->core.disass_output(pc.val, "__reserved_clui");
-            
-        }
-        // used registers// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        raise(0,  2);
-        } catch(...){}
-        // post execution stuff
         if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 68);
         // trap check
         if(*trap_state!=0){
@@ -3310,8 +3321,8 @@ private:
         return pc;
     }
     
-    /* instruction 69: CSRLI */
-    compile_ret_t __csrli(virt_addr_t& pc, code_word_t instr){
+    /* instruction 69: __reserved_clui */
+    compile_ret_t ____reserved_clui(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
         auto NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
@@ -3319,6 +3330,41 @@ private:
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
         if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 69);
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        if(this->disass_enabled){
+            /* generate console output when executing the command */
+            this->core.disass_output(pc.val, "__reserved_clui");
+            
+        }
+        // used registers// calculate next pc value
+        *NEXT_PC = *PC + 2;
+        // execute instruction
+        try {
+        raise(0,  2);
+        } catch(...){}
+        // post execution stuff
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 69);
+        // trap check
+        if(*trap_state!=0){
+            super::core.enter_trap(*trap_state, pc.val, instr);
+        } else {
+            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
+            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
+        }
+        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
+        pc.val=*NEXT_PC;
+        return pc;
+    }
+    
+    /* instruction 70: CSRLI */
+    compile_ret_t __csrli(virt_addr_t& pc, code_word_t instr){
+        // pre execution stuff
+        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
+        auto NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
+        *PC=*NEXT_PC;
+        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
+        *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 70);
         uint8_t shamt = ((bit_sub<2,5>(instr)));
         uint8_t rs1 = ((bit_sub<7,3>(instr)));
         if(this->disass_enabled){
@@ -3340,7 +3386,7 @@ private:
         }
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 69);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 70);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -3353,7 +3399,7 @@ private:
         return pc;
     }
     
-    /* instruction 70: CSRAI */
+    /* instruction 71: CSRAI */
     compile_ret_t __csrai(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -3361,7 +3407,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 70);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 71);
         uint8_t shamt = ((bit_sub<2,5>(instr)));
         uint8_t rs1 = ((bit_sub<7,3>(instr)));
         if(this->disass_enabled){
@@ -3387,7 +3433,7 @@ private:
         }
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 70);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 71);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -3400,7 +3446,7 @@ private:
         return pc;
     }
     
-    /* instruction 71: CANDI */
+    /* instruction 72: CANDI */
     compile_ret_t __candi(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -3408,7 +3454,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 71);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 72);
         uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
         uint8_t rs1 = ((bit_sub<7,3>(instr)));
         if(this->disass_enabled){
@@ -3430,7 +3476,7 @@ private:
         }
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 71);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 72);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -3443,7 +3489,7 @@ private:
         return pc;
     }
     
-    /* instruction 72: CSUB */
+    /* instruction 73: CSUB */
     compile_ret_t __csub(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -3451,7 +3497,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 72);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 73);
         uint8_t rs2 = ((bit_sub<2,3>(instr)));
         uint8_t rd = ((bit_sub<7,3>(instr)));
         if(this->disass_enabled){
@@ -3473,7 +3519,7 @@ private:
         }
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 72);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 73);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -3486,7 +3532,7 @@ private:
         return pc;
     }
     
-    /* instruction 73: CXOR */
+    /* instruction 74: CXOR */
     compile_ret_t __cxor(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -3494,7 +3540,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 73);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 74);
         uint8_t rs2 = ((bit_sub<2,3>(instr)));
         uint8_t rd = ((bit_sub<7,3>(instr)));
         if(this->disass_enabled){
@@ -3516,7 +3562,7 @@ private:
         }
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 73);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 74);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -3529,7 +3575,7 @@ private:
         return pc;
     }
     
-    /* instruction 74: COR */
+    /* instruction 75: COR */
     compile_ret_t __cor(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -3537,7 +3583,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 74);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 75);
         uint8_t rs2 = ((bit_sub<2,3>(instr)));
         uint8_t rd = ((bit_sub<7,3>(instr)));
         if(this->disass_enabled){
@@ -3559,7 +3605,7 @@ private:
         }
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 74);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 75);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -3572,7 +3618,7 @@ private:
         return pc;
     }
     
-    /* instruction 75: CAND */
+    /* instruction 76: CAND */
     compile_ret_t __cand(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -3580,7 +3626,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 75);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 76);
         uint8_t rs2 = ((bit_sub<2,3>(instr)));
         uint8_t rd = ((bit_sub<7,3>(instr)));
         if(this->disass_enabled){
@@ -3602,7 +3648,7 @@ private:
         }
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 75);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 76);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -3615,7 +3661,7 @@ private:
         return pc;
     }
     
-    /* instruction 76: CJ */
+    /* instruction 77: CJ */
     compile_ret_t __cj(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -3623,7 +3669,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 76);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 77);
         uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11));
         if(this->disass_enabled){
             /* generate console output when executing the command */
@@ -3640,7 +3686,7 @@ private:
         pc_assign(*NEXT_PC) = *PC + (int16_t)sext<12>(imm);
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 76);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 77);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -3653,7 +3699,7 @@ private:
         return pc;
     }
     
-    /* instruction 77: CBEQZ */
+    /* instruction 78: CBEQZ */
     compile_ret_t __cbeqz(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -3661,7 +3707,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 77);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 78);
         uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8));
         uint8_t rs1 = ((bit_sub<7,3>(instr)));
         if(this->disass_enabled){
@@ -3680,7 +3726,7 @@ private:
         if(*(X+(rs1 + 8)) == 0) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<9>(imm); 
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 77);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 78);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -3693,7 +3739,7 @@ private:
         return pc;
     }
     
-    /* instruction 78: CBNEZ */
+    /* instruction 79: CBNEZ */
     compile_ret_t __cbnez(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -3701,7 +3747,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 78);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 79);
         uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8));
         uint8_t rs1 = ((bit_sub<7,3>(instr)));
         if(this->disass_enabled){
@@ -3720,7 +3766,7 @@ private:
         if(*(X+(rs1 + 8)) != 0) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<9>(imm); 
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 78);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 79);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -3733,7 +3779,7 @@ private:
         return pc;
     }
     
-    /* instruction 79: CSLLI */
+    /* instruction 80: CSLLI */
     compile_ret_t __cslli(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -3741,7 +3787,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 79);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 80);
         uint8_t nzuimm = ((bit_sub<2,5>(instr)));
         uint8_t rs1 = ((bit_sub<7,5>(instr)));
         if(this->disass_enabled){
@@ -3760,7 +3806,7 @@ private:
         if(nzuimm) *(X+rs1) = *(X+rs1) << nzuimm; 
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 79);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 80);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -3773,7 +3819,7 @@ private:
         return pc;
     }
     
-    /* instruction 80: CLWSP */
+    /* instruction 81: CLWSP */
     compile_ret_t __clwsp(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -3781,7 +3827,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 80);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 81);
         uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5));
         uint8_t rd = ((bit_sub<7,5>(instr)));
         if(this->disass_enabled){
@@ -3804,7 +3850,7 @@ private:
         else raise(0, 2);
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 80);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 81);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -3817,7 +3863,7 @@ private:
         return pc;
     }
     
-    /* instruction 81: CMV */
+    /* instruction 82: CMV */
     compile_ret_t __cmv(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -3825,7 +3871,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 81);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 82);
         uint8_t rs2 = ((bit_sub<2,5>(instr)));
         uint8_t rd = ((bit_sub<7,5>(instr)));
         if(this->disass_enabled){
@@ -3844,7 +3890,7 @@ private:
         if(rd != 0) *(X+rd) = *(X+rs2); 
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 81);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 82);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -3857,7 +3903,7 @@ private:
         return pc;
     }
     
-    /* instruction 82: CJR */
+    /* instruction 83: CJR */
     compile_ret_t __cjr(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -3865,7 +3911,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 82);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 83);
         uint8_t rs1 = ((bit_sub<7,5>(instr)));
         if(this->disass_enabled){
             /* generate console output when executing the command */
@@ -3884,40 +3930,6 @@ private:
         else raise(0, 2);
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 82);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 83: __reserved_cmv */
-    compile_ret_t ____reserved_cmv(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        *PC=*NEXT_PC;
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 83);
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            this->core.disass_output(pc.val, "__reserved_cmv");
-            
-        }
-        // used registers// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        raise(0, 2);
-        } catch(...){}
-        // post execution stuff
         if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 83);
         // trap check
         if(*trap_state!=0){
@@ -3931,8 +3943,8 @@ private:
         return pc;
     }
     
-    /* instruction 84: CADD */
-    compile_ret_t __cadd(virt_addr_t& pc, code_word_t instr){
+    /* instruction 84: __reserved_cmv */
+    compile_ret_t ____reserved_cmv(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
         auto NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
@@ -3940,6 +3952,40 @@ private:
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
         if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 84);
+        if(this->disass_enabled){
+            /* generate console output when executing the command */
+            this->core.disass_output(pc.val, "__reserved_cmv");
+            
+        }
+        // used registers// calculate next pc value
+        *NEXT_PC = *PC + 2;
+        // execute instruction
+        try {
+        raise(0, 2);
+        } catch(...){}
+        // post execution stuff
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 84);
+        // trap check
+        if(*trap_state!=0){
+            super::core.enter_trap(*trap_state, pc.val, instr);
+        } else {
+            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
+            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
+        }
+        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
+        pc.val=*NEXT_PC;
+        return pc;
+    }
+    
+    /* instruction 85: CADD */
+    compile_ret_t __cadd(virt_addr_t& pc, code_word_t instr){
+        // pre execution stuff
+        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
+        auto NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
+        *PC=*NEXT_PC;
+        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
+        *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 85);
         uint8_t rs2 = ((bit_sub<2,5>(instr)));
         uint8_t rd = ((bit_sub<7,5>(instr)));
         if(this->disass_enabled){
@@ -3958,7 +4004,7 @@ private:
         if(rd != 0) *(X+rd) = *(X+rd) + *(X+rs2); 
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 84);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 85);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -3971,7 +4017,7 @@ private:
         return pc;
     }
     
-    /* instruction 85: CJALR */
+    /* instruction 86: CJALR */
     compile_ret_t __cjalr(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -3979,7 +4025,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 85);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 86);
         uint8_t rs1 = ((bit_sub<7,5>(instr)));
         if(this->disass_enabled){
             /* generate console output when executing the command */
@@ -4001,40 +4047,6 @@ private:
         }
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 85);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 86: CEBREAK */
-    compile_ret_t __cebreak(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        *PC=*NEXT_PC;
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 86);
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            this->core.disass_output(pc.val, "cebreak");
-            
-        }
-        // used registers// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        raise(0,  3);
-        } catch(...){}
-        // post execution stuff
         if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 86);
         // trap check
         if(*trap_state!=0){
@@ -4048,8 +4060,8 @@ private:
         return pc;
     }
     
-    /* instruction 87: CSWSP */
-    compile_ret_t __cswsp(virt_addr_t& pc, code_word_t instr){
+    /* instruction 87: CEBREAK */
+    compile_ret_t __cebreak(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
         auto NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
@@ -4057,6 +4069,40 @@ private:
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
         if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 87);
+        if(this->disass_enabled){
+            /* generate console output when executing the command */
+            this->core.disass_output(pc.val, "cebreak");
+            
+        }
+        // used registers// calculate next pc value
+        *NEXT_PC = *PC + 2;
+        // execute instruction
+        try {
+        raise(0,  3);
+        } catch(...){}
+        // post execution stuff
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 87);
+        // trap check
+        if(*trap_state!=0){
+            super::core.enter_trap(*trap_state, pc.val, instr);
+        } else {
+            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
+            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
+        }
+        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
+        pc.val=*NEXT_PC;
+        return pc;
+    }
+    
+    /* instruction 88: CSWSP */
+    compile_ret_t __cswsp(virt_addr_t& pc, code_word_t instr){
+        // pre execution stuff
+        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
+        auto NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
+        *PC=*NEXT_PC;
+        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
+        *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 88);
         uint8_t rs2 = ((bit_sub<2,5>(instr)));
         uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2));
         if(this->disass_enabled){
@@ -4078,7 +4124,7 @@ private:
         }
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 87);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 88);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);
@@ -4091,7 +4137,7 @@ private:
         return pc;
     }
     
-    /* instruction 88: DII */
+    /* instruction 89: DII */
     compile_ret_t __dii(virt_addr_t& pc, code_word_t instr){
         // pre execution stuff
         auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@@ -4099,7 +4145,7 @@ private:
         *PC=*NEXT_PC;
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
         *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 88);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 89);
         if(this->disass_enabled){
             /* generate console output when executing the command */
             this->core.disass_output(pc.val, "dii");
@@ -4112,7 +4158,7 @@ private:
         raise(0,  2);
         } catch(...){}
         // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 88);
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 89);
         // trap check
         if(*trap_state!=0){
             super::core.enter_trap(*trap_state, pc.val, instr);