removes use of exceptions to report bus errors

This commit is contained in:
2025-07-06 15:11:11 +02:00
parent d5d195845c
commit c1aed64a41

View File

@ -230,11 +230,6 @@ public:
trap_load_access_fault(uint64_t badaddr) trap_load_access_fault(uint64_t badaddr)
: trap_access(5 << 16, badaddr) {} : trap_access(5 << 16, badaddr) {}
}; };
class illegal_instruction_fault : public trap_access {
public:
illegal_instruction_fault(uint64_t badaddr)
: trap_access(2 << 16, badaddr) {}
};
class trap_instruction_page_fault : public trap_access { class trap_instruction_page_fault : public trap_access {
public: public:
trap_instruction_page_fault(uint64_t badaddr) trap_instruction_page_fault(uint64_t badaddr)
@ -523,10 +518,10 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
return iss::Err; return iss::Err;
auto req_priv_lvl = (addr >> 8) & 0x3; auto req_priv_lvl = (addr >> 8) & 0x3;
if(this->reg.PRIV < req_priv_lvl) // not having required privileges if(this->reg.PRIV < req_priv_lvl) // not having required privileges
throw illegal_instruction_fault(this->fault_data); return iss::Err;
auto it = csr_rd_cb.find(addr); auto it = csr_rd_cb.find(addr);
if(it == csr_rd_cb.end() || !it->second) // non existent register if(it == csr_rd_cb.end() || !it->second) // non existent register
throw illegal_instruction_fault(this->fault_data); return iss::Err;
return it->second(addr, val); return it->second(addr, val);
} }
@ -535,12 +530,12 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
return iss::Err; return iss::Err;
auto req_priv_lvl = (addr >> 8) & 0x3; auto req_priv_lvl = (addr >> 8) & 0x3;
if(this->reg.PRIV < req_priv_lvl) // not having required privileges if(this->reg.PRIV < req_priv_lvl) // not having required privileges
throw illegal_instruction_fault(this->fault_data); return iss::Err;
if((addr & 0xc00) == 0xc00) // writing to read-only region if((addr & 0xc00) == 0xc00) // writing to read-only region
throw illegal_instruction_fault(this->fault_data); return iss::Err;
auto it = csr_wr_cb.find(addr); auto it = csr_wr_cb.find(addr);
if(it == csr_wr_cb.end() || !it->second) // non existent register if(it == csr_wr_cb.end() || !it->second) // non existent register
throw illegal_instruction_fault(this->fault_data); return iss::Err;
return it->second(addr, val); return it->second(addr, val);
} }
@ -637,7 +632,7 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
iss::status write_dcsr(unsigned addr, reg_t val) { iss::status write_dcsr(unsigned addr, reg_t val) {
if(!debug_mode_active()) if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data); return iss::Err;
// +-------------- ebreakm // +-------------- ebreakm
// | +---------- stepi // | +---------- stepi
// | | +++----- cause // | | +++----- cause
@ -648,28 +643,28 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
iss::status read_debug(unsigned addr, reg_t& val) { iss::status read_debug(unsigned addr, reg_t& val) {
if(!debug_mode_active()) if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data); return iss::Err;
val = csr[addr]; val = csr[addr];
return iss::Ok; return iss::Ok;
} }
iss::status write_dscratch(unsigned addr, reg_t val) { iss::status write_dscratch(unsigned addr, reg_t val) {
if(!debug_mode_active()) if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data); return iss::Err;
csr[addr] = val; csr[addr] = val;
return iss::Ok; return iss::Ok;
} }
iss::status read_dpc(unsigned addr, reg_t& val) { iss::status read_dpc(unsigned addr, reg_t& val) {
if(!debug_mode_active()) if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data); return iss::Err;
val = this->reg.DPC; val = this->reg.DPC;
return iss::Ok; return iss::Ok;
} }
iss::status write_dpc(unsigned addr, reg_t val) { iss::status write_dpc(unsigned addr, reg_t val) {
if(!debug_mode_active()) if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data); return iss::Err;
this->reg.DPC = val; this->reg.DPC = val;
return iss::Ok; return iss::Ok;
} }