removes use of exceptions to report bus errors
This commit is contained in:
@ -230,11 +230,6 @@ public:
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trap_load_access_fault(uint64_t badaddr)
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trap_load_access_fault(uint64_t badaddr)
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: trap_access(5 << 16, badaddr) {}
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: trap_access(5 << 16, badaddr) {}
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};
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};
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class illegal_instruction_fault : public trap_access {
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public:
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illegal_instruction_fault(uint64_t badaddr)
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: trap_access(2 << 16, badaddr) {}
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};
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class trap_instruction_page_fault : public trap_access {
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class trap_instruction_page_fault : public trap_access {
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public:
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public:
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trap_instruction_page_fault(uint64_t badaddr)
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trap_instruction_page_fault(uint64_t badaddr)
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@ -523,10 +518,10 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
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return iss::Err;
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return iss::Err;
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auto req_priv_lvl = (addr >> 8) & 0x3;
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auto req_priv_lvl = (addr >> 8) & 0x3;
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if(this->reg.PRIV < req_priv_lvl) // not having required privileges
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if(this->reg.PRIV < req_priv_lvl) // not having required privileges
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throw illegal_instruction_fault(this->fault_data);
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return iss::Err;
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auto it = csr_rd_cb.find(addr);
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auto it = csr_rd_cb.find(addr);
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if(it == csr_rd_cb.end() || !it->second) // non existent register
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if(it == csr_rd_cb.end() || !it->second) // non existent register
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throw illegal_instruction_fault(this->fault_data);
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return iss::Err;
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return it->second(addr, val);
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return it->second(addr, val);
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}
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}
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@ -535,12 +530,12 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
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return iss::Err;
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return iss::Err;
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auto req_priv_lvl = (addr >> 8) & 0x3;
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auto req_priv_lvl = (addr >> 8) & 0x3;
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if(this->reg.PRIV < req_priv_lvl) // not having required privileges
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if(this->reg.PRIV < req_priv_lvl) // not having required privileges
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throw illegal_instruction_fault(this->fault_data);
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return iss::Err;
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if((addr & 0xc00) == 0xc00) // writing to read-only region
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if((addr & 0xc00) == 0xc00) // writing to read-only region
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throw illegal_instruction_fault(this->fault_data);
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return iss::Err;
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auto it = csr_wr_cb.find(addr);
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auto it = csr_wr_cb.find(addr);
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if(it == csr_wr_cb.end() || !it->second) // non existent register
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if(it == csr_wr_cb.end() || !it->second) // non existent register
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throw illegal_instruction_fault(this->fault_data);
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return iss::Err;
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return it->second(addr, val);
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return it->second(addr, val);
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}
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}
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@ -637,7 +632,7 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
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iss::status write_dcsr(unsigned addr, reg_t val) {
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iss::status write_dcsr(unsigned addr, reg_t val) {
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if(!debug_mode_active())
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if(!debug_mode_active())
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throw illegal_instruction_fault(this->fault_data);
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return iss::Err;
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// +-------------- ebreakm
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// +-------------- ebreakm
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// | +---------- stepi
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// | +---------- stepi
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// | | +++----- cause
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// | | +++----- cause
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@ -648,28 +643,28 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
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iss::status read_debug(unsigned addr, reg_t& val) {
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iss::status read_debug(unsigned addr, reg_t& val) {
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if(!debug_mode_active())
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if(!debug_mode_active())
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throw illegal_instruction_fault(this->fault_data);
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return iss::Err;
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val = csr[addr];
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val = csr[addr];
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return iss::Ok;
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return iss::Ok;
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}
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}
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iss::status write_dscratch(unsigned addr, reg_t val) {
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iss::status write_dscratch(unsigned addr, reg_t val) {
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if(!debug_mode_active())
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if(!debug_mode_active())
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throw illegal_instruction_fault(this->fault_data);
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return iss::Err;
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csr[addr] = val;
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csr[addr] = val;
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return iss::Ok;
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return iss::Ok;
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}
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}
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iss::status read_dpc(unsigned addr, reg_t& val) {
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iss::status read_dpc(unsigned addr, reg_t& val) {
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if(!debug_mode_active())
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if(!debug_mode_active())
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throw illegal_instruction_fault(this->fault_data);
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return iss::Err;
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val = this->reg.DPC;
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val = this->reg.DPC;
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return iss::Ok;
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return iss::Ok;
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}
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}
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iss::status write_dpc(unsigned addr, reg_t val) {
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iss::status write_dpc(unsigned addr, reg_t val) {
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if(!debug_mode_active())
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if(!debug_mode_active())
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throw illegal_instruction_fault(this->fault_data);
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return iss::Err;
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this->reg.DPC = val;
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this->reg.DPC = val;
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return iss::Ok;
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return iss::Ok;
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}
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}
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