From c1aed64a41efb674a4efb49f5a55e230f8a21b45 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Sun, 6 Jul 2025 15:11:11 +0200
Subject: [PATCH] removes use of exceptions to report bus errors

---
 src/iss/arch/riscv_hart_common.h | 25 ++++++++++---------------
 1 file changed, 10 insertions(+), 15 deletions(-)

diff --git a/src/iss/arch/riscv_hart_common.h b/src/iss/arch/riscv_hart_common.h
index d85a562..da5fe29 100644
--- a/src/iss/arch/riscv_hart_common.h
+++ b/src/iss/arch/riscv_hart_common.h
@@ -230,11 +230,6 @@ public:
     trap_load_access_fault(uint64_t badaddr)
     : trap_access(5 << 16, badaddr) {}
 };
-class illegal_instruction_fault : public trap_access {
-public:
-    illegal_instruction_fault(uint64_t badaddr)
-    : trap_access(2 << 16, badaddr) {}
-};
 class trap_instruction_page_fault : public trap_access {
 public:
     trap_instruction_page_fault(uint64_t badaddr)
@@ -523,10 +518,10 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
             return iss::Err;
         auto req_priv_lvl = (addr >> 8) & 0x3;
         if(this->reg.PRIV < req_priv_lvl) // not having required privileges
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         auto it = csr_rd_cb.find(addr);
         if(it == csr_rd_cb.end() || !it->second) // non existent register
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         return it->second(addr, val);
     }
 
@@ -535,12 +530,12 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
             return iss::Err;
         auto req_priv_lvl = (addr >> 8) & 0x3;
         if(this->reg.PRIV < req_priv_lvl) // not having required privileges
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         if((addr & 0xc00) == 0xc00) // writing to read-only region
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         auto it = csr_wr_cb.find(addr);
         if(it == csr_wr_cb.end() || !it->second) // non existent register
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         return it->second(addr, val);
     }
 
@@ -637,7 +632,7 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
 
     iss::status write_dcsr(unsigned addr, reg_t val) {
         if(!debug_mode_active())
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         //                  +-------------- ebreakm
         //                  |   +---------- stepi
         //                  |   |  +++----- cause
@@ -648,28 +643,28 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
 
     iss::status read_debug(unsigned addr, reg_t& val) {
         if(!debug_mode_active())
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         val = csr[addr];
         return iss::Ok;
     }
 
     iss::status write_dscratch(unsigned addr, reg_t val) {
         if(!debug_mode_active())
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         csr[addr] = val;
         return iss::Ok;
     }
 
     iss::status read_dpc(unsigned addr, reg_t& val) {
         if(!debug_mode_active())
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         val = this->reg.DPC;
         return iss::Ok;
     }
 
     iss::status write_dpc(unsigned addr, reg_t val) {
         if(!debug_mode_active())
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         this->reg.DPC = val;
         return iss::Ok;
     }