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DBT-RISE-TGC
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adapt to extended instrumentation interface

This commit is contained in:
Eyck Jentzsch 2022-02-09 21:01:17 +01:00
parent ac86f14a54
commit b8fa5fbbda
4 changed files with 12 additions and 1 deletions
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1
gen_input/templates/CORENAME.h.gtl
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@ -169,7 +169,6 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
}}%>
uint32_t trap_state = 0, pending_trap = 0;
uint64_t icount = 0;
uint64_t cycle = 0;
uint64_t instret = 0;
uint32_t last_branch;
} reg;

4
incl/iss/arch/riscv_hart_m_p.h
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@ -237,6 +237,10 @@ protected:
uint64_t get_next_pc() override { return arch.get_next_pc(); };
uint64_t get_instr_count() { return arch.reg.icount; }
uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }
void set_curr_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
riscv_hart_m_p<BASE, FEAT> &arch;

4
incl/iss/arch/riscv_hart_msu_vp.h
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@ -340,6 +340,10 @@ protected:
virtual uint64_t get_next_pc() { return arch.get_next_pc(); };
uint64_t get_instr_count() { return arch.reg.icount; }
uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }
virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; };
riscv_hart_msu_vp<BASE> &arch;

4
incl/iss/arch/riscv_hart_mu_p.h
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@ -252,6 +252,10 @@ protected:
virtual uint64_t get_next_pc() { return arch.get_next_pc(); };
uint64_t get_instr_count() { return arch.reg.icount; }
uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }
virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; };
riscv_hart_mu_p<BASE, FEAT> &arch;