From b8fa5fbbda1690ff37d0357b55440bc548d80dbe Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Wed, 9 Feb 2022 21:01:17 +0100
Subject: [PATCH] adapt to extended instrumentation interface

---
 gen_input/templates/CORENAME.h.gtl | 1 -
 incl/iss/arch/riscv_hart_m_p.h     | 4 ++++
 incl/iss/arch/riscv_hart_msu_vp.h  | 4 ++++
 incl/iss/arch/riscv_hart_mu_p.h    | 4 ++++
 4 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/gen_input/templates/CORENAME.h.gtl b/gen_input/templates/CORENAME.h.gtl
index fa69704..dbe4c82 100644
--- a/gen_input/templates/CORENAME.h.gtl
+++ b/gen_input/templates/CORENAME.h.gtl
@@ -169,7 +169,6 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
         }}%>
         uint32_t trap_state = 0, pending_trap = 0;
         uint64_t icount = 0;
-        uint64_t cycle = 0;
         uint64_t instret = 0;
         uint32_t last_branch;
     } reg;
diff --git a/incl/iss/arch/riscv_hart_m_p.h b/incl/iss/arch/riscv_hart_m_p.h
index b50b990..91dd7b4 100644
--- a/incl/iss/arch/riscv_hart_m_p.h
+++ b/incl/iss/arch/riscv_hart_m_p.h
@@ -237,6 +237,10 @@ protected:
 
         uint64_t get_next_pc() override { return arch.get_next_pc(); };
 
+        uint64_t get_instr_count() { return arch.reg.icount; }
+
+        uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }
+
         void set_curr_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
 
         riscv_hart_m_p<BASE, FEAT> &arch;
diff --git a/incl/iss/arch/riscv_hart_msu_vp.h b/incl/iss/arch/riscv_hart_msu_vp.h
index 196cae5..4ba669e 100644
--- a/incl/iss/arch/riscv_hart_msu_vp.h
+++ b/incl/iss/arch/riscv_hart_msu_vp.h
@@ -340,6 +340,10 @@ protected:
 
         virtual uint64_t get_next_pc() { return arch.get_next_pc(); };
 
+        uint64_t get_instr_count() { return arch.reg.icount; }
+
+        uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }
+
         virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; };
 
         riscv_hart_msu_vp<BASE> &arch;
diff --git a/incl/iss/arch/riscv_hart_mu_p.h b/incl/iss/arch/riscv_hart_mu_p.h
index 754ea1c..ab0444c 100644
--- a/incl/iss/arch/riscv_hart_mu_p.h
+++ b/incl/iss/arch/riscv_hart_mu_p.h
@@ -252,6 +252,10 @@ protected:
 
         virtual uint64_t get_next_pc() { return arch.get_next_pc(); };
 
+        uint64_t get_instr_count() { return arch.reg.icount; }
+
+        uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }
+
         virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; };
 
         riscv_hart_mu_p<BASE, FEAT> &arch;