DBT-RISE
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DBT-RISE-TGC
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sets reset start time to 0

This commit is contained in:
Eyck Jentzsch 2023-05-02 11:21:42 +02:00
parent f9e8e1d857
commit b493745cd7
2 changed files with 2 additions and 1 deletions
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2
contrib/tgc_import_tb.tcl
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@ -28,7 +28,7 @@ set clock "Clk"
puts "instantiating reset manager" puts "instantiating reset manager"
set reset "Rst" set reset "Rst"
::hw::create_hw_instance "" GenericIPlib:ResetGenerator ${reset}_reset ::hw::create_hw_instance "" GenericIPlib:ResetGenerator ${reset}_reset
::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time 1000 ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time 0
::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time_unit sc_core::SC_PS ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time_unit sc_core::SC_PS
::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration 10000 ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration 10000
::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration_unit sc_core::SC_PS ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration_unit sc_core::SC_PS

1
src/sysc/core_complex.cpp
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@ -500,6 +500,7 @@ void core_complex::local_irq_cb() {
void core_complex::run() { void core_complex::run() {
wait(SC_ZERO_TIME); // separate from elaboration phase wait(SC_ZERO_TIME); // separate from elaboration phase
do { do {
wait(SC_ZERO_TIME);
if (rst_i.read()) { if (rst_i.read()) {
cpu->reset(GET_PROP_VALUE(reset_address)); cpu->reset(GET_PROP_VALUE(reset_address));
wait(rst_i.negedge_event()); wait(rst_i.negedge_event());