DBT-RISE
/
DBT-RISE-TGC
11
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

Applied clang-format

This commit is contained in:
Eyck Jentzsch 2017-09-22 11:23:23 +02:00
parent 39150b68c0
commit b38319f9c2
34 changed files with 5579 additions and 6723 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

97
.clang-format Normal file
View File

@ -0,0 +1,97 @@
---
Language: Cpp
# BasedOnStyle: LLVM
# should be in line with IndentWidth
AccessModifierOffset: -4
AlignAfterOpenBracket: Align
AlignConsecutiveAssignments: false
AlignConsecutiveDeclarations: false
AlignEscapedNewlinesLeft: false
AlignOperands: true
AlignTrailingComments: true
AllowAllParametersOfDeclarationOnNextLine: true
AllowShortBlocksOnASingleLine: false
AllowShortCaseLabelsOnASingleLine: false
AllowShortFunctionsOnASingleLine: All
AllowShortIfStatementsOnASingleLine: true
AllowShortLoopsOnASingleLine: true
AlwaysBreakAfterDefinitionReturnType: None
AlwaysBreakAfterReturnType: None
AlwaysBreakBeforeMultilineStrings: false
AlwaysBreakTemplateDeclarations: false
BinPackArguments: true
BinPackParameters: true
BraceWrapping:
AfterClass: false
AfterControlStatement: false
AfterEnum: false
AfterFunction: false
AfterNamespace: false
AfterObjCDeclaration: false
AfterStruct: false
AfterUnion: false
BeforeCatch: false
BeforeElse: false
IndentBraces: false
BreakBeforeBinaryOperators: None
BreakBeforeBraces: Attach
BreakBeforeTernaryOperators: true
BreakConstructorInitializersBeforeComma: false
BreakAfterJavaFieldAnnotations: false
BreakStringLiterals: true
ColumnLimit: 120
CommentPragmas: '^ IWYU pragma:'
ConstructorInitializerAllOnOneLineOrOnePerLine: false
ConstructorInitializerIndentWidth: 4
ContinuationIndentWidth: 4
Cpp11BracedListStyle: true
DerivePointerAlignment: false
DisableFormat: false
ExperimentalAutoDetectBinPacking: false
ForEachMacros: [ foreach, Q_FOREACH, BOOST_FOREACH ]
IncludeCategories:
- Regex: '^"(llvm|llvm-c|clang|clang-c)/'
Priority: 2
- Regex: '^(<|"(gtest|isl|json)/)'
Priority: 3
- Regex: '.*'
Priority: 1
IncludeIsMainRegex: '$'
IndentCaseLabels: false
IndentWidth: 4
IndentWrappedFunctionNames: false
JavaScriptQuotes: Leave
JavaScriptWrapImports: true
KeepEmptyLinesAtTheStartOfBlocks: true
MacroBlockBegin: ''
MacroBlockEnd: ''
MaxEmptyLinesToKeep: 1
NamespaceIndentation: None
ObjCBlockIndentWidth: 2
ObjCSpaceAfterProperty: false
ObjCSpaceBeforeProtocolList: true
PenaltyBreakBeforeFirstCallParameter: 19
PenaltyBreakComment: 300
PenaltyBreakFirstLessLess: 120
PenaltyBreakString: 1000
PenaltyExcessCharacter: 1000000
PenaltyReturnTypeOnItsOwnLine: 60
PointerAlignment: Right
ReflowComments: true
SortIncludes: true
SpaceAfterCStyleCast: false
SpaceAfterTemplateKeyword: true
SpaceBeforeAssignmentOperators: true
SpaceBeforeParens: ControlStatements
SpaceInEmptyParentheses: false
SpacesBeforeTrailingComments: 1
SpacesInAngles: false
SpacesInContainerLiterals: true
SpacesInCStyleCastParentheses: false
SpacesInParentheses: false
SpacesInSquareBrackets: false
Standard: Cpp11
TabWidth: 4
UseTab: Never
...

27
.cproject
View File

@ -516,7 +516,6 @@
<buildTargets> <buildTargets>
<target name="all VERBOSE=1" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder"> <target name="all VERBOSE=1" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand> <buildCommand>make</buildCommand>
<buildArguments/>
<buildTarget>all VERBOSE=1</buildTarget> <buildTarget>all VERBOSE=1</buildTarget>
<stopOnError>true</stopOnError> <stopOnError>true</stopOnError>
<useDefaultCommand>true</useDefaultCommand> <useDefaultCommand>true</useDefaultCommand>
@ -524,7 +523,6 @@
</target> </target>
<target name="clean" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder"> <target name="clean" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand> <buildCommand>make</buildCommand>
<buildArguments/>
<buildTarget>clean</buildTarget> <buildTarget>clean</buildTarget>
<stopOnError>true</stopOnError> <stopOnError>true</stopOnError>
<useDefaultCommand>true</useDefaultCommand> <useDefaultCommand>true</useDefaultCommand>
@ -532,12 +530,35 @@
</target> </target>
<target name="all" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder"> <target name="all" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand> <buildCommand>make</buildCommand>
<buildArguments/>
<buildTarget>all</buildTarget> <buildTarget>all</buildTarget>
<stopOnError>true</stopOnError> <stopOnError>true</stopOnError>
<useDefaultCommand>true</useDefaultCommand> <useDefaultCommand>true</useDefaultCommand>
<runAllBuilders>true</runAllBuilders> <runAllBuilders>true</runAllBuilders>
</target> </target>
<target name="clangformat" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand>
<buildArguments/>
<buildTarget>clangformat</buildTarget>
<stopOnError>true</stopOnError>
<useDefaultCommand>true</useDefaultCommand>
<runAllBuilders>true</runAllBuilders>
</target>
<target name="riscv" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand>
<buildArguments/>
<buildTarget>riscv</buildTarget>
<stopOnError>true</stopOnError>
<useDefaultCommand>true</useDefaultCommand>
<runAllBuilders>true</runAllBuilders>
</target>
<target name="riscv.sc" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand>
<buildArguments/>
<buildTarget>riscv.sc</buildTarget>
<stopOnError>true</stopOnError>
<useDefaultCommand>true</useDefaultCommand>
<runAllBuilders>true</runAllBuilders>
</target>
</buildTargets> </buildTargets>
</storageModule> </storageModule>
</cproject> </cproject>

3
CMakeLists.txt
View File

@ -27,6 +27,9 @@ endif()
FIND_PACKAGE(Threads) FIND_PACKAGE(Threads)
set(PROJECT_3PARTY_DIRS external sr_report sr_signal)
include(sc-components/cmake/clang-format.cmake)
add_subdirectory(external) add_subdirectory(external)
add_subdirectory(dbt-core) add_subdirectory(dbt-core)
add_subdirectory(sc-components) add_subdirectory(sc-components)

2
dbt-core

@ -1 +1 @@
Subproject commit f23a45ab77d25ac42fd8df3e3f7206baad122c67 Subproject commit 7902b61b2cb504defdbb48baf74c7facfa7c249c

218
riscv.sc/incl/cli_options.h
View File

@ -1,21 +1,21 @@
/******************************************************************************* /*******************************************************************************
* Copyright (C) 2017, MINRES Technologies GmbH * Copyright (C) 2017, MINRES Technologies GmbH
* All rights reserved. * All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
* *
* 1. Redistributions of source code must retain the above copyright notice, * 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer. * this list of conditions and the following disclaimer.
* *
* 2. Redistributions in binary form must reproduce the above copyright notice, * 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation * this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution. * and/or other materials provided with the distribution.
* *
* 3. Neither the name of the copyright holder nor the names of its contributors * 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software * may be used to endorse or promote products derived from this software
* without specific prior written permission. * without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@ -27,7 +27,7 @@
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
* *
* Contributors: * Contributors:
* eyck@minres.com - initial API and implementation * eyck@minres.com - initial API and implementation
******************************************************************************/ ******************************************************************************/
@ -35,137 +35,139 @@
#ifndef _CLI_OPTIONS_H_ #ifndef _CLI_OPTIONS_H_
#define _CLI_OPTIONS_H_ #define _CLI_OPTIONS_H_
#include <boost/program_options.hpp> #include <boost/program_options.hpp>
#include <util/logging.h>
#include <iostream>
#include <cstdio> #include <cstdio>
#include <iostream>
#include <util/logging.h>
namespace { namespace {
const size_t ERROR_IN_COMMAND_LINE = 1; const size_t ERROR_IN_COMMAND_LINE = 1;
const size_t SUCCESS = 0; const size_t SUCCESS = 0;
const size_t ERROR_UNHANDLED_EXCEPTION = 2; const size_t ERROR_UNHANDLED_EXCEPTION = 2;
inline void enable_log_level(int level) {
inline void enable_log_level(int level){ switch (level) {
switch(level){ case 0:
case 0: logging::Logger::reporting_level() = logging::FATAL;
logging::Logger::reporting_level()= logging::FATAL; /* no break */
/* no break */ case 1:
case 1: logging::Logger::reporting_level() = logging::ERROR;
logging::Logger::reporting_level()= logging::ERROR; /* no break */
/* no break */ case 2:
case 2: logging::Logger::reporting_level() = logging::WARNING;
logging::Logger::reporting_level()= logging::WARNING; /* no break */
/* no break */ case 3:
case 3: logging::Logger::reporting_level() = logging::INFO;
logging::Logger::reporting_level()= logging::INFO; /* no break */
/* no break */ case 4:
case 4: logging::Logger::reporting_level() = logging::DEBUG;
logging::Logger::reporting_level()= logging::DEBUG; /* no break */
/* no break */ case 5:
case 5: logging::Logger::reporting_level() = logging::TRACE;
logging::Logger::reporting_level()= logging::TRACE; /* no break */
/* no break */ }
}
} }
inline void configure_default_logger(boost::program_options::variables_map& vm){ inline void configure_default_logger(boost::program_options::variables_map &vm) {
// el::Configurations defaultConf; // el::Configurations defaultConf;
// defaultConf.setToDefault(); // defaultConf.setToDefault();
// defaultConf.set(el::Level::Error, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg"); // defaultConf.set(el::Level::Error, el::ConfigurationType::Format,
// defaultConf.set(el::Level::Warning, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg"); //"%datetime{%H:%m:%s.%g} %level %msg");
// defaultConf.set(el::Level::Info, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg"); // defaultConf.set(el::Level::Warning, el::ConfigurationType::Format,
// defaultConf.set(el::Level::Debug, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg"); //"%datetime{%H:%m:%s.%g} %level %msg");
// defaultConf.set(el::Level::Trace, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg"); // defaultConf.set(el::Level::Info, el::ConfigurationType::Format,
if(vm.count("verbose")) //"%datetime{%H:%m:%s.%g} %level %msg");
enable_log_level(vm["verbose"].as<int>()); // defaultConf.set(el::Level::Debug, el::ConfigurationType::Format,
if(vm.count("log-file")) //"%datetime{%H:%m:%s.%g} %level %msg");
logging::Output2FILE::stream() = fopen(vm["log-file"].as<std::string>().c_str(), "w"); // defaultConf.set(el::Level::Trace, el::ConfigurationType::Format,
// default logger uses default configurations //"%datetime{%H:%m:%s.%g} %level %msg");
// el::Loggers::reconfigureLogger("default", defaultConf); if (vm.count("verbose")) enable_log_level(vm["verbose"].as<int>());
if (vm.count("log-file")) logging::Output2FILE::stream() = fopen(vm["log-file"].as<std::string>().c_str(), "w");
// default logger uses default configurations
// el::Loggers::reconfigureLogger("default", defaultConf);
} }
inline void configure_debugger_logger() { inline void configure_debugger_logger() {
// configure the connection logger // configure the connection logger
// el::Logger* gdbServerLogger = el::Loggers::getLogger(connection); // el::Logger* gdbServerLogger = el::Loggers::getLogger(connection);
// el::Configurations gdbServerConf; // el::Configurations gdbServerConf;
// gdbServerConf.setToDefault(); // gdbServerConf.setToDefault();
// gdbServerConf.set(el::Level::Error, el::ConfigurationType::Format, // gdbServerConf.set(el::Level::Error, el::ConfigurationType::Format,
// "%datetime{%H:%m:%s.%g} %level [%logger] %msg"); // "%datetime{%H:%m:%s.%g} %level [%logger] %msg");
// gdbServerConf.set(el::Level::Warning, el::ConfigurationType::Format, // gdbServerConf.set(el::Level::Warning, el::ConfigurationType::Format,
// "%datetime{%H:%m:%s.%g} %level [%logger] %msg"); // "%datetime{%H:%m:%s.%g} %level [%logger] %msg");
// gdbServerConf.set(el::Level::Info, el::ConfigurationType::Format, // gdbServerConf.set(el::Level::Info, el::ConfigurationType::Format,
// "%datetime{%H:%m:%s.%g} %level [%logger] %msg"); // "%datetime{%H:%m:%s.%g} %level [%logger] %msg");
// gdbServerConf.set(el::Level::Debug, el::ConfigurationType::Format, // gdbServerConf.set(el::Level::Debug, el::ConfigurationType::Format,
// "%datetime{%H:%m:%s.%g} %level [%logger] %msg"); // "%datetime{%H:%m:%s.%g} %level [%logger] %msg");
// gdbServerConf.set(el::Level::Trace, el::ConfigurationType::Format, // gdbServerConf.set(el::Level::Trace, el::ConfigurationType::Format,
// "%datetime{%H:%m:%s.%g} %level [%logger] %msg"); // "%datetime{%H:%m:%s.%g} %level [%logger] %msg");
// enable_log_level(gdbServerConf, 5); // enable_log_level(gdbServerConf, 5);
// gdbServerLogger->configure(gdbServerConf); // gdbServerLogger->configure(gdbServerConf);
} }
inline void configure_disass_logger(boost::program_options::variables_map& vm) { inline void configure_disass_logger(boost::program_options::variables_map &vm) {
// el::Logger* disassLogger = el::Loggers::getLogger(disass); // el::Logger* disassLogger = el::Loggers::getLogger(disass);
// el::Configurations disassConf; // el::Configurations disassConf;
// if(vm.count(disass)){ // if(vm.count(disass)){
// auto file_name=vm[disass].as<std::string>(); // auto file_name=vm[disass].as<std::string>();
// disassConf.setToDefault(); // disassConf.setToDefault();
// if (file_name.length() > 0) { // if (file_name.length() > 0) {
// disassConf.set(el::Level::Global, el::ConfigurationType::ToFile, // disassConf.set(el::Level::Global, el::ConfigurationType::ToFile,
// std::string("true")); // std::string("true"));
// disassConf.set(el::Level::Global, // disassConf.set(el::Level::Global,
// el::ConfigurationType::ToStandardOutput, std::string("false")); // el::ConfigurationType::ToStandardOutput,
// disassConf.set(el::Level::Global, el::ConfigurationType::Format, // std::string("false"));
// std::string("%msg")); // disassConf.set(el::Level::Global, el::ConfigurationType::Format,
// disassConf.set(el::Level::Global, el::ConfigurationType::Filename, // std::string("%msg"));
// file_name); // disassConf.set(el::Level::Global,
// std::ofstream str(file_name); // just to clear the file // el::ConfigurationType::Filename,
// } else { // file_name);
// disassConf.set(el::Level::Global, el::ConfigurationType::Format, // std::ofstream str(file_name); // just to clear the file
// "%datetime{%H:%m:%s.%g} [%logger] %msg"); // } else {
// } // disassConf.set(el::Level::Global, el::ConfigurationType::Format,
// } else { // "%datetime{%H:%m:%s.%g} [%logger] %msg");
// enable_log_level(disassConf, 0); // }
// } // } else {
// disassLogger->configure(disassConf); // enable_log_level(disassConf, 0);
// }
// disassLogger->configure(disassConf);
} }
} // namespace } // namespace
inline int parse_cli_options(boost::program_options::variables_map& vm, int argc, char *argv[]){ inline int parse_cli_options(boost::program_options::variables_map &vm, int argc, char *argv[]) {
namespace po = boost::program_options; namespace po = boost::program_options;
po::options_description desc("Options"); po::options_description desc("Options");
desc.add_options() desc.add_options()("help,h", "Print help message")("verbose,v", po::value<int>()->implicit_value(0),
("help,h", "Print help message") "Sets logging verbosity")("vmodule", po::value<std::string>(),
("verbose,v", po::value<int>()->implicit_value(0), "Sets logging verbosity") "Defines the module(s) to be logged")(
("vmodule", po::value<std::string>(),"Defines the module(s) to be logged") "logging-flags", po::value<int>(), "Sets logging flag(s).")("log-file", po::value<std::string>(),
("logging-flags", po::value<int>(),"Sets logging flag(s).") "Sets default log file.")(
("log-file", po::value<std::string>(),"Sets default log file.") "disass,d", po::value<std::string>()->implicit_value(""),
("disass,d", po::value<std::string>()->implicit_value(""),"Enables disassembly") "Enables disassembly")("elf,l", po::value<std::vector<std::string>>(), "ELF file(s) to load")(
("elf,l", po::value< std::vector<std::string> >(), "ELF file(s) to load") "gdb-port,g", po::value<unsigned>(), "enable gdb server and specify port to use")(
("gdb-port,g", po::value<unsigned>(), "enable gdb server and specify port to use") "input,i", po::value<std::string>(), "the elf file to load (instead of hex files)")(
("input,i", po::value<std::string>(), "the elf file to load (instead of hex files)") "dump-ir", "dump the intermediate representation")("cycles,c", po::value<int64_t>()->default_value(-1),
("dump-ir", "dump the intermediate representation") "number of cycles to run")(
("cycles,c", po::value<int64_t>()->default_value(-1), "number of cycles to run") "systemc,s", "Run as SystemC simulation")("time", po::value<int>(), "SystemC siimulation time in ms")(
("systemc,s", "Run as SystemC simulation") "reset,r", po::value<std::string>(), "reset address")(
("time", po::value<int>(), "SystemC siimulation time in ms") "trace", po::value<uint8_t>(), "enable tracing, or cmbintation of 1=signals and 2=TX text, 4=TX "
("reset,r", po::value<std::string>(), "reset address") "compressed text, 6=TX in SQLite")("mem,m", po::value<std::string>(),
("trace", po::value<uint8_t>(), "enable tracing, or cmbintation of 1=signals and 2=TX text, 4=TX compressed text, 6=TX in SQLite")\ "the memory input file")("rv64", "run RV64");
("mem,m", po::value<std::string>(), "the memory input file")
("rv64", "run RV64");
try { try {
po::store(po::parse_command_line(argc, argv, desc), vm); // can throw po::store(po::parse_command_line(argc, argv, desc), vm); // can throw
// --help option // --help option
if ( vm.count("help") ){ if (vm.count("help")) {
std::cout << "DBT-RISE-RiscV" << std::endl << desc << std::endl; std::cout << "DBT-RISE-RiscV" << std::endl << desc << std::endl;
return SUCCESS; return SUCCESS;
} }
po::notify(vm); // throws on error, so do after help in case po::notify(vm); // throws on error, so do after help in case
} catch(po::error& e){ } catch (po::error &e) {
// there are problems // there are problems
std::cerr << "ERROR: " << e.what() << std::endl << std::endl; std::cerr << "ERROR: " << e.what() << std::endl << std::endl;
std::cerr << desc << std::endl; std::cerr << desc << std::endl;
return ERROR_IN_COMMAND_LINE; return ERROR_IN_COMMAND_LINE;
} }
return SUCCESS; return SUCCESS;
} }
#endif /* _CLI_OPTIONS_H_ */ #endif /* _CLI_OPTIONS_H_ */

12
riscv.sc/incl/sysc/SiFive/core_complex.h
View File

@ -1,4 +1,4 @@
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH // Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved. // All rights reserved.
// //
@ -37,25 +37,21 @@
#ifndef _SYSC_SIFIVE_FE310_H_ #ifndef _SYSC_SIFIVE_FE310_H_
#define _SYSC_SIFIVE_FE310_H_ #define _SYSC_SIFIVE_FE310_H_
#include <iss/arch/rv32imac.h>
#include <iss/arch/riscv_hart_msu_vp.h> #include <iss/arch/riscv_hart_msu_vp.h>
#include <tlm> #include <iss/arch/rv32imac.h>
#include <sysc/utilities.h> #include <sysc/utilities.h>
#include <tlm>
namespace sysc { namespace sysc {
namespace SiFive { namespace SiFive {
class core_complex: class core_complex : public iss::arch::riscv_hart_msu_vp<iss::arch::rv32imac>, public sc_core::sc_module {
public iss::arch::riscv_hart_msu_vp<iss::arch::rv32imac>,
public sc_core::sc_module {
public: public:
tlm::tlm_initiator_socket<32> initiator; tlm::tlm_initiator_socket<32> initiator;
sc_core::sc_in<bool> rst_i; sc_core::sc_in<bool> rst_i;
core_complex(sc_core::sc_module_name name); core_complex(sc_core::sc_module_name name);
virtual ~core_complex(); virtual ~core_complex();
}; };
} /* namespace SiFive */ } /* namespace SiFive */

3
riscv.sc/incl/sysc/SiFive/gen/e300_plat_t.h
View File

@ -1,6 +1,7 @@
#ifndef _E300_PLAT_MAP_H_ #ifndef _E300_PLAT_MAP_H_
#define _E300_PLAT_MAP_H_ #define _E300_PLAT_MAP_H_
// need double braces, see https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191 // need double braces, see
// https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191
const std::array<sysc::target_memory_map_entry<32>, 4> e300_plat_map = {{ const std::array<sysc::target_memory_map_entry<32>, 4> e300_plat_map = {{
{&i_plic, 0xc000000, 0x1000}, {&i_plic, 0xc000000, 0x1000},
{&i_gpio, 0x10012000, 0x1000}, {&i_gpio, 0x10012000, 0x1000},

77
riscv.sc/incl/sysc/SiFive/gen/gpio_regs.h
View File

@ -36,53 +36,50 @@
#ifndef _GPIO_REGS_H_ #ifndef _GPIO_REGS_H_
#define _GPIO_REGS_H_ #define _GPIO_REGS_H_
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include <sysc/register.h> #include <sysc/register.h>
#include <sysc/tlm_target.h> #include <sysc/tlm_target.h>
#include <sysc/utilities.h>
#include <util/bit_field.h>
namespace sysc { namespace sysc {
class gpio_regs : class gpio_regs : public sc_core::sc_module, public sysc::resetable {
public sc_core::sc_module,
public sysc::resetable
{
protected: protected:
// storage declarations // storage declarations
uint32_t r_value; uint32_t r_value;
uint32_t r_input_en; uint32_t r_input_en;
uint32_t r_output_en; uint32_t r_output_en;
uint32_t r_port; uint32_t r_port;
uint32_t r_pue; uint32_t r_pue;
uint32_t r_ds; uint32_t r_ds;
uint32_t r_rise_ie; uint32_t r_rise_ie;
uint32_t r_rise_ip; uint32_t r_rise_ip;
uint32_t r_fall_ie; uint32_t r_fall_ie;
uint32_t r_fall_ip; uint32_t r_fall_ip;
uint32_t r_high_ie; uint32_t r_high_ie;
uint32_t r_high_ip; uint32_t r_high_ip;
uint32_t r_low_ie; uint32_t r_low_ie;
uint32_t r_low_ip; uint32_t r_low_ip;
uint32_t r_iof_en; uint32_t r_iof_en;
uint32_t r_iof_sel; uint32_t r_iof_sel;
uint32_t r_out_xor; uint32_t r_out_xor;
// register declarations // register declarations
sysc::sc_register<uint32_t> value; sysc::sc_register<uint32_t> value;
sysc::sc_register<uint32_t> input_en; sysc::sc_register<uint32_t> input_en;
@ -101,12 +98,11 @@ protected:
sysc::sc_register<uint32_t> iof_en; sysc::sc_register<uint32_t> iof_en;
sysc::sc_register<uint32_t> iof_sel; sysc::sc_register<uint32_t> iof_sel;
sysc::sc_register<uint32_t> out_xor; sysc::sc_register<uint32_t> out_xor;
public: public:
gpio_regs(sc_core::sc_module_name nm); gpio_regs(sc_core::sc_module_name nm);
template<unsigned BUSWIDTH=32> template <unsigned BUSWIDTH = 32> void registerResources(sysc::tlm_target<BUSWIDTH> &target);
void registerResources(sysc::tlm_target<BUSWIDTH>& target);
}; };
} }
////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////
@ -114,29 +110,14 @@ public:
////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////
inline sysc::gpio_regs::gpio_regs(sc_core::sc_module_name nm) inline sysc::gpio_regs::gpio_regs(sc_core::sc_module_name nm)
: sc_core::sc_module(nm) : sc_core::sc_module(nm), NAMED(value, r_value, 0, *this), NAMED(input_en, r_input_en, 0, *this),
, NAMED(value, r_value, 0, *this) NAMED(output_en, r_output_en, 0, *this), NAMED(port, r_port, 0, *this), NAMED(pue, r_pue, 0, *this),
, NAMED(input_en, r_input_en, 0, *this) NAMED(ds, r_ds, 0, *this), NAMED(rise_ie, r_rise_ie, 0, *this), NAMED(rise_ip, r_rise_ip, 0, *this),
, NAMED(output_en, r_output_en, 0, *this) NAMED(fall_ie, r_fall_ie, 0, *this), NAMED(fall_ip, r_fall_ip, 0, *this), NAMED(high_ie, r_high_ie, 0, *this),
, NAMED(port, r_port, 0, *this) NAMED(high_ip, r_high_ip, 0, *this), NAMED(low_ie, r_low_ie, 0, *this), NAMED(low_ip, r_low_ip, 0, *this),
, NAMED(pue, r_pue, 0, *this) NAMED(iof_en, r_iof_en, 0, *this), NAMED(iof_sel, r_iof_sel, 0, *this), NAMED(out_xor, r_out_xor, 0, *this) {}
, NAMED(ds, r_ds, 0, *this)
, NAMED(rise_ie, r_rise_ie, 0, *this)
, NAMED(rise_ip, r_rise_ip, 0, *this)
, NAMED(fall_ie, r_fall_ie, 0, *this)
, NAMED(fall_ip, r_fall_ip, 0, *this)
, NAMED(high_ie, r_high_ie, 0, *this)
, NAMED(high_ip, r_high_ip, 0, *this)
, NAMED(low_ie, r_low_ie, 0, *this)
, NAMED(low_ip, r_low_ip, 0, *this)
, NAMED(iof_en, r_iof_en, 0, *this)
, NAMED(iof_sel, r_iof_sel, 0, *this)
, NAMED(out_xor, r_out_xor, 0, *this)
{
}
template<unsigned BUSWIDTH> template <unsigned BUSWIDTH> inline void sysc::gpio_regs::registerResources(sysc::tlm_target<BUSWIDTH> &target) {
inline void sysc::gpio_regs::registerResources(sysc::tlm_target<BUSWIDTH>& target) {
target.addResource(value, 0x0UL); target.addResource(value, 0x0UL);
target.addResource(input_en, 0x4UL); target.addResource(input_en, 0x4UL);
target.addResource(output_en, 0x8UL); target.addResource(output_en, 0x8UL);

44
riscv.sc/incl/sysc/SiFive/gen/plic_regs.h
View File

@ -36,46 +36,42 @@
#ifndef _PLIC_REGS_H_ #ifndef _PLIC_REGS_H_
#define _PLIC_REGS_H_ #define _PLIC_REGS_H_
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include <sysc/register.h> #include <sysc/register.h>
#include <sysc/tlm_target.h> #include <sysc/tlm_target.h>
#include <sysc/utilities.h>
#include <util/bit_field.h>
namespace sysc { namespace sysc {
class plic_regs : class plic_regs : public sc_core::sc_module, public sysc::resetable {
public sc_core::sc_module,
public sysc::resetable
{
protected: protected:
// storage declarations // storage declarations
BEGIN_BF_DECL(priority_t, uint32_t); BEGIN_BF_DECL(priority_t, uint32_t);
BF_FIELD(priority, 0, 3); BF_FIELD(priority, 0, 3);
END_BF_DECL() ; END_BF_DECL();
std::array<priority_t, 255> r_priority; std::array<priority_t, 255> r_priority;
uint32_t r_pending; uint32_t r_pending;
uint32_t r_enabled; uint32_t r_enabled;
BEGIN_BF_DECL(threshold_t, uint32_t); BEGIN_BF_DECL(threshold_t, uint32_t);
BF_FIELD(threshold, 0, 3); BF_FIELD(threshold, 0, 3);
END_BF_DECL() r_threshold; END_BF_DECL() r_threshold;
uint32_t r_claim_complete; uint32_t r_claim_complete;
// register declarations // register declarations
sysc::sc_register_indexed<priority_t, 255> priority; sysc::sc_register_indexed<priority_t, 255> priority;
sysc::sc_register<uint32_t> pending; sysc::sc_register<uint32_t> pending;
sysc::sc_register<uint32_t> enabled; sysc::sc_register<uint32_t> enabled;
sysc::sc_register<threshold_t> threshold; sysc::sc_register<threshold_t> threshold;
sysc::sc_register<uint32_t> claim_complete; sysc::sc_register<uint32_t> claim_complete;
public: public:
plic_regs(sc_core::sc_module_name nm); plic_regs(sc_core::sc_module_name nm);
template<unsigned BUSWIDTH=32> template <unsigned BUSWIDTH = 32> void registerResources(sysc::tlm_target<BUSWIDTH> &target);
void registerResources(sysc::tlm_target<BUSWIDTH>& target);
}; };
} }
////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////
@ -83,17 +79,11 @@ public:
////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////
inline sysc::plic_regs::plic_regs(sc_core::sc_module_name nm) inline sysc::plic_regs::plic_regs(sc_core::sc_module_name nm)
: sc_core::sc_module(nm) : sc_core::sc_module(nm), NAMED(priority, r_priority, 0, *this), NAMED(pending, r_pending, 0, *this),
, NAMED(priority, r_priority, 0, *this) NAMED(enabled, r_enabled, 0, *this), NAMED(threshold, r_threshold, 0, *this),
, NAMED(pending, r_pending, 0, *this) NAMED(claim_complete, r_claim_complete, 0, *this) {}
, NAMED(enabled, r_enabled, 0, *this)
, NAMED(threshold, r_threshold, 0, *this)
, NAMED(claim_complete, r_claim_complete, 0, *this)
{
}
template<unsigned BUSWIDTH> template <unsigned BUSWIDTH> inline void sysc::plic_regs::registerResources(sysc::tlm_target<BUSWIDTH> &target) {
inline void sysc::plic_regs::registerResources(sysc::tlm_target<BUSWIDTH>& target) {
target.addResource(priority, 0x4UL); target.addResource(priority, 0x4UL);
target.addResource(pending, 0x1000UL); target.addResource(pending, 0x1000UL);
target.addResource(enabled, 0x2000UL); target.addResource(enabled, 0x2000UL);

136
riscv.sc/incl/sysc/SiFive/gen/spi_regs.h
View File

@ -36,96 +36,93 @@
#ifndef _SPI_REGS_H_ #ifndef _SPI_REGS_H_
#define _SPI_REGS_H_ #define _SPI_REGS_H_
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include <sysc/register.h> #include <sysc/register.h>
#include <sysc/tlm_target.h> #include <sysc/tlm_target.h>
#include <sysc/utilities.h>
#include <util/bit_field.h>
namespace sysc { namespace sysc {
class spi_regs : class spi_regs : public sc_core::sc_module, public sysc::resetable {
public sc_core::sc_module,
public sysc::resetable
{
protected: protected:
// storage declarations // storage declarations
BEGIN_BF_DECL(sckdiv_t, uint32_t); BEGIN_BF_DECL(sckdiv_t, uint32_t);
BF_FIELD(div, 0, 12); BF_FIELD(div, 0, 12);
END_BF_DECL() r_sckdiv; END_BF_DECL() r_sckdiv;
BEGIN_BF_DECL(sckmode_t, uint32_t); BEGIN_BF_DECL(sckmode_t, uint32_t);
BF_FIELD(pha, 0, 1); BF_FIELD(pha, 0, 1);
BF_FIELD(pol, 1, 1); BF_FIELD(pol, 1, 1);
END_BF_DECL() r_sckmode; END_BF_DECL() r_sckmode;
uint32_t r_csid; uint32_t r_csid;
uint32_t r_csdef; uint32_t r_csdef;
BEGIN_BF_DECL(csmode_t, uint32_t); BEGIN_BF_DECL(csmode_t, uint32_t);
BF_FIELD(mode, 0, 2); BF_FIELD(mode, 0, 2);
END_BF_DECL() r_csmode; END_BF_DECL() r_csmode;
BEGIN_BF_DECL(delay0_t, uint32_t); BEGIN_BF_DECL(delay0_t, uint32_t);
BF_FIELD(cssck, 0, 8); BF_FIELD(cssck, 0, 8);
BF_FIELD(sckcs, 16, 8); BF_FIELD(sckcs, 16, 8);
END_BF_DECL() r_delay0; END_BF_DECL() r_delay0;
BEGIN_BF_DECL(delay1_t, uint32_t); BEGIN_BF_DECL(delay1_t, uint32_t);
BF_FIELD(intercs, 0, 16); BF_FIELD(intercs, 0, 16);
BF_FIELD(interxfr, 16, 8); BF_FIELD(interxfr, 16, 8);
END_BF_DECL() r_delay1; END_BF_DECL() r_delay1;
BEGIN_BF_DECL(fmt_t, uint32_t); BEGIN_BF_DECL(fmt_t, uint32_t);
BF_FIELD(proto, 0, 2); BF_FIELD(proto, 0, 2);
BF_FIELD(endian, 2, 1); BF_FIELD(endian, 2, 1);
BF_FIELD(dir, 3, 1); BF_FIELD(dir, 3, 1);
BF_FIELD(len, 16, 4); BF_FIELD(len, 16, 4);
END_BF_DECL() r_fmt; END_BF_DECL() r_fmt;
BEGIN_BF_DECL(txdata_t, uint32_t); BEGIN_BF_DECL(txdata_t, uint32_t);
BF_FIELD(data, 0, 8); BF_FIELD(data, 0, 8);
BF_FIELD(full, 31, 1); BF_FIELD(full, 31, 1);
END_BF_DECL() r_txdata; END_BF_DECL() r_txdata;
BEGIN_BF_DECL(rxdata_t, uint32_t); BEGIN_BF_DECL(rxdata_t, uint32_t);
BF_FIELD(data, 0, 8); BF_FIELD(data, 0, 8);
BF_FIELD(empty, 31, 1); BF_FIELD(empty, 31, 1);
END_BF_DECL() r_rxdata; END_BF_DECL() r_rxdata;
BEGIN_BF_DECL(txmark_t, uint32_t); BEGIN_BF_DECL(txmark_t, uint32_t);
BF_FIELD(txmark, 0, 3); BF_FIELD(txmark, 0, 3);
END_BF_DECL() r_txmark; END_BF_DECL() r_txmark;
BEGIN_BF_DECL(rxmark_t, uint32_t); BEGIN_BF_DECL(rxmark_t, uint32_t);
BF_FIELD(rxmark, 0, 3); BF_FIELD(rxmark, 0, 3);
END_BF_DECL() r_rxmark; END_BF_DECL() r_rxmark;
BEGIN_BF_DECL(fctrl_t, uint32_t); BEGIN_BF_DECL(fctrl_t, uint32_t);
BF_FIELD(en, 0, 1); BF_FIELD(en, 0, 1);
END_BF_DECL() r_fctrl; END_BF_DECL() r_fctrl;
BEGIN_BF_DECL(ffmt_t, uint32_t); BEGIN_BF_DECL(ffmt_t, uint32_t);
BF_FIELD(cmd_en, 0, 1); BF_FIELD(cmd_en, 0, 1);
BF_FIELD(addr_len, 1, 2); BF_FIELD(addr_len, 1, 2);
BF_FIELD(pad_cnt, 3, 4); BF_FIELD(pad_cnt, 3, 4);
BF_FIELD(cmd_proto, 7, 2); BF_FIELD(cmd_proto, 7, 2);
BF_FIELD(addr_proto, 9, 2); BF_FIELD(addr_proto, 9, 2);
BF_FIELD(data_proto, 11, 2); BF_FIELD(data_proto, 11, 2);
BF_FIELD(cmd_code, 16, 8); BF_FIELD(cmd_code, 16, 8);
BF_FIELD(pad_code, 24, 8); BF_FIELD(pad_code, 24, 8);
END_BF_DECL() r_ffmt; END_BF_DECL() r_ffmt;
BEGIN_BF_DECL(ie_t, uint32_t); BEGIN_BF_DECL(ie_t, uint32_t);
BF_FIELD(txwm, 0, 1); BF_FIELD(txwm, 0, 1);
BF_FIELD(rxwm, 1, 1); BF_FIELD(rxwm, 1, 1);
END_BF_DECL() r_ie; END_BF_DECL() r_ie;
BEGIN_BF_DECL(ip_t, uint32_t); BEGIN_BF_DECL(ip_t, uint32_t);
BF_FIELD(txwm, 0, 1); BF_FIELD(txwm, 0, 1);
BF_FIELD(rxwm, 1, 1); BF_FIELD(rxwm, 1, 1);
END_BF_DECL() r_ip; END_BF_DECL() r_ip;
// register declarations // register declarations
sysc::sc_register<sckdiv_t> sckdiv; sysc::sc_register<sckdiv_t> sckdiv;
sysc::sc_register<sckmode_t> sckmode; sysc::sc_register<sckmode_t> sckmode;
@ -143,12 +140,11 @@ protected:
sysc::sc_register<ffmt_t> ffmt; sysc::sc_register<ffmt_t> ffmt;
sysc::sc_register<ie_t> ie; sysc::sc_register<ie_t> ie;
sysc::sc_register<ip_t> ip; sysc::sc_register<ip_t> ip;
public: public:
spi_regs(sc_core::sc_module_name nm); spi_regs(sc_core::sc_module_name nm);
template<unsigned BUSWIDTH=32> template <unsigned BUSWIDTH = 32> void registerResources(sysc::tlm_target<BUSWIDTH> &target);
void registerResources(sysc::tlm_target<BUSWIDTH>& target);
}; };
} }
////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////
@ -156,28 +152,14 @@ public:
////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////
inline sysc::spi_regs::spi_regs(sc_core::sc_module_name nm) inline sysc::spi_regs::spi_regs(sc_core::sc_module_name nm)
: sc_core::sc_module(nm) : sc_core::sc_module(nm), NAMED(sckdiv, r_sckdiv, 0, *this), NAMED(sckmode, r_sckmode, 0, *this),
, NAMED(sckdiv, r_sckdiv, 0, *this) NAMED(csid, r_csid, 0, *this), NAMED(csdef, r_csdef, 0, *this), NAMED(csmode, r_csmode, 0, *this),
, NAMED(sckmode, r_sckmode, 0, *this) NAMED(delay0, r_delay0, 0, *this), NAMED(delay1, r_delay1, 0, *this), NAMED(fmt, r_fmt, 0, *this),
, NAMED(csid, r_csid, 0, *this) NAMED(txdata, r_txdata, 0, *this), NAMED(rxdata, r_rxdata, 0, *this), NAMED(txmark, r_txmark, 0, *this),
, NAMED(csdef, r_csdef, 0, *this) NAMED(rxmark, r_rxmark, 0, *this), NAMED(fctrl, r_fctrl, 0, *this), NAMED(ffmt, r_ffmt, 0, *this),
, NAMED(csmode, r_csmode, 0, *this) NAMED(ie, r_ie, 0, *this), NAMED(ip, r_ip, 0, *this) {}
, NAMED(delay0, r_delay0, 0, *this)
, NAMED(delay1, r_delay1, 0, *this)
, NAMED(fmt, r_fmt, 0, *this)
, NAMED(txdata, r_txdata, 0, *this)
, NAMED(rxdata, r_rxdata, 0, *this)
, NAMED(txmark, r_txmark, 0, *this)
, NAMED(rxmark, r_rxmark, 0, *this)
, NAMED(fctrl, r_fctrl, 0, *this)
, NAMED(ffmt, r_ffmt, 0, *this)
, NAMED(ie, r_ie, 0, *this)
, NAMED(ip, r_ip, 0, *this)
{
}
template<unsigned BUSWIDTH> template <unsigned BUSWIDTH> inline void sysc::spi_regs::registerResources(sysc::tlm_target<BUSWIDTH> &target) {
inline void sysc::spi_regs::registerResources(sysc::tlm_target<BUSWIDTH>& target) {
target.addResource(sckdiv, 0x0UL); target.addResource(sckdiv, 0x0UL);
target.addResource(sckmode, 0x4UL); target.addResource(sckmode, 0x4UL);
target.addResource(csid, 0x10UL); target.addResource(csid, 0x10UL);

76
riscv.sc/incl/sysc/SiFive/gen/uart_regs.h
View File

@ -36,56 +36,53 @@
#ifndef _UART_REGS_H_ #ifndef _UART_REGS_H_
#define _UART_REGS_H_ #define _UART_REGS_H_
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include <sysc/register.h> #include <sysc/register.h>
#include <sysc/tlm_target.h> #include <sysc/tlm_target.h>
#include <sysc/utilities.h>
#include <util/bit_field.h>
namespace sysc { namespace sysc {
class uart_regs : class uart_regs : public sc_core::sc_module, public sysc::resetable {
public sc_core::sc_module,
public sysc::resetable
{
protected: protected:
// storage declarations // storage declarations
BEGIN_BF_DECL(txdata_t, uint32_t); BEGIN_BF_DECL(txdata_t, uint32_t);
BF_FIELD(data, 0, 8); BF_FIELD(data, 0, 8);
BF_FIELD(full, 31, 1); BF_FIELD(full, 31, 1);
END_BF_DECL() r_txdata; END_BF_DECL() r_txdata;
BEGIN_BF_DECL(rxdata_t, uint32_t); BEGIN_BF_DECL(rxdata_t, uint32_t);
BF_FIELD(data, 0, 8); BF_FIELD(data, 0, 8);
BF_FIELD(empty, 31, 1); BF_FIELD(empty, 31, 1);
END_BF_DECL() r_rxdata; END_BF_DECL() r_rxdata;
BEGIN_BF_DECL(txctrl_t, uint32_t); BEGIN_BF_DECL(txctrl_t, uint32_t);
BF_FIELD(txen, 0, 1); BF_FIELD(txen, 0, 1);
BF_FIELD(nstop, 1, 1); BF_FIELD(nstop, 1, 1);
BF_FIELD(reserved, 2, 14); BF_FIELD(reserved, 2, 14);
BF_FIELD(txcnt, 16, 3); BF_FIELD(txcnt, 16, 3);
END_BF_DECL() r_txctrl; END_BF_DECL() r_txctrl;
BEGIN_BF_DECL(rxctrl_t, uint32_t); BEGIN_BF_DECL(rxctrl_t, uint32_t);
BF_FIELD(rxen, 0, 1); BF_FIELD(rxen, 0, 1);
BF_FIELD(reserved, 1, 15); BF_FIELD(reserved, 1, 15);
BF_FIELD(rxcnt, 16, 3); BF_FIELD(rxcnt, 16, 3);
END_BF_DECL() r_rxctrl; END_BF_DECL() r_rxctrl;
BEGIN_BF_DECL(ie_t, uint32_t); BEGIN_BF_DECL(ie_t, uint32_t);
BF_FIELD(txwm, 0, 1); BF_FIELD(txwm, 0, 1);
BF_FIELD(rxwm, 1, 1); BF_FIELD(rxwm, 1, 1);
END_BF_DECL() r_ie; END_BF_DECL() r_ie;
BEGIN_BF_DECL(ip_t, uint32_t); BEGIN_BF_DECL(ip_t, uint32_t);
BF_FIELD(txwm, 0, 1); BF_FIELD(txwm, 0, 1);
BF_FIELD(rxwm, 1, 1); BF_FIELD(rxwm, 1, 1);
END_BF_DECL() r_ip; END_BF_DECL() r_ip;
BEGIN_BF_DECL(div_t, uint32_t); BEGIN_BF_DECL(div_t, uint32_t);
BF_FIELD(div, 0, 16); BF_FIELD(div, 0, 16);
END_BF_DECL() r_div; END_BF_DECL() r_div;
// register declarations // register declarations
sysc::sc_register<txdata_t> txdata; sysc::sc_register<txdata_t> txdata;
sysc::sc_register<rxdata_t> rxdata; sysc::sc_register<rxdata_t> rxdata;
@ -94,12 +91,11 @@ protected:
sysc::sc_register<ie_t> ie; sysc::sc_register<ie_t> ie;
sysc::sc_register<ip_t> ip; sysc::sc_register<ip_t> ip;
sysc::sc_register<div_t> div; sysc::sc_register<div_t> div;
public: public:
uart_regs(sc_core::sc_module_name nm); uart_regs(sc_core::sc_module_name nm);
template<unsigned BUSWIDTH=32> template <unsigned BUSWIDTH = 32> void registerResources(sysc::tlm_target<BUSWIDTH> &target);
void registerResources(sysc::tlm_target<BUSWIDTH>& target);
}; };
} }
////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////
@ -107,19 +103,11 @@ public:
////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////
inline sysc::uart_regs::uart_regs(sc_core::sc_module_name nm) inline sysc::uart_regs::uart_regs(sc_core::sc_module_name nm)
: sc_core::sc_module(nm) : sc_core::sc_module(nm), NAMED(txdata, r_txdata, 0, *this), NAMED(rxdata, r_rxdata, 0, *this),
, NAMED(txdata, r_txdata, 0, *this) NAMED(txctrl, r_txctrl, 0, *this), NAMED(rxctrl, r_rxctrl, 0, *this), NAMED(ie, r_ie, 0, *this),
, NAMED(rxdata, r_rxdata, 0, *this) NAMED(ip, r_ip, 0, *this), NAMED(div, r_div, 0, *this) {}
, NAMED(txctrl, r_txctrl, 0, *this)
, NAMED(rxctrl, r_rxctrl, 0, *this)
, NAMED(ie, r_ie, 0, *this)
, NAMED(ip, r_ip, 0, *this)
, NAMED(div, r_div, 0, *this)
{
}
template<unsigned BUSWIDTH> template <unsigned BUSWIDTH> inline void sysc::uart_regs::registerResources(sysc::tlm_target<BUSWIDTH> &target) {
inline void sysc::uart_regs::registerResources(sysc::tlm_target<BUSWIDTH>& target) {
target.addResource(txdata, 0x0UL); target.addResource(txdata, 0x0UL);
target.addResource(rxdata, 0x4UL); target.addResource(rxdata, 0x4UL);
target.addResource(txctrl, 0x8UL); target.addResource(txctrl, 0x8UL);

11
riscv.sc/incl/sysc/SiFive/gpio.h
View File

@ -1,12 +1,12 @@
/******************************************************************************* /*******************************************************************************
* Copyright 2017 eyck@minres.com * Copyright 2017 eyck@minres.com
* *
* Licensed under the Apache License, Version 2.0 (the "License"); you may not * Licensed under the Apache License, Version 2.0 (the "License"); you may not
* use this file except in compliance with the License. You may obtain a copy * use this file except in compliance with the License. You may obtain a copy
* of the License at * of the License at
* *
* http://www.apache.org/licenses/LICENSE-2.0 * http://www.apache.org/licenses/LICENSE-2.0
* *
* Unless required by applicable law or agreed to in writing, software * Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
@ -23,13 +23,14 @@ namespace sysc {
class gpio_regs; class gpio_regs;
class gpio: public sc_core::sc_module, public tlm_target<> { class gpio : public sc_core::sc_module, public tlm_target<> {
public: public:
SC_HAS_PROCESS(gpio); SC_HAS_PROCESS(gpio);
sc_core::sc_in<sc_core::sc_time> clk_i; sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i; sc_core::sc_in<bool> rst_i;
gpio(sc_core::sc_module_name nm); gpio(sc_core::sc_module_name nm);
virtual ~gpio(); virtual ~gpio();
protected: protected:
void clock_cb(); void clock_cb();
void reset_cb(); void reset_cb();

18
riscv.sc/incl/sysc/SiFive/platform.h
View File

@ -1,12 +1,12 @@
/******************************************************************************* /*******************************************************************************
* Copyright 2017 eyck@minres.com * Copyright 2017 eyck@minres.com
* *
* Licensed under the Apache License, Version 2.0 (the "License"); you may not * Licensed under the Apache License, Version 2.0 (the "License"); you may not
* use this file except in compliance with the License. You may obtain a copy * use this file except in compliance with the License. You may obtain a copy
* of the License at * of the License at
* *
* http://www.apache.org/licenses/LICENSE-2.0 * http://www.apache.org/licenses/LICENSE-2.0
* *
* Unless required by applicable law or agreed to in writing, software * Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
@ -23,21 +23,20 @@
#ifndef SIMPLESYSTEM_H_ #ifndef SIMPLESYSTEM_H_
#define SIMPLESYSTEM_H_ #define SIMPLESYSTEM_H_
#include "uart.h"
#include "spi.h"
#include "gpio.h" #include "gpio.h"
#include "plic.h" #include "plic.h"
#include "spi.h"
#include "uart.h"
#include <sysc/router.h>
#include <sysc/kernel/sc_module.h>
#include <array> #include <array>
#include <sysc/kernel/sc_module.h>
#include <sysc/router.h>
#include "core_complex.h" #include "core_complex.h"
namespace sysc { namespace sysc {
class platform: public sc_core::sc_module { class platform : public sc_core::sc_module {
public: public:
SC_HAS_PROCESS(platform); SC_HAS_PROCESS(platform);
@ -51,6 +50,7 @@ public:
sc_core::sc_signal<bool> s_rst; sc_core::sc_signal<bool> s_rst;
platform(sc_core::sc_module_name nm); platform(sc_core::sc_module_name nm);
protected: protected:
void gen_reset(); void gen_reset();

11
riscv.sc/incl/sysc/SiFive/plic.h
View File

@ -1,12 +1,12 @@
/******************************************************************************* /*******************************************************************************
* Copyright 2017 eyck@minres.com * Copyright 2017 eyck@minres.com
* *
* Licensed under the Apache License, Version 2.0 (the "License"); you may not * Licensed under the Apache License, Version 2.0 (the "License"); you may not
* use this file except in compliance with the License. You may obtain a copy * use this file except in compliance with the License. You may obtain a copy
* of the License at * of the License at
* *
* http://www.apache.org/licenses/LICENSE-2.0 * http://www.apache.org/licenses/LICENSE-2.0
* *
* Unless required by applicable law or agreed to in writing, software * Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
@ -23,13 +23,14 @@ namespace sysc {
class plic_regs; class plic_regs;
class plic: public sc_core::sc_module, public tlm_target<> { class plic : public sc_core::sc_module, public tlm_target<> {
public: public:
SC_HAS_PROCESS(plic); SC_HAS_PROCESS(plic);
sc_core::sc_in<sc_core::sc_time> clk_i; sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i; sc_core::sc_in<bool> rst_i;
plic(sc_core::sc_module_name nm); plic(sc_core::sc_module_name nm);
virtual ~plic(); virtual ~plic();
protected: protected:
void clock_cb(); void clock_cb();
void reset_cb(); void reset_cb();

11
riscv.sc/incl/sysc/SiFive/spi.h
View File

@ -1,12 +1,12 @@
/******************************************************************************* /*******************************************************************************
* Copyright 2017 eyck@minres.com * Copyright 2017 eyck@minres.com
* *
* Licensed under the Apache License, Version 2.0 (the "License"); you may not * Licensed under the Apache License, Version 2.0 (the "License"); you may not
* use this file except in compliance with the License. You may obtain a copy * use this file except in compliance with the License. You may obtain a copy
* of the License at * of the License at
* *
* http://www.apache.org/licenses/LICENSE-2.0 * http://www.apache.org/licenses/LICENSE-2.0
* *
* Unless required by applicable law or agreed to in writing, software * Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
@ -23,13 +23,14 @@ namespace sysc {
class spi_regs; class spi_regs;
class spi: public sc_core::sc_module, public tlm_target<> { class spi : public sc_core::sc_module, public tlm_target<> {
public: public:
SC_HAS_PROCESS(spi); SC_HAS_PROCESS(spi);
sc_core::sc_in<sc_core::sc_time> clk_i; sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i; sc_core::sc_in<bool> rst_i;
spi(sc_core::sc_module_name nm); spi(sc_core::sc_module_name nm);
virtual ~spi(); virtual ~spi();
protected: protected:
void clock_cb(); void clock_cb();
void reset_cb(); void reset_cb();

11
riscv.sc/incl/sysc/SiFive/uart.h
View File

@ -1,12 +1,12 @@
/******************************************************************************* /*******************************************************************************
* Copyright 2017 eyck@minres.com * Copyright 2017 eyck@minres.com
* *
* Licensed under the Apache License, Version 2.0 (the "License"); you may not * Licensed under the Apache License, Version 2.0 (the "License"); you may not
* use this file except in compliance with the License. You may obtain a copy * use this file except in compliance with the License. You may obtain a copy
* of the License at * of the License at
* *
* http://www.apache.org/licenses/LICENSE-2.0 * http://www.apache.org/licenses/LICENSE-2.0
* *
* Unless required by applicable law or agreed to in writing, software * Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
@ -23,13 +23,14 @@ namespace sysc {
class uart_regs; class uart_regs;
class uart: public sc_core::sc_module, public tlm_target<> { class uart : public sc_core::sc_module, public tlm_target<> {
public: public:
SC_HAS_PROCESS(uart); SC_HAS_PROCESS(uart);
sc_core::sc_in<sc_core::sc_time> clk_i; sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i; sc_core::sc_in<bool> rst_i;
uart(sc_core::sc_module_name nm); uart(sc_core::sc_module_name nm);
virtual ~uart(); virtual ~uart();
protected: protected:
void clock_cb(); void clock_cb();
void reset_cb(); void reset_cb();

40
riscv.sc/src/sc_main.cpp
View File

@ -1,12 +1,12 @@
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Copyright 2017 eyck@minres.com // Copyright 2017 eyck@minres.com
// //
// Licensed under the Apache License, Version 2.0 (the "License"); you may not // Licensed under the Apache License, Version 2.0 (the "License"); you may not
// use this file except in compliance with the License. You may obtain a copy // use this file except in compliance with the License. You may obtain a copy
// of the License at // of the License at
// //
// http://www.apache.org/licenses/LICENSE-2.0 // http://www.apache.org/licenses/LICENSE-2.0
// //
// Unless required by applicable law or agreed to in writing, software // Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
@ -20,13 +20,13 @@
* Author: eyck@minres.com * Author: eyck@minres.com
*/ */
#include <sysc/tracer.h>
#include <sysc/scv_tr_db.h>
#include <sr_report/sr_report.h>
#include <boost/program_options.hpp> #include <boost/program_options.hpp>
#include <sysc/report.h> #include <sr_report/sr_report.h>
#include <sstream> #include <sstream>
#include <sysc/SiFive/platform.h> #include <sysc/SiFive/platform.h>
#include <sysc/report.h>
#include <sysc/scv_tr_db.h>
#include <sysc/tracer.h>
using namespace sysc; using namespace sysc;
namespace po = boost::program_options; namespace po = boost::program_options;
@ -37,28 +37,26 @@ const size_t SUCCESS = 0;
const size_t ERROR_UNHANDLED_EXCEPTION = 2; const size_t ERROR_UNHANDLED_EXCEPTION = 2;
} // namespace } // namespace
int sc_main(int argc, char* argv[]){ int sc_main(int argc, char *argv[]) {
// sc_report_handler::set_handler(my_report_handler); // sc_report_handler::set_handler(my_report_handler);
sysc::Logger::reporting_level()=log::DEBUG; sysc::Logger::reporting_level() = log::DEBUG;
/////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////
// CLI argument parsing // CLI argument parsing
/////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////
po::options_description desc("Options");\ po::options_description desc("Options");
desc.add_options()\ desc.add_options()("help,h", "Print help message")("debug,d", po::value<int>(),
("help,h", "Print help message")\ "set debug level")("trace,t", "trace SystemC signals");
("debug,d", po::value<int>(), "set debug level")\
("trace,t", "trace SystemC signals");
po::variables_map vm; po::variables_map vm;
try { try {
po::store(po::parse_command_line(argc, argv, desc), vm); // can throw po::store(po::parse_command_line(argc, argv, desc), vm); // can throw
// --help option // --help option
if ( vm.count("help") ){ if (vm.count("help")) {
std::cout << "JIT-ISS simulator for AVR" << std::endl << desc << std::endl; std::cout << "JIT-ISS simulator for AVR" << std::endl << desc << std::endl;
return SUCCESS; return SUCCESS;
} }
po::notify(vm); // throws on error, so do after help in case po::notify(vm); // throws on error, so do after help in case
// there are any problems // there are any problems
} catch(po::error& e){ } catch (po::error &e) {
std::cerr << "ERROR: " << e.what() << std::endl << std::endl; std::cerr << "ERROR: " << e.what() << std::endl << std::endl;
std::cerr << desc << std::endl; std::cerr << desc << std::endl;
return ERROR_IN_COMMAND_LINE; return ERROR_IN_COMMAND_LINE;
@ -71,13 +69,13 @@ int sc_main(int argc, char* argv[]){
// instantiate top level // instantiate top level
/////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////
platform i_simple_system("i_simple_system"); platform i_simple_system("i_simple_system");
//sr_report_handler::add_sc_object_to_filter(&i_simple_system.i_master, sc_core::SC_WARNING, sc_core::SC_MEDIUM); // sr_report_handler::add_sc_object_to_filter(&i_simple_system.i_master,
// sc_core::SC_WARNING, sc_core::SC_MEDIUM);
/////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////
// run simulation // run simulation
/////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////
sc_start(sc_core::sc_time(100, sc_core::SC_NS)); sc_start(sc_core::sc_time(100, sc_core::SC_NS));
if(!sc_end_of_simulation_invoked()) sc_stop(); if (!sc_end_of_simulation_invoked()) sc_stop();
return 0; return 0;
} }

6
riscv.sc/src/sysc/core_complex.cpp
View File

@ -39,12 +39,8 @@
namespace sysc { namespace sysc {
namespace SiFive { namespace SiFive {
core_complex::core_complex(sc_core::sc_module_name name) core_complex::core_complex(sc_core::sc_module_name name) : sc_core::sc_module(name), NAMED(initiator), NAMED(rst_i) {
:sc_core::sc_module(name)
, NAMED(initiator)
, NAMED(rst_i){
// TODO Auto-generated constructor stub // TODO Auto-generated constructor stub
} }
core_complex::~core_complex() { core_complex::~core_complex() {

25
riscv.sc/src/sysc/gpio.cpp
View File

@ -1,12 +1,12 @@
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Copyright 2017 eyck@minres.com // Copyright 2017 eyck@minres.com
// //
// Licensed under the Apache License, Version 2.0 (the "License"); you may not // Licensed under the Apache License, Version 2.0 (the "License"); you may not
// use this file except in compliance with the License. You may obtain a copy // use this file except in compliance with the License. You may obtain a copy
// of the License at // of the License at
// //
// http://www.apache.org/licenses/LICENSE-2.0 // http://www.apache.org/licenses/LICENSE-2.0
// //
// Unless required by applicable law or agreed to in writing, software // Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
@ -21,27 +21,20 @@
namespace sysc { namespace sysc {
gpio::gpio(sc_core::sc_module_name nm) gpio::gpio(sc_core::sc_module_name nm)
: sc_core::sc_module(nm) : sc_core::sc_module(nm), tlm_target<>(clk), NAMED(clk_i), NAMED(rst_i), NAMEDD(gpio_regs, regs) {
, tlm_target<>(clk)
, NAMED(clk_i)
, NAMED(rst_i)
, NAMEDD(gpio_regs, regs)
{
regs->registerResources(*this); regs->registerResources(*this);
SC_METHOD(clock_cb); SC_METHOD(clock_cb);
sensitive<<clk_i; sensitive << clk_i;
SC_METHOD(reset_cb); SC_METHOD(reset_cb);
sensitive<<rst_i; sensitive << rst_i;
} }
gpio::~gpio() { gpio::~gpio() {}
}
void gpio::clock_cb() { void gpio::clock_cb() {}
}
void gpio::reset_cb() { void gpio::reset_cb() {
if(rst_i.read()) if (rst_i.read())
regs->reset_start(); regs->reset_start();
else else
regs->reset_stop(); regs->reset_stop();

26
riscv.sc/src/sysc/platform.cpp
View File

@ -1,12 +1,12 @@
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Copyright 2017 eyck@minres.com // Copyright 2017 eyck@minres.com
// //
// Licensed under the Apache License, Version 2.0 (the "License"); you may not // Licensed under the Apache License, Version 2.0 (the "License"); you may not
// use this file except in compliance with the License. You may obtain a copy // use this file except in compliance with the License. You may obtain a copy
// of the License at // of the License at
// //
// http://www.apache.org/licenses/LICENSE-2.0 // http://www.apache.org/licenses/LICENSE-2.0
// //
// Unless required by applicable law or agreed to in writing, software // Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
@ -25,19 +25,11 @@
namespace sysc { namespace sysc {
platform::platform(sc_core::sc_module_name nm) platform::platform(sc_core::sc_module_name nm)
: sc_core::sc_module(nm) : sc_core::sc_module(nm), NAMED(i_master), NAMED(i_router, 4, 1), NAMED(i_uart), NAMED(i_spi), NAMED(i_gpio),
, NAMED(i_master) NAMED(i_plic), NAMED(s_clk), NAMED(s_rst) {
, NAMED(i_router, 4, 1)
, NAMED(i_uart)
, NAMED(i_spi)
, NAMED(i_gpio)
, NAMED(i_plic)
, NAMED(s_clk)
, NAMED(s_rst)
{
i_master.initiator(i_router.target[0]); i_master.initiator(i_router.target[0]);
size_t i=0; size_t i = 0;
for(const auto& e: e300_plat_map){ for (const auto &e : e300_plat_map) {
i_router.initiator.at(i)(e.target->socket); i_router.initiator.at(i)(e.target->socket);
i_router.add_target_range(i, e.start, e.size); i_router.add_target_range(i, e.start, e.size);
i++; i++;
@ -58,9 +50,9 @@ platform::platform(sc_core::sc_module_name nm)
} }
void platform::gen_reset() { void platform::gen_reset() {
s_rst=true; s_rst = true;
wait(10_ns); wait(10_ns);
s_rst=false; s_rst = false;
} }
} /* namespace sysc */ } /* namespace sysc */

26
riscv.sc/src/sysc/plic.cpp
View File

@ -1,12 +1,12 @@
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Copyright 2017 eyck@minres.com // Copyright 2017 eyck@minres.com
// //
// Licensed under the Apache License, Version 2.0 (the "License"); you may not // Licensed under the Apache License, Version 2.0 (the "License"); you may not
// use this file except in compliance with the License. You may obtain a copy // use this file except in compliance with the License. You may obtain a copy
// of the License at // of the License at
// //
// http://www.apache.org/licenses/LICENSE-2.0 // http://www.apache.org/licenses/LICENSE-2.0
// //
// Unless required by applicable law or agreed to in writing, software // Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
@ -21,28 +21,20 @@
namespace sysc { namespace sysc {
plic::plic(sc_core::sc_module_name nm) plic::plic(sc_core::sc_module_name nm)
: sc_core::sc_module(nm) : sc_core::sc_module(nm), tlm_target<>(clk), NAMED(clk_i), NAMED(rst_i), NAMEDD(plic_regs, regs) {
, tlm_target<>(clk)
, NAMED(clk_i)
, NAMED(rst_i)
, NAMEDD(plic_regs, regs)
{
regs->registerResources(*this); regs->registerResources(*this);
SC_METHOD(clock_cb); SC_METHOD(clock_cb);
sensitive<<clk_i; sensitive << clk_i;
SC_METHOD(reset_cb); SC_METHOD(reset_cb);
sensitive<<rst_i; sensitive << rst_i;
} }
plic::~plic() { plic::~plic() {}
}
void plic::clock_cb() { void plic::clock_cb() { this->clk = clk_i.read(); }
this->clk=clk_i.read();
}
void plic::reset_cb() { void plic::reset_cb() {
if(rst_i.read()) if (rst_i.read())
regs->reset_start(); regs->reset_start();
else else
regs->reset_stop(); regs->reset_stop();

26
riscv.sc/src/sysc/spi.cpp
View File

@ -1,12 +1,12 @@
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Copyright 2017 eyck@minres.com // Copyright 2017 eyck@minres.com
// //
// Licensed under the Apache License, Version 2.0 (the "License"); you may not // Licensed under the Apache License, Version 2.0 (the "License"); you may not
// use this file except in compliance with the License. You may obtain a copy // use this file except in compliance with the License. You may obtain a copy
// of the License at // of the License at
// //
// http://www.apache.org/licenses/LICENSE-2.0 // http://www.apache.org/licenses/LICENSE-2.0
// //
// Unless required by applicable law or agreed to in writing, software // Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
@ -21,28 +21,20 @@
namespace sysc { namespace sysc {
spi::spi(sc_core::sc_module_name nm) spi::spi(sc_core::sc_module_name nm)
: sc_core::sc_module(nm) : sc_core::sc_module(nm), tlm_target<>(clk), NAMED(clk_i), NAMED(rst_i), NAMEDD(spi_regs, regs) {
, tlm_target<>(clk)
, NAMED(clk_i)
, NAMED(rst_i)
, NAMEDD(spi_regs, regs)
{
regs->registerResources(*this); regs->registerResources(*this);
SC_METHOD(clock_cb); SC_METHOD(clock_cb);
sensitive<<clk_i; sensitive << clk_i;
SC_METHOD(reset_cb); SC_METHOD(reset_cb);
sensitive<<rst_i; sensitive << rst_i;
} }
spi::~spi() { spi::~spi() {}
}
void spi::clock_cb() { void spi::clock_cb() { this->clk = clk_i.read(); }
this->clk=clk_i.read();
}
void spi::reset_cb() { void spi::reset_cb() {
if(rst_i.read()) if (rst_i.read())
regs->reset_start(); regs->reset_start();
else else
regs->reset_stop(); regs->reset_stop();

26
riscv.sc/src/sysc/uart.cpp
View File

@ -1,12 +1,12 @@
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Copyright 2017 eyck@minres.com // Copyright 2017 eyck@minres.com
// //
// Licensed under the Apache License, Version 2.0 (the "License"); you may not // Licensed under the Apache License, Version 2.0 (the "License"); you may not
// use this file except in compliance with the License. You may obtain a copy // use this file except in compliance with the License. You may obtain a copy
// of the License at // of the License at
// //
// http://www.apache.org/licenses/LICENSE-2.0 // http://www.apache.org/licenses/LICENSE-2.0
// //
// Unless required by applicable law or agreed to in writing, software // Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
@ -21,28 +21,20 @@
namespace sysc { namespace sysc {
uart::uart(sc_core::sc_module_name nm) uart::uart(sc_core::sc_module_name nm)
: sc_core::sc_module(nm) : sc_core::sc_module(nm), tlm_target<>(clk), NAMED(clk_i), NAMED(rst_i), NAMEDD(uart_regs, regs) {
, tlm_target<>(clk)
, NAMED(clk_i)
, NAMED(rst_i)
, NAMEDD(uart_regs, regs)
{
regs->registerResources(*this); regs->registerResources(*this);
SC_METHOD(clock_cb); SC_METHOD(clock_cb);
sensitive<<clk_i; sensitive << clk_i;
SC_METHOD(reset_cb); SC_METHOD(reset_cb);
sensitive<<rst_i; sensitive << rst_i;
} }
uart::~uart() { uart::~uart() {}
}
void uart::clock_cb() { void uart::clock_cb() { this->clk = clk_i.read(); }
this->clk=clk_i.read();
}
void uart::reset_cb() { void uart::reset_cb() {
if(rst_i.read()) if (rst_i.read())
regs->reset_start(); regs->reset_start();
else else
regs->reset_stop(); regs->reset_stop();

62
riscv/incl/cli_options.h
View File

@ -1,21 +1,21 @@
/******************************************************************************* /*******************************************************************************
* Copyright (C) 2017, MINRES Technologies GmbH * Copyright (C) 2017, MINRES Technologies GmbH
* All rights reserved. * All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
* *
* 1. Redistributions of source code must retain the above copyright notice, * 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer. * this list of conditions and the following disclaimer.
* *
* 2. Redistributions in binary form must reproduce the above copyright notice, * 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation * this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution. * and/or other materials provided with the distribution.
* *
* 3. Neither the name of the copyright holder nor the names of its contributors * 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software * may be used to endorse or promote products derived from this software
* without specific prior written permission. * without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@ -27,7 +27,7 @@
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
* *
* Contributors: * Contributors:
* eyck@minres.com - initial API and implementation * eyck@minres.com - initial API and implementation
******************************************************************************/ ******************************************************************************/
@ -35,49 +35,47 @@
#ifndef _CLI_OPTIONS_H_ #ifndef _CLI_OPTIONS_H_
#define _CLI_OPTIONS_H_ #define _CLI_OPTIONS_H_
#include <boost/program_options.hpp> #include <boost/program_options.hpp>
#include <util/logging.h>
#include <iostream>
#include <cstdio> #include <cstdio>
#include <iostream>
#include <util/logging.h>
const size_t ERROR_IN_COMMAND_LINE = 1; const size_t ERROR_IN_COMMAND_LINE = 1;
const size_t SUCCESS = 0; const size_t SUCCESS = 0;
const size_t ERROR_UNHANDLED_EXCEPTION = 2; const size_t ERROR_UNHANDLED_EXCEPTION = 2;
inline int parse_cli_options(boost::program_options::variables_map& vm, int argc, char *argv[]){ inline int parse_cli_options(boost::program_options::variables_map &vm, int argc, char *argv[]) {
namespace po = boost::program_options; namespace po = boost::program_options;
po::options_description desc("Options"); po::options_description desc("Options");
desc.add_options() desc.add_options()("help,h", "Print help message")("verbose,v", po::value<int>()->implicit_value(0),
("help,h", "Print help message") "Sets logging verbosity")("vmodule", po::value<std::string>(),
("verbose,v", po::value<int>()->implicit_value(0), "Sets logging verbosity") "Defines the module(s) to be logged")(
("vmodule", po::value<std::string>(),"Defines the module(s) to be logged") "logging-flags", po::value<int>(), "Sets logging flag(s).")("log-file", po::value<std::string>(),
("logging-flags", po::value<int>(),"Sets logging flag(s).") "Sets default log file.")(
("log-file", po::value<std::string>(),"Sets default log file.") "disass,d", po::value<std::string>()->implicit_value(""),
("disass,d", po::value<std::string>()->implicit_value(""),"Enables disassembly") "Enables disassembly")("elf,l", po::value<std::vector<std::string>>(), "ELF file(s) to load")(
("elf,l", po::value< std::vector<std::string> >(), "ELF file(s) to load") "gdb-port,g", po::value<unsigned>(), "enable gdb server and specify port to use")(
("gdb-port,g", po::value<unsigned>(), "enable gdb server and specify port to use") "input,i", po::value<std::string>(), "the elf file to load (instead of hex files)")(
("input,i", po::value<std::string>(), "the elf file to load (instead of hex files)") "dump-ir", "dump the intermediate representation")("cycles,c", po::value<int64_t>()->default_value(-1),
("dump-ir", "dump the intermediate representation") "number of cycles to run")(
("cycles,c", po::value<int64_t>()->default_value(-1), "number of cycles to run") "systemc,s", "Run as SystemC simulation")("time", po::value<int>(), "SystemC siimulation time in ms")(
("systemc,s", "Run as SystemC simulation") "reset,r", po::value<std::string>(), "reset address")(
("time", po::value<int>(), "SystemC siimulation time in ms") "trace", po::value<uint8_t>(), "enable tracing, or cmbintation of 1=signals and 2=TX text, 4=TX "
("reset,r", po::value<std::string>(), "reset address") "compressed text, 6=TX in SQLite")("mem,m", po::value<std::string>(),
("trace", po::value<uint8_t>(), "enable tracing, or cmbintation of 1=signals and 2=TX text, 4=TX compressed text, 6=TX in SQLite")\ "the memory input file")("rv64", "run RV64");
("mem,m", po::value<std::string>(), "the memory input file")
("rv64", "run RV64");
try { try {
po::store(po::parse_command_line(argc, argv, desc), vm); // can throw po::store(po::parse_command_line(argc, argv, desc), vm); // can throw
// --help option // --help option
if ( vm.count("help") ){ if (vm.count("help")) {
std::cout << "DBT-RISE-RiscV" << std::endl << desc << std::endl; std::cout << "DBT-RISE-RiscV" << std::endl << desc << std::endl;
return SUCCESS; return SUCCESS;
} }
po::notify(vm); // throws on error, so do after help in case po::notify(vm); // throws on error, so do after help in case
} catch(po::error& e){ } catch (po::error &e) {
// there are problems // there are problems
std::cerr << "ERROR: " << e.what() << std::endl << std::endl; std::cerr << "ERROR: " << e.what() << std::endl << std::endl;
std::cerr << desc << std::endl; std::cerr << desc << std::endl;
return ERROR_IN_COMMAND_LINE; return ERROR_IN_COMMAND_LINE;
} }
return SUCCESS; return SUCCESS;
} }
#endif /* _CLI_OPTIONS_H_ */ #endif /* _CLI_OPTIONS_H_ */

1382
riscv/incl/iss/arch/riscv_hart_msu_vp.h
View File

File diff suppressed because it is too large Load Diff

83
riscv/incl/iss/arch/rv32imac.h
View File

@ -1,21 +1,21 @@
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH // Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved. // All rights reserved.
// //
// Redistribution and use in source and binary forms, with or without // Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met: // modification, are permitted provided that the following conditions are met:
// //
// 1. Redistributions of source code must retain the above copyright notice, // 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer. // this list of conditions and the following disclaimer.
// //
// 2. Redistributions in binary form must reproduce the above copyright notice, // 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation // this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution. // and/or other materials provided with the distribution.
// //
// 3. Neither the name of the copyright holder nor the names of its contributors // 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software // may be used to endorse or promote products derived from this software
// without specific prior written permission. // without specific prior written permission.
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@ -27,7 +27,7 @@
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE. // POSSIBILITY OF SUCH DAMAGE.
// //
// Created on: Thu Sep 21 17:01:54 CEST 2017 // Created on: Thu Sep 21 17:01:54 CEST 2017
// * rv32imac.h Author: <CoreDSL Generator> // * rv32imac.h Author: <CoreDSL Generator>
// //
@ -36,19 +36,30 @@
#ifndef _RV32IMAC_H_ #ifndef _RV32IMAC_H_
#define _RV32IMAC_H_ #define _RV32IMAC_H_
#include <iss/arch/traits.h>
#include <iss/arch_if.h> #include <iss/arch_if.h>
#include <iss/vm_if.h> #include <iss/vm_if.h>
#include <iss/arch/traits.h>
namespace iss { namespace iss {
namespace arch { namespace arch {
struct rv32imac; struct rv32imac;
template<> template <> struct traits<rv32imac> {
struct traits<rv32imac> {
enum constants {XLEN=32,XLEN2=64,XLEN_BIT_MASK=31,PCLEN=32,fence=0,fencei=1,fencevmal=2,fencevmau=3,MISA_VAL=1075056897,PGSIZE=4096,PGMASK=4095}; enum constants {
XLEN = 32,
XLEN2 = 64,
XLEN_BIT_MASK = 31,
PCLEN = 32,
fence = 0,
fencei = 1,
fencevmal = 2,
fencevmau = 3,
MISA_VAL = 1075056897,
PGSIZE = 4096,
PGMASK = 4095
};
enum reg_e { enum reg_e {
X0, X0,
@ -85,7 +96,7 @@ struct traits<rv32imac> {
X31, X31,
PC, PC,
NUM_REGS, NUM_REGS,
NEXT_PC=NUM_REGS, NEXT_PC = NUM_REGS,
TRAP_STATE, TRAP_STATE,
PENDING_TRAP, PENDING_TRAP,
MACHINE_STATE, MACHINE_STATE,
@ -96,61 +107,64 @@ struct traits<rv32imac> {
typedef uint32_t addr_t; typedef uint32_t addr_t;
typedef uint32_t code_word_t; //TODO: check removal typedef uint32_t code_word_t; // TODO: check removal
typedef iss::typed_addr_t<iss::VIRTUAL> virt_addr_t; typedef iss::typed_addr_t<iss::VIRTUAL> virt_addr_t;
typedef iss::typed_addr_t<iss::PHYSICAL> phys_addr_t; typedef iss::typed_addr_t<iss::PHYSICAL> phys_addr_t;
constexpr static unsigned reg_bit_width(unsigned r) { constexpr static unsigned reg_bit_width(unsigned r) {
const uint32_t RV32IMAC_reg_size[] = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64}; const uint32_t RV32IMAC_reg_size[] = {32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 64};
return RV32IMAC_reg_size[r]; return RV32IMAC_reg_size[r];
} }
constexpr static unsigned reg_byte_offset(unsigned r) { constexpr static unsigned reg_byte_offset(unsigned r) {
const uint32_t RV32IMAC_reg_byte_offset[] = {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,152,160}; const uint32_t RV32IMAC_reg_byte_offset[] = {0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48,
52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 96, 100,
104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 152, 160};
return RV32IMAC_reg_byte_offset[r]; return RV32IMAC_reg_byte_offset[r];
} }
enum sreg_flag_e {FLAGS}; enum sreg_flag_e { FLAGS };
enum mem_type_e {MEM,CSR,FENCE,RES};
enum mem_type_e { MEM, CSR, FENCE, RES };
}; };
struct rv32imac: public arch_if { struct rv32imac : public arch_if {
using virt_addr_t = typename traits<rv32imac>::virt_addr_t; using virt_addr_t = typename traits<rv32imac>::virt_addr_t;
using phys_addr_t = typename traits<rv32imac>::phys_addr_t; using phys_addr_t = typename traits<rv32imac>::phys_addr_t;
using reg_t = typename traits<rv32imac>::reg_t; using reg_t = typename traits<rv32imac>::reg_t;
using addr_t = typename traits<rv32imac>::addr_t; using addr_t = typename traits<rv32imac>::addr_t;
rv32imac(); rv32imac();
~rv32imac(); ~rv32imac();
virtual void reset(uint64_t address=0) override; virtual void reset(uint64_t address = 0) override;
virtual uint8_t* get_regs_base_ptr() override; virtual uint8_t *get_regs_base_ptr() override;
/// deprecated /// deprecated
virtual void get_reg(short idx, std::vector<uint8_t>& value) override {} virtual void get_reg(short idx, std::vector<uint8_t> &value) override {}
virtual void set_reg(short idx, const std::vector<uint8_t>& value) override {} virtual void set_reg(short idx, const std::vector<uint8_t> &value) override {}
/// deprecated /// deprecated
virtual bool get_flag(int flag) override {return false;} virtual bool get_flag(int flag) override { return false; }
virtual void set_flag(int, bool value) override {}; virtual void set_flag(int, bool value) override{};
/// deprecated /// deprecated
virtual void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {}; virtual void update_flags(operations op, uint64_t opr1, uint64_t opr2) override{};
virtual void notify_phase(exec_phase phase){ virtual void notify_phase(exec_phase phase) {
if(phase==ISTART){ if (phase == ISTART) {
++reg.icount; ++reg.icount;
reg.PC=reg.NEXT_PC; reg.PC = reg.NEXT_PC;
reg.trap_state=reg.pending_trap; reg.trap_state = reg.pending_trap;
} }
} }
uint64_t get_icount() { return reg.icount;} uint64_t get_icount() { return reg.icount; }
virtual phys_addr_t v2p(const iss::addr_t& pc); virtual phys_addr_t v2p(const iss::addr_t &pc);
virtual iss::sync_type needed_sync() const { return iss::PRE_SYNC; } virtual iss::sync_type needed_sync() const { return iss::PRE_SYNC; }
@ -194,7 +208,6 @@ protected:
uint64_t icount; uint64_t icount;
} reg; } reg;
}; };
} }
} }
#endif /* _RV32IMAC_H_ */ #endif /* _RV32IMAC_H_ */

82
riscv/incl/iss/arch/rv64ia.h
View File

@ -1,21 +1,21 @@
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH // Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved. // All rights reserved.
// //
// Redistribution and use in source and binary forms, with or without // Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met: // modification, are permitted provided that the following conditions are met:
// //
// 1. Redistributions of source code must retain the above copyright notice, // 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer. // this list of conditions and the following disclaimer.
// //
// 2. Redistributions in binary form must reproduce the above copyright notice, // 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation // this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution. // and/or other materials provided with the distribution.
// //
// 3. Neither the name of the copyright holder nor the names of its contributors // 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software // may be used to endorse or promote products derived from this software
// without specific prior written permission. // without specific prior written permission.
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@ -27,7 +27,7 @@
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE. // POSSIBILITY OF SUCH DAMAGE.
// //
// Created on: Thu Sep 21 17:01:54 CEST 2017 // Created on: Thu Sep 21 17:01:54 CEST 2017
// * rv64ia.h Author: <CoreDSL Generator> // * rv64ia.h Author: <CoreDSL Generator>
// //
@ -36,19 +36,30 @@
#ifndef _RV64IA_H_ #ifndef _RV64IA_H_
#define _RV64IA_H_ #define _RV64IA_H_
#include <iss/arch/traits.h>
#include <iss/arch_if.h> #include <iss/arch_if.h>
#include <iss/vm_if.h> #include <iss/vm_if.h>
#include <iss/arch/traits.h>
namespace iss { namespace iss {
namespace arch { namespace arch {
struct rv64ia; struct rv64ia;
template<> template <> struct traits<rv64ia> {
struct traits<rv64ia> {
enum constants {XLEN=64,XLEN2=128,XLEN_BIT_MASK=63,PCLEN=64,fence=0,fencei=1,fencevmal=2,fencevmau=3,MISA_VAL=2147750144,PGSIZE=4096,PGMASK=4095}; enum constants {
XLEN = 64,
XLEN2 = 128,
XLEN_BIT_MASK = 63,
PCLEN = 64,
fence = 0,
fencei = 1,
fencevmal = 2,
fencevmau = 3,
MISA_VAL = 2147750144,
PGSIZE = 4096,
PGMASK = 4095
};
enum reg_e { enum reg_e {
X0, X0,
@ -85,7 +96,7 @@ struct traits<rv64ia> {
X31, X31,
PC, PC,
NUM_REGS, NUM_REGS,
NEXT_PC=NUM_REGS, NEXT_PC = NUM_REGS,
TRAP_STATE, TRAP_STATE,
PENDING_TRAP, PENDING_TRAP,
MACHINE_STATE, MACHINE_STATE,
@ -96,61 +107,63 @@ struct traits<rv64ia> {
typedef uint64_t addr_t; typedef uint64_t addr_t;
typedef uint64_t code_word_t; //TODO: check removal typedef uint64_t code_word_t; // TODO: check removal
typedef iss::typed_addr_t<iss::VIRTUAL> virt_addr_t; typedef iss::typed_addr_t<iss::VIRTUAL> virt_addr_t;
typedef iss::typed_addr_t<iss::PHYSICAL> phys_addr_t; typedef iss::typed_addr_t<iss::PHYSICAL> phys_addr_t;
constexpr static unsigned reg_bit_width(unsigned r) { constexpr static unsigned reg_bit_width(unsigned r) {
const uint32_t RV64IA_reg_size[] = {64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,32,32,32,64}; const uint32_t RV64IA_reg_size[] = {64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 32, 32, 32, 64};
return RV64IA_reg_size[r]; return RV64IA_reg_size[r];
} }
constexpr static unsigned reg_byte_offset(unsigned r) { constexpr static unsigned reg_byte_offset(unsigned r) {
const uint32_t RV64IA_reg_byte_offset[] = {0,8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,256,264,272,276,280,288,296}; const uint32_t RV64IA_reg_byte_offset[] = {0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96,
104, 112, 120, 128, 136, 144, 152, 160, 168, 176, 184, 192, 200,
208, 216, 224, 232, 240, 248, 256, 264, 272, 276, 280, 288, 296};
return RV64IA_reg_byte_offset[r]; return RV64IA_reg_byte_offset[r];
} }
enum sreg_flag_e {FLAGS}; enum sreg_flag_e { FLAGS };
enum mem_type_e {MEM,CSR,FENCE,RES};
enum mem_type_e { MEM, CSR, FENCE, RES };
}; };
struct rv64ia: public arch_if { struct rv64ia : public arch_if {
using virt_addr_t = typename traits<rv64ia>::virt_addr_t; using virt_addr_t = typename traits<rv64ia>::virt_addr_t;
using phys_addr_t = typename traits<rv64ia>::phys_addr_t; using phys_addr_t = typename traits<rv64ia>::phys_addr_t;
using reg_t = typename traits<rv64ia>::reg_t; using reg_t = typename traits<rv64ia>::reg_t;
using addr_t = typename traits<rv64ia>::addr_t; using addr_t = typename traits<rv64ia>::addr_t;
rv64ia(); rv64ia();
~rv64ia(); ~rv64ia();
virtual void reset(uint64_t address=0) override; virtual void reset(uint64_t address = 0) override;
virtual uint8_t* get_regs_base_ptr() override; virtual uint8_t *get_regs_base_ptr() override;
/// deprecated /// deprecated
virtual void get_reg(short idx, std::vector<uint8_t>& value) override {} virtual void get_reg(short idx, std::vector<uint8_t> &value) override {}
virtual void set_reg(short idx, const std::vector<uint8_t>& value) override {} virtual void set_reg(short idx, const std::vector<uint8_t> &value) override {}
/// deprecated /// deprecated
virtual bool get_flag(int flag) override {return false;} virtual bool get_flag(int flag) override { return false; }
virtual void set_flag(int, bool value) override {}; virtual void set_flag(int, bool value) override{};
/// deprecated /// deprecated
virtual void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {}; virtual void update_flags(operations op, uint64_t opr1, uint64_t opr2) override{};
virtual void notify_phase(exec_phase phase){ virtual void notify_phase(exec_phase phase) {
if(phase==ISTART){ if (phase == ISTART) {
++reg.icount; ++reg.icount;
reg.PC=reg.NEXT_PC; reg.PC = reg.NEXT_PC;
reg.trap_state=reg.pending_trap; reg.trap_state = reg.pending_trap;
} }
} }
uint64_t get_icount() { return reg.icount;} uint64_t get_icount() { return reg.icount; }
virtual phys_addr_t v2p(const iss::addr_t& pc); virtual phys_addr_t v2p(const iss::addr_t &pc);
virtual iss::sync_type needed_sync() const { return iss::PRE_SYNC; } virtual iss::sync_type needed_sync() const { return iss::PRE_SYNC; }
@ -194,7 +207,6 @@ protected:
uint64_t icount; uint64_t icount;
} reg; } reg;
}; };
} }
} }
#endif /* _RV64IA_H_ */ #endif /* _RV64IA_H_ */

791
riscv/src/internal/vm_riscv.in.cpp
View File

File diff suppressed because it is too large Load Diff

4872
riscv/src/internal/vm_rv32imac.cpp
View File

File diff suppressed because it is too large Load Diff

3952
riscv/src/internal/vm_rv64ia.cpp
View File

File diff suppressed because it is too large Load Diff

40
riscv/src/iss/rv32imac.cpp
View File

@ -1,21 +1,21 @@
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH // Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved. // All rights reserved.
// //
// Redistribution and use in source and binary forms, with or without // Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met: // modification, are permitted provided that the following conditions are met:
// //
// 1. Redistributions of source code must retain the above copyright notice, // 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer. // this list of conditions and the following disclaimer.
// //
// 2. Redistributions in binary form must reproduce the above copyright notice, // 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation // this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution. // and/or other materials provided with the distribution.
// //
// 3. Neither the name of the copyright holder nor the names of its contributors // 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software // may be used to endorse or promote products derived from this software
// without specific prior written permission. // without specific prior written permission.
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@ -27,7 +27,7 @@
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE. // POSSIBILITY OF SUCH DAMAGE.
// //
// Created on: Tue Aug 29 16:45:20 CEST 2017 // Created on: Tue Aug 29 16:45:20 CEST 2017
// * rv32imac.cpp Author: <CoreDSL Generator> // * rv32imac.cpp Author: <CoreDSL Generator>
// //
@ -46,31 +46,27 @@ extern "C" {
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#include <fstream>
#include <cstdio> #include <cstdio>
#include <cstring> #include <cstring>
#include <fstream>
using namespace iss::arch; using namespace iss::arch;
rv32imac::rv32imac() { rv32imac::rv32imac() { reg.icount = 0; }
reg.icount=0;
}
rv32imac::~rv32imac(){ rv32imac::~rv32imac() {}
}
void rv32imac::reset(uint64_t address) { void rv32imac::reset(uint64_t address) {
for(size_t i=0; i<traits<rv32imac>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<rv32imac>::reg_t),0)); for (size_t i = 0; i < traits<rv32imac>::NUM_REGS; ++i)
reg.PC=address; set_reg(i, std::vector<uint8_t>(sizeof(traits<rv32imac>::reg_t), 0));
reg.NEXT_PC=reg.PC; reg.PC = address;
reg.trap_state=0; reg.NEXT_PC = reg.PC;
reg.machine_state=0x3; reg.trap_state = 0;
reg.machine_state = 0x3;
} }
uint8_t* rv32imac::get_regs_base_ptr(){ uint8_t *rv32imac::get_regs_base_ptr() { return reinterpret_cast<uint8_t *>(&reg); }
return reinterpret_cast<uint8_t*>(&reg);
}
rv32imac::phys_addr_t rv32imac::v2p(const iss::addr_t& pc) { rv32imac::phys_addr_t rv32imac::v2p(const iss::addr_t &pc) {
return phys_addr_t(pc); //change logical address to physical address return phys_addr_t(pc); // change logical address to physical address
} }

40
riscv/src/iss/rv64ia.cpp
View File

@ -1,21 +1,21 @@
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH // Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved. // All rights reserved.
// //
// Redistribution and use in source and binary forms, with or without // Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met: // modification, are permitted provided that the following conditions are met:
// //
// 1. Redistributions of source code must retain the above copyright notice, // 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer. // this list of conditions and the following disclaimer.
// //
// 2. Redistributions in binary form must reproduce the above copyright notice, // 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation // this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution. // and/or other materials provided with the distribution.
// //
// 3. Neither the name of the copyright holder nor the names of its contributors // 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software // may be used to endorse or promote products derived from this software
// without specific prior written permission. // without specific prior written permission.
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@ -27,7 +27,7 @@
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE. // POSSIBILITY OF SUCH DAMAGE.
// //
// Created on: Tue Sep 05 18:57:24 CEST 2017 // Created on: Tue Sep 05 18:57:24 CEST 2017
// * rv64ia.cpp Author: <CoreDSL Generator> // * rv64ia.cpp Author: <CoreDSL Generator>
// //
@ -46,31 +46,27 @@ extern "C" {
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#include <fstream>
#include <cstdio> #include <cstdio>
#include <cstring> #include <cstring>
#include <fstream>
using namespace iss::arch; using namespace iss::arch;
rv64ia::rv64ia() { rv64ia::rv64ia() { reg.icount = 0; }
reg.icount=0;
}
rv64ia::~rv64ia(){ rv64ia::~rv64ia() {}
}
void rv64ia::reset(uint64_t address) { void rv64ia::reset(uint64_t address) {
for(size_t i=0; i<traits<rv64ia>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<rv64ia>::reg_t),0)); for (size_t i = 0; i < traits<rv64ia>::NUM_REGS; ++i)
reg.PC=address; set_reg(i, std::vector<uint8_t>(sizeof(traits<rv64ia>::reg_t), 0));
reg.NEXT_PC=reg.PC; reg.PC = address;
reg.trap_state=0; reg.NEXT_PC = reg.PC;
reg.machine_state=0x0; reg.trap_state = 0;
reg.machine_state = 0x0;
} }
uint8_t* rv64ia::get_regs_base_ptr(){ uint8_t *rv64ia::get_regs_base_ptr() { return reinterpret_cast<uint8_t *>(&reg); }
return reinterpret_cast<uint8_t*>(&reg);
}
rv64ia::phys_addr_t rv64ia::v2p(const iss::addr_t& pc) { rv64ia::phys_addr_t rv64ia::v2p(const iss::addr_t &pc) {
return phys_addr_t(pc); //change logical address to physical address return phys_addr_t(pc); // change logical address to physical address
} }

64
riscv/src/main.cpp
View File

@ -1,21 +1,21 @@
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH // Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved. // All rights reserved.
// //
// Redistribution and use in source and binary forms, with or without // Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met: // modification, are permitted provided that the following conditions are met:
// //
// 1. Redistributions of source code must retain the above copyright notice, // 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer. // this list of conditions and the following disclaimer.
// //
// 2. Redistributions in binary form must reproduce the above copyright notice, // 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation // this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution. // and/or other materials provided with the distribution.
// //
// 3. Neither the name of the copyright holder nor the names of its contributors // 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software // may be used to endorse or promote products derived from this software
// without specific prior written permission. // without specific prior written permission.
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@ -27,37 +27,36 @@
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE. // POSSIBILITY OF SUCH DAMAGE.
// //
// Contributors: // Contributors:
// eyck@minres.com - initial API and implementation // eyck@minres.com - initial API and implementation
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
#include <cli_options.h> #include <cli_options.h>
#include <iss/iss.h>
#include <iostream> #include <iostream>
#include <iss/iss.h>
#include <iss/log_categories.h> #include <boost/lexical_cast.hpp>
#include <iss/arch/rv32imac.h> #include <iss/arch/rv32imac.h>
#include <iss/arch/rv64ia.h> #include <iss/arch/rv64ia.h>
#include <iss/jit/MCJIThelper.h> #include <iss/jit/MCJIThelper.h>
#include <boost/lexical_cast.hpp> #include <iss/log_categories.h>
namespace po= boost::program_options; namespace po = boost::program_options;
int main(int argc, char *argv[]) { int main(int argc, char *argv[]) {
try{ try {
/* /*
* Define and parse the program options * Define and parse the program options
*/ */
po::variables_map vm; po::variables_map vm;
if(parse_cli_options(vm, argc, argv)) return ERROR_IN_COMMAND_LINE; if (parse_cli_options(vm, argc, argv)) return ERROR_IN_COMMAND_LINE;
if(vm.count("verbose")){ if (vm.count("verbose")) {
auto l = logging::as_log_level(vm["verbose"].as<int>()); auto l = logging::as_log_level(vm["verbose"].as<int>());
LOGGER(DEFAULT)::reporting_level() = l; LOGGER(DEFAULT)::reporting_level() = l;
LOGGER(connection)::reporting_level()=l; LOGGER(connection)::reporting_level() = l;
} }
if(vm.count("log-file")){ if (vm.count("log-file")) {
// configure the connection logger // configure the connection logger
auto f = fopen(vm["log-file"].as<std::string>().c_str(), "w"); auto f = fopen(vm["log-file"].as<std::string>().c_str(), "w");
LOG_OUTPUT(DEFAULT)::stream() = f; LOG_OUTPUT(DEFAULT)::stream() = f;
@ -66,48 +65,47 @@ int main(int argc, char *argv[]) {
// application code comes here // // application code comes here //
iss::init_jit(argc, argv); iss::init_jit(argc, argv);
bool dump=vm.count("dump-ir"); bool dump = vm.count("dump-ir");
// instantiate the simulator // instantiate the simulator
std::unique_ptr<iss::vm_if> cpu = nullptr; std::unique_ptr<iss::vm_if> cpu = nullptr;
if(vm.count("rv64")==1){ if (vm.count("rv64") == 1) {
if(vm.count("gdb-port")==1) if (vm.count("gdb-port") == 1)
cpu = iss::create<iss::arch::rv64ia>("rv64ia", vm["gdb-port"].as<unsigned>(), dump); cpu = iss::create<iss::arch::rv64ia>("rv64ia", vm["gdb-port"].as<unsigned>(), dump);
else else
cpu = iss::create<iss::arch::rv64ia>("rv64ia", dump); cpu = iss::create<iss::arch::rv64ia>("rv64ia", dump);
} else { } else {
if(vm.count("gdb-port")==1) if (vm.count("gdb-port") == 1)
cpu = iss::create<iss::arch::rv32imac>("rv32ima", vm["gdb-port"].as<unsigned>(), dump); cpu = iss::create<iss::arch::rv32imac>("rv32ima", vm["gdb-port"].as<unsigned>(), dump);
else else
cpu = iss::create<iss::arch::rv32imac>("rv32ima", dump); cpu = iss::create<iss::arch::rv32imac>("rv32ima", dump);
} }
if(vm.count("elf")){ if (vm.count("elf")) {
for(std::string input: vm["elf"].as<std::vector<std::string> >()) for (std::string input : vm["elf"].as<std::vector<std::string>>()) cpu->get_arch()->load_file(input);
cpu->get_arch()->load_file(input); } else if (vm.count("mem")) {
} else if(vm.count("mem")){ cpu->get_arch()->load_file(vm["mem"].as<std::string>(), iss::arch::traits<iss::arch::rv32imac>::MEM);
cpu->get_arch()->load_file(vm["mem"].as<std::string>() , iss::arch::traits<iss::arch::rv32imac>::MEM);
} }
if(vm.count("disass")){ if (vm.count("disass")) {
cpu->setDisassEnabled(true); cpu->setDisassEnabled(true);
LOGGER(disass)::reporting_level()=logging::INFO; LOGGER(disass)::reporting_level() = logging::INFO;
auto file_name=vm["disass"].as<std::string>(); auto file_name = vm["disass"].as<std::string>();
if (file_name.length() > 0) { if (file_name.length() > 0) {
LOG_OUTPUT(disass)::stream() = fopen(file_name.c_str(), "w"); LOG_OUTPUT(disass)::stream() = fopen(file_name.c_str(), "w");
LOGGER(disass)::print_time() = false; LOGGER(disass)::print_time() = false;
LOGGER(disass)::print_severity() = false; LOGGER(disass)::print_severity() = false;
} }
} }
if(vm.count("reset")){ if (vm.count("reset")) {
auto str = vm["reset"].as<std::string>(); auto str = vm["reset"].as<std::string>();
auto start_address = str.find("0x")==0? std::stoull(str, 0, 16):std::stoull(str, 0, 10); auto start_address = str.find("0x") == 0 ? std::stoull(str, 0, 16) : std::stoull(str, 0, 10);
cpu->reset(start_address); cpu->reset(start_address);
} else { } else {
cpu->reset(); cpu->reset();
} }
return cpu->start(vm["cycles"].as<int64_t>()); return cpu->start(vm["cycles"].as<int64_t>());
} catch(std::exception& e){ } catch (std::exception &e) {
LOG(ERROR) << "Unhandled Exception reached the top of main: " LOG(ERROR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit"
<< e.what() << ", application will now exit" << std::endl; << std::endl;
return ERROR_UNHANDLED_EXCEPTION; return ERROR_UNHANDLED_EXCEPTION;
} }
} }

2
sc-components

@ -1 +1 @@
Subproject commit 46d79504a8a5a6a9541b19a6774fb8161350a0a4 Subproject commit a5c9101b71da3824af4a54322232de270c5547de