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Applied clang-format

This commit is contained in:
Eyck Jentzsch 2017-09-22 11:23:23 +02:00
parent 39150b68c0
commit b38319f9c2
34 changed files with 5579 additions and 6723 deletions
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97
.clang-format Normal file
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@ -0,0 +1,97 @@
---
Language: Cpp
# BasedOnStyle: LLVM
# should be in line with IndentWidth
AccessModifierOffset: -4
AlignAfterOpenBracket: Align
AlignConsecutiveAssignments: false
AlignConsecutiveDeclarations: false
AlignEscapedNewlinesLeft: false
AlignOperands: true
AlignTrailingComments: true
AllowAllParametersOfDeclarationOnNextLine: true
AllowShortBlocksOnASingleLine: false
AllowShortCaseLabelsOnASingleLine: false
AllowShortFunctionsOnASingleLine: All
AllowShortIfStatementsOnASingleLine: true
AllowShortLoopsOnASingleLine: true
AlwaysBreakAfterDefinitionReturnType: None
AlwaysBreakAfterReturnType: None
AlwaysBreakBeforeMultilineStrings: false
AlwaysBreakTemplateDeclarations: false
BinPackArguments: true
BinPackParameters: true
BraceWrapping:
AfterClass: false
AfterControlStatement: false
AfterEnum: false
AfterFunction: false
AfterNamespace: false
AfterObjCDeclaration: false
AfterStruct: false
AfterUnion: false
BeforeCatch: false
BeforeElse: false
IndentBraces: false
BreakBeforeBinaryOperators: None
BreakBeforeBraces: Attach
BreakBeforeTernaryOperators: true
BreakConstructorInitializersBeforeComma: false
BreakAfterJavaFieldAnnotations: false
BreakStringLiterals: true
ColumnLimit: 120
CommentPragmas: '^ IWYU pragma:'
ConstructorInitializerAllOnOneLineOrOnePerLine: false
ConstructorInitializerIndentWidth: 4
ContinuationIndentWidth: 4
Cpp11BracedListStyle: true
DerivePointerAlignment: false
DisableFormat: false
ExperimentalAutoDetectBinPacking: false
ForEachMacros: [ foreach, Q_FOREACH, BOOST_FOREACH ]
IncludeCategories:
- Regex: '^"(llvm|llvm-c|clang|clang-c)/'
Priority: 2
- Regex: '^(<|"(gtest|isl|json)/)'
Priority: 3
- Regex: '.*'
Priority: 1
IncludeIsMainRegex: '$'
IndentCaseLabels: false
IndentWidth: 4
IndentWrappedFunctionNames: false
JavaScriptQuotes: Leave
JavaScriptWrapImports: true
KeepEmptyLinesAtTheStartOfBlocks: true
MacroBlockBegin: ''
MacroBlockEnd: ''
MaxEmptyLinesToKeep: 1
NamespaceIndentation: None
ObjCBlockIndentWidth: 2
ObjCSpaceAfterProperty: false
ObjCSpaceBeforeProtocolList: true
PenaltyBreakBeforeFirstCallParameter: 19
PenaltyBreakComment: 300
PenaltyBreakFirstLessLess: 120
PenaltyBreakString: 1000
PenaltyExcessCharacter: 1000000
PenaltyReturnTypeOnItsOwnLine: 60
PointerAlignment: Right
ReflowComments: true
SortIncludes: true
SpaceAfterCStyleCast: false
SpaceAfterTemplateKeyword: true
SpaceBeforeAssignmentOperators: true
SpaceBeforeParens: ControlStatements
SpaceInEmptyParentheses: false
SpacesBeforeTrailingComments: 1
SpacesInAngles: false
SpacesInContainerLiterals: true
SpacesInCStyleCastParentheses: false
SpacesInParentheses: false
SpacesInSquareBrackets: false
Standard: Cpp11
TabWidth: 4
UseTab: Never
...

27
.cproject
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@ -516,7 +516,6 @@
<buildTargets> <buildTargets>
<target name="all VERBOSE=1" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder"> <target name="all VERBOSE=1" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand> <buildCommand>make</buildCommand>
<buildArguments/>
<buildTarget>all VERBOSE=1</buildTarget> <buildTarget>all VERBOSE=1</buildTarget>
<stopOnError>true</stopOnError> <stopOnError>true</stopOnError>
<useDefaultCommand>true</useDefaultCommand> <useDefaultCommand>true</useDefaultCommand>
@ -524,7 +523,6 @@
</target> </target>
<target name="clean" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder"> <target name="clean" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand> <buildCommand>make</buildCommand>
<buildArguments/>
<buildTarget>clean</buildTarget> <buildTarget>clean</buildTarget>
<stopOnError>true</stopOnError> <stopOnError>true</stopOnError>
<useDefaultCommand>true</useDefaultCommand> <useDefaultCommand>true</useDefaultCommand>
@ -532,12 +530,35 @@
</target> </target>
<target name="all" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder"> <target name="all" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand> <buildCommand>make</buildCommand>
<buildArguments/>
<buildTarget>all</buildTarget> <buildTarget>all</buildTarget>
<stopOnError>true</stopOnError> <stopOnError>true</stopOnError>
<useDefaultCommand>true</useDefaultCommand> <useDefaultCommand>true</useDefaultCommand>
<runAllBuilders>true</runAllBuilders> <runAllBuilders>true</runAllBuilders>
</target> </target>
<target name="clangformat" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand>
<buildArguments/>
<buildTarget>clangformat</buildTarget>
<stopOnError>true</stopOnError>
<useDefaultCommand>true</useDefaultCommand>
<runAllBuilders>true</runAllBuilders>
</target>
<target name="riscv" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand>
<buildArguments/>
<buildTarget>riscv</buildTarget>
<stopOnError>true</stopOnError>
<useDefaultCommand>true</useDefaultCommand>
<runAllBuilders>true</runAllBuilders>
</target>
<target name="riscv.sc" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand>
<buildArguments/>
<buildTarget>riscv.sc</buildTarget>
<stopOnError>true</stopOnError>
<useDefaultCommand>true</useDefaultCommand>
<runAllBuilders>true</runAllBuilders>
</target>
</buildTargets> </buildTargets>
</storageModule> </storageModule>
</cproject> </cproject>

3
CMakeLists.txt
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@ -27,6 +27,9 @@ endif()
FIND_PACKAGE(Threads) FIND_PACKAGE(Threads)
set(PROJECT_3PARTY_DIRS external sr_report sr_signal)
include(sc-components/cmake/clang-format.cmake)
add_subdirectory(external) add_subdirectory(external)
add_subdirectory(dbt-core) add_subdirectory(dbt-core)
add_subdirectory(sc-components) add_subdirectory(sc-components)

2
dbt-core

@ -1 +1 @@
Subproject commit f23a45ab77d25ac42fd8df3e3f7206baad122c67 Subproject commit 7902b61b2cb504defdbb48baf74c7facfa7c249c

170
riscv.sc/incl/cli_options.h
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@ -35,132 +35,134 @@
#ifndef _CLI_OPTIONS_H_ #ifndef _CLI_OPTIONS_H_
#define _CLI_OPTIONS_H_ #define _CLI_OPTIONS_H_
#include <boost/program_options.hpp> #include <boost/program_options.hpp>
#include <util/logging.h>
#include <iostream>
#include <cstdio> #include <cstdio>
#include <iostream>
#include <util/logging.h>
namespace { namespace {
const size_t ERROR_IN_COMMAND_LINE = 1; const size_t ERROR_IN_COMMAND_LINE = 1;
const size_t SUCCESS = 0; const size_t SUCCESS = 0;
const size_t ERROR_UNHANDLED_EXCEPTION = 2; const size_t ERROR_UNHANDLED_EXCEPTION = 2;
inline void enable_log_level(int level) {
inline void enable_log_level(int level){ switch (level) {
switch(level){
case 0: case 0:
logging::Logger::reporting_level()= logging::FATAL; logging::Logger::reporting_level() = logging::FATAL;
/* no break */ /* no break */
case 1: case 1:
logging::Logger::reporting_level()= logging::ERROR; logging::Logger::reporting_level() = logging::ERROR;
/* no break */ /* no break */
case 2: case 2:
logging::Logger::reporting_level()= logging::WARNING; logging::Logger::reporting_level() = logging::WARNING;
/* no break */ /* no break */
case 3: case 3:
logging::Logger::reporting_level()= logging::INFO; logging::Logger::reporting_level() = logging::INFO;
/* no break */ /* no break */
case 4: case 4:
logging::Logger::reporting_level()= logging::DEBUG; logging::Logger::reporting_level() = logging::DEBUG;
/* no break */ /* no break */
case 5: case 5:
logging::Logger::reporting_level()= logging::TRACE; logging::Logger::reporting_level() = logging::TRACE;
/* no break */ /* no break */
} }
} }
inline void configure_default_logger(boost::program_options::variables_map& vm){ inline void configure_default_logger(boost::program_options::variables_map &vm) {
// el::Configurations defaultConf; // el::Configurations defaultConf;
// defaultConf.setToDefault(); // defaultConf.setToDefault();
// defaultConf.set(el::Level::Error, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg"); // defaultConf.set(el::Level::Error, el::ConfigurationType::Format,
// defaultConf.set(el::Level::Warning, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg"); //"%datetime{%H:%m:%s.%g} %level %msg");
// defaultConf.set(el::Level::Info, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg"); // defaultConf.set(el::Level::Warning, el::ConfigurationType::Format,
// defaultConf.set(el::Level::Debug, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg"); //"%datetime{%H:%m:%s.%g} %level %msg");
// defaultConf.set(el::Level::Trace, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg"); // defaultConf.set(el::Level::Info, el::ConfigurationType::Format,
if(vm.count("verbose")) //"%datetime{%H:%m:%s.%g} %level %msg");
enable_log_level(vm["verbose"].as<int>()); // defaultConf.set(el::Level::Debug, el::ConfigurationType::Format,
if(vm.count("log-file")) //"%datetime{%H:%m:%s.%g} %level %msg");
logging::Output2FILE::stream() = fopen(vm["log-file"].as<std::string>().c_str(), "w"); // defaultConf.set(el::Level::Trace, el::ConfigurationType::Format,
//"%datetime{%H:%m:%s.%g} %level %msg");
if (vm.count("verbose")) enable_log_level(vm["verbose"].as<int>());
if (vm.count("log-file")) logging::Output2FILE::stream() = fopen(vm["log-file"].as<std::string>().c_str(), "w");
// default logger uses default configurations // default logger uses default configurations
// el::Loggers::reconfigureLogger("default", defaultConf); // el::Loggers::reconfigureLogger("default", defaultConf);
} }
inline void configure_debugger_logger() { inline void configure_debugger_logger() {
// configure the connection logger // configure the connection logger
// el::Logger* gdbServerLogger = el::Loggers::getLogger(connection); // el::Logger* gdbServerLogger = el::Loggers::getLogger(connection);
// el::Configurations gdbServerConf; // el::Configurations gdbServerConf;
// gdbServerConf.setToDefault(); // gdbServerConf.setToDefault();
// gdbServerConf.set(el::Level::Error, el::ConfigurationType::Format, // gdbServerConf.set(el::Level::Error, el::ConfigurationType::Format,
// "%datetime{%H:%m:%s.%g} %level [%logger] %msg"); // "%datetime{%H:%m:%s.%g} %level [%logger] %msg");
// gdbServerConf.set(el::Level::Warning, el::ConfigurationType::Format, // gdbServerConf.set(el::Level::Warning, el::ConfigurationType::Format,
// "%datetime{%H:%m:%s.%g} %level [%logger] %msg"); // "%datetime{%H:%m:%s.%g} %level [%logger] %msg");
// gdbServerConf.set(el::Level::Info, el::ConfigurationType::Format, // gdbServerConf.set(el::Level::Info, el::ConfigurationType::Format,
// "%datetime{%H:%m:%s.%g} %level [%logger] %msg"); // "%datetime{%H:%m:%s.%g} %level [%logger] %msg");
// gdbServerConf.set(el::Level::Debug, el::ConfigurationType::Format, // gdbServerConf.set(el::Level::Debug, el::ConfigurationType::Format,
// "%datetime{%H:%m:%s.%g} %level [%logger] %msg"); // "%datetime{%H:%m:%s.%g} %level [%logger] %msg");
// gdbServerConf.set(el::Level::Trace, el::ConfigurationType::Format, // gdbServerConf.set(el::Level::Trace, el::ConfigurationType::Format,
// "%datetime{%H:%m:%s.%g} %level [%logger] %msg"); // "%datetime{%H:%m:%s.%g} %level [%logger] %msg");
// enable_log_level(gdbServerConf, 5); // enable_log_level(gdbServerConf, 5);
// gdbServerLogger->configure(gdbServerConf); // gdbServerLogger->configure(gdbServerConf);
} }
inline void configure_disass_logger(boost::program_options::variables_map& vm) { inline void configure_disass_logger(boost::program_options::variables_map &vm) {
// el::Logger* disassLogger = el::Loggers::getLogger(disass); // el::Logger* disassLogger = el::Loggers::getLogger(disass);
// el::Configurations disassConf; // el::Configurations disassConf;
// if(vm.count(disass)){ // if(vm.count(disass)){
// auto file_name=vm[disass].as<std::string>(); // auto file_name=vm[disass].as<std::string>();
// disassConf.setToDefault(); // disassConf.setToDefault();
// if (file_name.length() > 0) { // if (file_name.length() > 0) {
// disassConf.set(el::Level::Global, el::ConfigurationType::ToFile, // disassConf.set(el::Level::Global, el::ConfigurationType::ToFile,
// std::string("true")); // std::string("true"));
// disassConf.set(el::Level::Global, // disassConf.set(el::Level::Global,
// el::ConfigurationType::ToStandardOutput, std::string("false")); // el::ConfigurationType::ToStandardOutput,
// disassConf.set(el::Level::Global, el::ConfigurationType::Format, // std::string("false"));
// std::string("%msg")); // disassConf.set(el::Level::Global, el::ConfigurationType::Format,
// disassConf.set(el::Level::Global, el::ConfigurationType::Filename, // std::string("%msg"));
// file_name); // disassConf.set(el::Level::Global,
// std::ofstream str(file_name); // just to clear the file // el::ConfigurationType::Filename,
// } else { // file_name);
// disassConf.set(el::Level::Global, el::ConfigurationType::Format, // std::ofstream str(file_name); // just to clear the file
// "%datetime{%H:%m:%s.%g} [%logger] %msg"); // } else {
// } // disassConf.set(el::Level::Global, el::ConfigurationType::Format,
// } else { // "%datetime{%H:%m:%s.%g} [%logger] %msg");
// enable_log_level(disassConf, 0); // }
// } // } else {
// disassLogger->configure(disassConf); // enable_log_level(disassConf, 0);
// }
// disassLogger->configure(disassConf);
} }
} // namespace } // namespace
inline int parse_cli_options(boost::program_options::variables_map& vm, int argc, char *argv[]){ inline int parse_cli_options(boost::program_options::variables_map &vm, int argc, char *argv[]) {
namespace po = boost::program_options; namespace po = boost::program_options;
po::options_description desc("Options"); po::options_description desc("Options");
desc.add_options() desc.add_options()("help,h", "Print help message")("verbose,v", po::value<int>()->implicit_value(0),
("help,h", "Print help message") "Sets logging verbosity")("vmodule", po::value<std::string>(),
("verbose,v", po::value<int>()->implicit_value(0), "Sets logging verbosity") "Defines the module(s) to be logged")(
("vmodule", po::value<std::string>(),"Defines the module(s) to be logged") "logging-flags", po::value<int>(), "Sets logging flag(s).")("log-file", po::value<std::string>(),
("logging-flags", po::value<int>(),"Sets logging flag(s).") "Sets default log file.")(
("log-file", po::value<std::string>(),"Sets default log file.") "disass,d", po::value<std::string>()->implicit_value(""),
("disass,d", po::value<std::string>()->implicit_value(""),"Enables disassembly") "Enables disassembly")("elf,l", po::value<std::vector<std::string>>(), "ELF file(s) to load")(
("elf,l", po::value< std::vector<std::string> >(), "ELF file(s) to load") "gdb-port,g", po::value<unsigned>(), "enable gdb server and specify port to use")(
("gdb-port,g", po::value<unsigned>(), "enable gdb server and specify port to use") "input,i", po::value<std::string>(), "the elf file to load (instead of hex files)")(
("input,i", po::value<std::string>(), "the elf file to load (instead of hex files)") "dump-ir", "dump the intermediate representation")("cycles,c", po::value<int64_t>()->default_value(-1),
("dump-ir", "dump the intermediate representation") "number of cycles to run")(
("cycles,c", po::value<int64_t>()->default_value(-1), "number of cycles to run") "systemc,s", "Run as SystemC simulation")("time", po::value<int>(), "SystemC siimulation time in ms")(
("systemc,s", "Run as SystemC simulation") "reset,r", po::value<std::string>(), "reset address")(
("time", po::value<int>(), "SystemC siimulation time in ms") "trace", po::value<uint8_t>(), "enable tracing, or cmbintation of 1=signals and 2=TX text, 4=TX "
("reset,r", po::value<std::string>(), "reset address") "compressed text, 6=TX in SQLite")("mem,m", po::value<std::string>(),
("trace", po::value<uint8_t>(), "enable tracing, or cmbintation of 1=signals and 2=TX text, 4=TX compressed text, 6=TX in SQLite")\ "the memory input file")("rv64", "run RV64");
("mem,m", po::value<std::string>(), "the memory input file")
("rv64", "run RV64");
try { try {
po::store(po::parse_command_line(argc, argv, desc), vm); // can throw po::store(po::parse_command_line(argc, argv, desc), vm); // can throw
// --help option // --help option
if ( vm.count("help") ){ if (vm.count("help")) {
std::cout << "DBT-RISE-RiscV" << std::endl << desc << std::endl; std::cout << "DBT-RISE-RiscV" << std::endl << desc << std::endl;
return SUCCESS; return SUCCESS;
} }
po::notify(vm); // throws on error, so do after help in case po::notify(vm); // throws on error, so do after help in case
} catch(po::error& e){ } catch (po::error &e) {
// there are problems // there are problems
std::cerr << "ERROR: " << e.what() << std::endl << std::endl; std::cerr << "ERROR: " << e.what() << std::endl << std::endl;
std::cerr << desc << std::endl; std::cerr << desc << std::endl;

12
riscv.sc/incl/sysc/SiFive/core_complex.h
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@ -1,4 +1,4 @@
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH // Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved. // All rights reserved.
// //
@ -37,25 +37,21 @@
#ifndef _SYSC_SIFIVE_FE310_H_ #ifndef _SYSC_SIFIVE_FE310_H_
#define _SYSC_SIFIVE_FE310_H_ #define _SYSC_SIFIVE_FE310_H_
#include <iss/arch/rv32imac.h>
#include <iss/arch/riscv_hart_msu_vp.h> #include <iss/arch/riscv_hart_msu_vp.h>
#include <tlm> #include <iss/arch/rv32imac.h>
#include <sysc/utilities.h> #include <sysc/utilities.h>
#include <tlm>
namespace sysc { namespace sysc {
namespace SiFive { namespace SiFive {
class core_complex: class core_complex : public iss::arch::riscv_hart_msu_vp<iss::arch::rv32imac>, public sc_core::sc_module {
public iss::arch::riscv_hart_msu_vp<iss::arch::rv32imac>,
public sc_core::sc_module {
public: public:
tlm::tlm_initiator_socket<32> initiator; tlm::tlm_initiator_socket<32> initiator;
sc_core::sc_in<bool> rst_i; sc_core::sc_in<bool> rst_i;
core_complex(sc_core::sc_module_name name); core_complex(sc_core::sc_module_name name);
virtual ~core_complex(); virtual ~core_complex();
}; };
} /* namespace SiFive */ } /* namespace SiFive */

3
riscv.sc/incl/sysc/SiFive/gen/e300_plat_t.h
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@ -1,6 +1,7 @@
#ifndef _E300_PLAT_MAP_H_ #ifndef _E300_PLAT_MAP_H_
#define _E300_PLAT_MAP_H_ #define _E300_PLAT_MAP_H_
// need double braces, see https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191 // need double braces, see
// https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191
const std::array<sysc::target_memory_map_entry<32>, 4> e300_plat_map = {{ const std::array<sysc::target_memory_map_entry<32>, 4> e300_plat_map = {{
{&i_plic, 0xc000000, 0x1000}, {&i_plic, 0xc000000, 0x1000},
{&i_gpio, 0x10012000, 0x1000}, {&i_gpio, 0x10012000, 0x1000},

41
riscv.sc/incl/sysc/SiFive/gen/gpio_regs.h
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@ -36,17 +36,14 @@
#ifndef _GPIO_REGS_H_ #ifndef _GPIO_REGS_H_
#define _GPIO_REGS_H_ #define _GPIO_REGS_H_
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include <sysc/register.h> #include <sysc/register.h>
#include <sysc/tlm_target.h> #include <sysc/tlm_target.h>
#include <sysc/utilities.h>
#include <util/bit_field.h>
namespace sysc { namespace sysc {
class gpio_regs : class gpio_regs : public sc_core::sc_module, public sysc::resetable {
public sc_core::sc_module,
public sysc::resetable
{
protected: protected:
// storage declarations // storage declarations
uint32_t r_value; uint32_t r_value;
@ -105,8 +102,7 @@ protected:
public: public:
gpio_regs(sc_core::sc_module_name nm); gpio_regs(sc_core::sc_module_name nm);
template<unsigned BUSWIDTH=32> template <unsigned BUSWIDTH = 32> void registerResources(sysc::tlm_target<BUSWIDTH> &target);
void registerResources(sysc::tlm_target<BUSWIDTH>& target);
}; };
} }
////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////
@ -114,29 +110,14 @@ public:
////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////
inline sysc::gpio_regs::gpio_regs(sc_core::sc_module_name nm) inline sysc::gpio_regs::gpio_regs(sc_core::sc_module_name nm)
: sc_core::sc_module(nm) : sc_core::sc_module(nm), NAMED(value, r_value, 0, *this), NAMED(input_en, r_input_en, 0, *this),
, NAMED(value, r_value, 0, *this) NAMED(output_en, r_output_en, 0, *this), NAMED(port, r_port, 0, *this), NAMED(pue, r_pue, 0, *this),
, NAMED(input_en, r_input_en, 0, *this) NAMED(ds, r_ds, 0, *this), NAMED(rise_ie, r_rise_ie, 0, *this), NAMED(rise_ip, r_rise_ip, 0, *this),
, NAMED(output_en, r_output_en, 0, *this) NAMED(fall_ie, r_fall_ie, 0, *this), NAMED(fall_ip, r_fall_ip, 0, *this), NAMED(high_ie, r_high_ie, 0, *this),
, NAMED(port, r_port, 0, *this) NAMED(high_ip, r_high_ip, 0, *this), NAMED(low_ie, r_low_ie, 0, *this), NAMED(low_ip, r_low_ip, 0, *this),
, NAMED(pue, r_pue, 0, *this) NAMED(iof_en, r_iof_en, 0, *this), NAMED(iof_sel, r_iof_sel, 0, *this), NAMED(out_xor, r_out_xor, 0, *this) {}
, NAMED(ds, r_ds, 0, *this)
, NAMED(rise_ie, r_rise_ie, 0, *this)
, NAMED(rise_ip, r_rise_ip, 0, *this)
, NAMED(fall_ie, r_fall_ie, 0, *this)
, NAMED(fall_ip, r_fall_ip, 0, *this)
, NAMED(high_ie, r_high_ie, 0, *this)
, NAMED(high_ip, r_high_ip, 0, *this)
, NAMED(low_ie, r_low_ie, 0, *this)
, NAMED(low_ip, r_low_ip, 0, *this)
, NAMED(iof_en, r_iof_en, 0, *this)
, NAMED(iof_sel, r_iof_sel, 0, *this)
, NAMED(out_xor, r_out_xor, 0, *this)
{
}
template<unsigned BUSWIDTH> template <unsigned BUSWIDTH> inline void sysc::gpio_regs::registerResources(sysc::tlm_target<BUSWIDTH> &target) {
inline void sysc::gpio_regs::registerResources(sysc::tlm_target<BUSWIDTH>& target) {
target.addResource(value, 0x0UL); target.addResource(value, 0x0UL);
target.addResource(input_en, 0x4UL); target.addResource(input_en, 0x4UL);
target.addResource(output_en, 0x8UL); target.addResource(output_en, 0x8UL);

28
riscv.sc/incl/sysc/SiFive/gen/plic_regs.h
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@ -36,22 +36,19 @@
#ifndef _PLIC_REGS_H_ #ifndef _PLIC_REGS_H_
#define _PLIC_REGS_H_ #define _PLIC_REGS_H_
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include <sysc/register.h> #include <sysc/register.h>
#include <sysc/tlm_target.h> #include <sysc/tlm_target.h>
#include <sysc/utilities.h>
#include <util/bit_field.h>
namespace sysc { namespace sysc {
class plic_regs : class plic_regs : public sc_core::sc_module, public sysc::resetable {
public sc_core::sc_module,
public sysc::resetable
{
protected: protected:
// storage declarations // storage declarations
BEGIN_BF_DECL(priority_t, uint32_t); BEGIN_BF_DECL(priority_t, uint32_t);
BF_FIELD(priority, 0, 3); BF_FIELD(priority, 0, 3);
END_BF_DECL() ; END_BF_DECL();
std::array<priority_t, 255> r_priority; std::array<priority_t, 255> r_priority;
uint32_t r_pending; uint32_t r_pending;
@ -74,8 +71,7 @@ protected:
public: public:
plic_regs(sc_core::sc_module_name nm); plic_regs(sc_core::sc_module_name nm);
template<unsigned BUSWIDTH=32> template <unsigned BUSWIDTH = 32> void registerResources(sysc::tlm_target<BUSWIDTH> &target);
void registerResources(sysc::tlm_target<BUSWIDTH>& target);
}; };
} }
////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////
@ -83,17 +79,11 @@ public:
////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////
inline sysc::plic_regs::plic_regs(sc_core::sc_module_name nm) inline sysc::plic_regs::plic_regs(sc_core::sc_module_name nm)
: sc_core::sc_module(nm) : sc_core::sc_module(nm), NAMED(priority, r_priority, 0, *this), NAMED(pending, r_pending, 0, *this),
, NAMED(priority, r_priority, 0, *this) NAMED(enabled, r_enabled, 0, *this), NAMED(threshold, r_threshold, 0, *this),
, NAMED(pending, r_pending, 0, *this) NAMED(claim_complete, r_claim_complete, 0, *this) {}
, NAMED(enabled, r_enabled, 0, *this)
, NAMED(threshold, r_threshold, 0, *this)
, NAMED(claim_complete, r_claim_complete, 0, *this)
{
}
template<unsigned BUSWIDTH> template <unsigned BUSWIDTH> inline void sysc::plic_regs::registerResources(sysc::tlm_target<BUSWIDTH> &target) {
inline void sysc::plic_regs::registerResources(sysc::tlm_target<BUSWIDTH>& target) {
target.addResource(priority, 0x4UL); target.addResource(priority, 0x4UL);
target.addResource(pending, 0x1000UL); target.addResource(pending, 0x1000UL);
target.addResource(enabled, 0x2000UL); target.addResource(enabled, 0x2000UL);

40
riscv.sc/incl/sysc/SiFive/gen/spi_regs.h
View File

@ -36,17 +36,14 @@
#ifndef _SPI_REGS_H_ #ifndef _SPI_REGS_H_
#define _SPI_REGS_H_ #define _SPI_REGS_H_
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include <sysc/register.h> #include <sysc/register.h>
#include <sysc/tlm_target.h> #include <sysc/tlm_target.h>
#include <sysc/utilities.h>
#include <util/bit_field.h>
namespace sysc { namespace sysc {
class spi_regs : class spi_regs : public sc_core::sc_module, public sysc::resetable {
public sc_core::sc_module,
public sysc::resetable
{
protected: protected:
// storage declarations // storage declarations
BEGIN_BF_DECL(sckdiv_t, uint32_t); BEGIN_BF_DECL(sckdiv_t, uint32_t);
@ -147,8 +144,7 @@ protected:
public: public:
spi_regs(sc_core::sc_module_name nm); spi_regs(sc_core::sc_module_name nm);
template<unsigned BUSWIDTH=32> template <unsigned BUSWIDTH = 32> void registerResources(sysc::tlm_target<BUSWIDTH> &target);
void registerResources(sysc::tlm_target<BUSWIDTH>& target);
}; };
} }
////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////
@ -156,28 +152,14 @@ public:
////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////
inline sysc::spi_regs::spi_regs(sc_core::sc_module_name nm) inline sysc::spi_regs::spi_regs(sc_core::sc_module_name nm)
: sc_core::sc_module(nm) : sc_core::sc_module(nm), NAMED(sckdiv, r_sckdiv, 0, *this), NAMED(sckmode, r_sckmode, 0, *this),
, NAMED(sckdiv, r_sckdiv, 0, *this) NAMED(csid, r_csid, 0, *this), NAMED(csdef, r_csdef, 0, *this), NAMED(csmode, r_csmode, 0, *this),
, NAMED(sckmode, r_sckmode, 0, *this) NAMED(delay0, r_delay0, 0, *this), NAMED(delay1, r_delay1, 0, *this), NAMED(fmt, r_fmt, 0, *this),
, NAMED(csid, r_csid, 0, *this) NAMED(txdata, r_txdata, 0, *this), NAMED(rxdata, r_rxdata, 0, *this), NAMED(txmark, r_txmark, 0, *this),
, NAMED(csdef, r_csdef, 0, *this) NAMED(rxmark, r_rxmark, 0, *this), NAMED(fctrl, r_fctrl, 0, *this), NAMED(ffmt, r_ffmt, 0, *this),
, NAMED(csmode, r_csmode, 0, *this) NAMED(ie, r_ie, 0, *this), NAMED(ip, r_ip, 0, *this) {}
, NAMED(delay0, r_delay0, 0, *this)
, NAMED(delay1, r_delay1, 0, *this)
, NAMED(fmt, r_fmt, 0, *this)
, NAMED(txdata, r_txdata, 0, *this)
, NAMED(rxdata, r_rxdata, 0, *this)
, NAMED(txmark, r_txmark, 0, *this)
, NAMED(rxmark, r_rxmark, 0, *this)
, NAMED(fctrl, r_fctrl, 0, *this)
, NAMED(ffmt, r_ffmt, 0, *this)
, NAMED(ie, r_ie, 0, *this)
, NAMED(ip, r_ip, 0, *this)
{
}
template<unsigned BUSWIDTH> template <unsigned BUSWIDTH> inline void sysc::spi_regs::registerResources(sysc::tlm_target<BUSWIDTH> &target) {
inline void sysc::spi_regs::registerResources(sysc::tlm_target<BUSWIDTH>& target) {
target.addResource(sckdiv, 0x0UL); target.addResource(sckdiv, 0x0UL);
target.addResource(sckmode, 0x4UL); target.addResource(sckmode, 0x4UL);
target.addResource(csid, 0x10UL); target.addResource(csid, 0x10UL);

28
riscv.sc/incl/sysc/SiFive/gen/uart_regs.h
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@ -36,17 +36,14 @@
#ifndef _UART_REGS_H_ #ifndef _UART_REGS_H_
#define _UART_REGS_H_ #define _UART_REGS_H_
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include <sysc/register.h> #include <sysc/register.h>
#include <sysc/tlm_target.h> #include <sysc/tlm_target.h>
#include <sysc/utilities.h>
#include <util/bit_field.h>
namespace sysc { namespace sysc {
class uart_regs : class uart_regs : public sc_core::sc_module, public sysc::resetable {
public sc_core::sc_module,
public sysc::resetable
{
protected: protected:
// storage declarations // storage declarations
BEGIN_BF_DECL(txdata_t, uint32_t); BEGIN_BF_DECL(txdata_t, uint32_t);
@ -98,8 +95,7 @@ protected:
public: public:
uart_regs(sc_core::sc_module_name nm); uart_regs(sc_core::sc_module_name nm);
template<unsigned BUSWIDTH=32> template <unsigned BUSWIDTH = 32> void registerResources(sysc::tlm_target<BUSWIDTH> &target);
void registerResources(sysc::tlm_target<BUSWIDTH>& target);
}; };
} }
////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////
@ -107,19 +103,11 @@ public:
////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////
inline sysc::uart_regs::uart_regs(sc_core::sc_module_name nm) inline sysc::uart_regs::uart_regs(sc_core::sc_module_name nm)
: sc_core::sc_module(nm) : sc_core::sc_module(nm), NAMED(txdata, r_txdata, 0, *this), NAMED(rxdata, r_rxdata, 0, *this),
, NAMED(txdata, r_txdata, 0, *this) NAMED(txctrl, r_txctrl, 0, *this), NAMED(rxctrl, r_rxctrl, 0, *this), NAMED(ie, r_ie, 0, *this),
, NAMED(rxdata, r_rxdata, 0, *this) NAMED(ip, r_ip, 0, *this), NAMED(div, r_div, 0, *this) {}
, NAMED(txctrl, r_txctrl, 0, *this)
, NAMED(rxctrl, r_rxctrl, 0, *this)
, NAMED(ie, r_ie, 0, *this)
, NAMED(ip, r_ip, 0, *this)
, NAMED(div, r_div, 0, *this)
{
}
template<unsigned BUSWIDTH> template <unsigned BUSWIDTH> inline void sysc::uart_regs::registerResources(sysc::tlm_target<BUSWIDTH> &target) {
inline void sysc::uart_regs::registerResources(sysc::tlm_target<BUSWIDTH>& target) {
target.addResource(txdata, 0x0UL); target.addResource(txdata, 0x0UL);
target.addResource(rxdata, 0x4UL); target.addResource(rxdata, 0x4UL);
target.addResource(txctrl, 0x8UL); target.addResource(txctrl, 0x8UL);

3
riscv.sc/incl/sysc/SiFive/gpio.h
View File

@ -23,13 +23,14 @@ namespace sysc {
class gpio_regs; class gpio_regs;
class gpio: public sc_core::sc_module, public tlm_target<> { class gpio : public sc_core::sc_module, public tlm_target<> {
public: public:
SC_HAS_PROCESS(gpio); SC_HAS_PROCESS(gpio);
sc_core::sc_in<sc_core::sc_time> clk_i; sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i; sc_core::sc_in<bool> rst_i;
gpio(sc_core::sc_module_name nm); gpio(sc_core::sc_module_name nm);
virtual ~gpio(); virtual ~gpio();
protected: protected:
void clock_cb(); void clock_cb();
void reset_cb(); void reset_cb();

12
riscv.sc/incl/sysc/SiFive/platform.h
View File

@ -23,21 +23,20 @@
#ifndef SIMPLESYSTEM_H_ #ifndef SIMPLESYSTEM_H_
#define SIMPLESYSTEM_H_ #define SIMPLESYSTEM_H_
#include "uart.h"
#include "spi.h"
#include "gpio.h" #include "gpio.h"
#include "plic.h" #include "plic.h"
#include "spi.h"
#include "uart.h"
#include <sysc/router.h>
#include <sysc/kernel/sc_module.h>
#include <array> #include <array>
#include <sysc/kernel/sc_module.h>
#include <sysc/router.h>
#include "core_complex.h" #include "core_complex.h"
namespace sysc { namespace sysc {
class platform: public sc_core::sc_module { class platform : public sc_core::sc_module {
public: public:
SC_HAS_PROCESS(platform); SC_HAS_PROCESS(platform);
@ -51,6 +50,7 @@ public:
sc_core::sc_signal<bool> s_rst; sc_core::sc_signal<bool> s_rst;
platform(sc_core::sc_module_name nm); platform(sc_core::sc_module_name nm);
protected: protected:
void gen_reset(); void gen_reset();

3
riscv.sc/incl/sysc/SiFive/plic.h
View File

@ -23,13 +23,14 @@ namespace sysc {
class plic_regs; class plic_regs;
class plic: public sc_core::sc_module, public tlm_target<> { class plic : public sc_core::sc_module, public tlm_target<> {
public: public:
SC_HAS_PROCESS(plic); SC_HAS_PROCESS(plic);
sc_core::sc_in<sc_core::sc_time> clk_i; sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i; sc_core::sc_in<bool> rst_i;
plic(sc_core::sc_module_name nm); plic(sc_core::sc_module_name nm);
virtual ~plic(); virtual ~plic();
protected: protected:
void clock_cb(); void clock_cb();
void reset_cb(); void reset_cb();

3
riscv.sc/incl/sysc/SiFive/spi.h
View File

@ -23,13 +23,14 @@ namespace sysc {
class spi_regs; class spi_regs;
class spi: public sc_core::sc_module, public tlm_target<> { class spi : public sc_core::sc_module, public tlm_target<> {
public: public:
SC_HAS_PROCESS(spi); SC_HAS_PROCESS(spi);
sc_core::sc_in<sc_core::sc_time> clk_i; sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i; sc_core::sc_in<bool> rst_i;
spi(sc_core::sc_module_name nm); spi(sc_core::sc_module_name nm);
virtual ~spi(); virtual ~spi();
protected: protected:
void clock_cb(); void clock_cb();
void reset_cb(); void reset_cb();

3
riscv.sc/incl/sysc/SiFive/uart.h
View File

@ -23,13 +23,14 @@ namespace sysc {
class uart_regs; class uart_regs;
class uart: public sc_core::sc_module, public tlm_target<> { class uart : public sc_core::sc_module, public tlm_target<> {
public: public:
SC_HAS_PROCESS(uart); SC_HAS_PROCESS(uart);
sc_core::sc_in<sc_core::sc_time> clk_i; sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i; sc_core::sc_in<bool> rst_i;
uart(sc_core::sc_module_name nm); uart(sc_core::sc_module_name nm);
virtual ~uart(); virtual ~uart();
protected: protected:
void clock_cb(); void clock_cb();
void reset_cb(); void reset_cb();

32
riscv.sc/src/sc_main.cpp
View File

@ -20,13 +20,13 @@
* Author: eyck@minres.com * Author: eyck@minres.com
*/ */
#include <sysc/tracer.h>
#include <sysc/scv_tr_db.h>
#include <sr_report/sr_report.h>
#include <boost/program_options.hpp> #include <boost/program_options.hpp>
#include <sysc/report.h> #include <sr_report/sr_report.h>
#include <sstream> #include <sstream>
#include <sysc/SiFive/platform.h> #include <sysc/SiFive/platform.h>
#include <sysc/report.h>
#include <sysc/scv_tr_db.h>
#include <sysc/tracer.h>
using namespace sysc; using namespace sysc;
namespace po = boost::program_options; namespace po = boost::program_options;
@ -37,28 +37,26 @@ const size_t SUCCESS = 0;
const size_t ERROR_UNHANDLED_EXCEPTION = 2; const size_t ERROR_UNHANDLED_EXCEPTION = 2;
} // namespace } // namespace
int sc_main(int argc, char* argv[]){ int sc_main(int argc, char *argv[]) {
// sc_report_handler::set_handler(my_report_handler); // sc_report_handler::set_handler(my_report_handler);
sysc::Logger::reporting_level()=log::DEBUG; sysc::Logger::reporting_level() = log::DEBUG;
/////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////
// CLI argument parsing // CLI argument parsing
/////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////
po::options_description desc("Options");\ po::options_description desc("Options");
desc.add_options()\ desc.add_options()("help,h", "Print help message")("debug,d", po::value<int>(),
("help,h", "Print help message")\ "set debug level")("trace,t", "trace SystemC signals");
("debug,d", po::value<int>(), "set debug level")\
("trace,t", "trace SystemC signals");
po::variables_map vm; po::variables_map vm;
try { try {
po::store(po::parse_command_line(argc, argv, desc), vm); // can throw po::store(po::parse_command_line(argc, argv, desc), vm); // can throw
// --help option // --help option
if ( vm.count("help") ){ if (vm.count("help")) {
std::cout << "JIT-ISS simulator for AVR" << std::endl << desc << std::endl; std::cout << "JIT-ISS simulator for AVR" << std::endl << desc << std::endl;
return SUCCESS; return SUCCESS;
} }
po::notify(vm); // throws on error, so do after help in case po::notify(vm); // throws on error, so do after help in case
// there are any problems // there are any problems
} catch(po::error& e){ } catch (po::error &e) {
std::cerr << "ERROR: " << e.what() << std::endl << std::endl; std::cerr << "ERROR: " << e.what() << std::endl << std::endl;
std::cerr << desc << std::endl; std::cerr << desc << std::endl;
return ERROR_IN_COMMAND_LINE; return ERROR_IN_COMMAND_LINE;
@ -71,13 +69,13 @@ int sc_main(int argc, char* argv[]){
// instantiate top level // instantiate top level
/////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////
platform i_simple_system("i_simple_system"); platform i_simple_system("i_simple_system");
//sr_report_handler::add_sc_object_to_filter(&i_simple_system.i_master, sc_core::SC_WARNING, sc_core::SC_MEDIUM); // sr_report_handler::add_sc_object_to_filter(&i_simple_system.i_master,
// sc_core::SC_WARNING, sc_core::SC_MEDIUM);
/////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////
// run simulation // run simulation
/////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////
sc_start(sc_core::sc_time(100, sc_core::SC_NS)); sc_start(sc_core::sc_time(100, sc_core::SC_NS));
if(!sc_end_of_simulation_invoked()) sc_stop(); if (!sc_end_of_simulation_invoked()) sc_stop();
return 0; return 0;
} }

6
riscv.sc/src/sysc/core_complex.cpp
View File

@ -39,12 +39,8 @@
namespace sysc { namespace sysc {
namespace SiFive { namespace SiFive {
core_complex::core_complex(sc_core::sc_module_name name) core_complex::core_complex(sc_core::sc_module_name name) : sc_core::sc_module(name), NAMED(initiator), NAMED(rst_i) {
:sc_core::sc_module(name)
, NAMED(initiator)
, NAMED(rst_i){
// TODO Auto-generated constructor stub // TODO Auto-generated constructor stub
} }
core_complex::~core_complex() { core_complex::~core_complex() {

19
riscv.sc/src/sysc/gpio.cpp
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@ -21,27 +21,20 @@
namespace sysc { namespace sysc {
gpio::gpio(sc_core::sc_module_name nm) gpio::gpio(sc_core::sc_module_name nm)
: sc_core::sc_module(nm) : sc_core::sc_module(nm), tlm_target<>(clk), NAMED(clk_i), NAMED(rst_i), NAMEDD(gpio_regs, regs) {
, tlm_target<>(clk)
, NAMED(clk_i)
, NAMED(rst_i)
, NAMEDD(gpio_regs, regs)
{
regs->registerResources(*this); regs->registerResources(*this);
SC_METHOD(clock_cb); SC_METHOD(clock_cb);
sensitive<<clk_i; sensitive << clk_i;
SC_METHOD(reset_cb); SC_METHOD(reset_cb);
sensitive<<rst_i; sensitive << rst_i;
} }
gpio::~gpio() { gpio::~gpio() {}
}
void gpio::clock_cb() { void gpio::clock_cb() {}
}
void gpio::reset_cb() { void gpio::reset_cb() {
if(rst_i.read()) if (rst_i.read())
regs->reset_start(); regs->reset_start();
else else
regs->reset_stop(); regs->reset_stop();

20
riscv.sc/src/sysc/platform.cpp
View File

@ -25,19 +25,11 @@
namespace sysc { namespace sysc {
platform::platform(sc_core::sc_module_name nm) platform::platform(sc_core::sc_module_name nm)
: sc_core::sc_module(nm) : sc_core::sc_module(nm), NAMED(i_master), NAMED(i_router, 4, 1), NAMED(i_uart), NAMED(i_spi), NAMED(i_gpio),
, NAMED(i_master) NAMED(i_plic), NAMED(s_clk), NAMED(s_rst) {
, NAMED(i_router, 4, 1)
, NAMED(i_uart)
, NAMED(i_spi)
, NAMED(i_gpio)
, NAMED(i_plic)
, NAMED(s_clk)
, NAMED(s_rst)
{
i_master.initiator(i_router.target[0]); i_master.initiator(i_router.target[0]);
size_t i=0; size_t i = 0;
for(const auto& e: e300_plat_map){ for (const auto &e : e300_plat_map) {
i_router.initiator.at(i)(e.target->socket); i_router.initiator.at(i)(e.target->socket);
i_router.add_target_range(i, e.start, e.size); i_router.add_target_range(i, e.start, e.size);
i++; i++;
@ -58,9 +50,9 @@ platform::platform(sc_core::sc_module_name nm)
} }
void platform::gen_reset() { void platform::gen_reset() {
s_rst=true; s_rst = true;
wait(10_ns); wait(10_ns);
s_rst=false; s_rst = false;
} }
} /* namespace sysc */ } /* namespace sysc */

20
riscv.sc/src/sysc/plic.cpp
View File

@ -21,28 +21,20 @@
namespace sysc { namespace sysc {
plic::plic(sc_core::sc_module_name nm) plic::plic(sc_core::sc_module_name nm)
: sc_core::sc_module(nm) : sc_core::sc_module(nm), tlm_target<>(clk), NAMED(clk_i), NAMED(rst_i), NAMEDD(plic_regs, regs) {
, tlm_target<>(clk)
, NAMED(clk_i)
, NAMED(rst_i)
, NAMEDD(plic_regs, regs)
{
regs->registerResources(*this); regs->registerResources(*this);
SC_METHOD(clock_cb); SC_METHOD(clock_cb);
sensitive<<clk_i; sensitive << clk_i;
SC_METHOD(reset_cb); SC_METHOD(reset_cb);
sensitive<<rst_i; sensitive << rst_i;
} }
plic::~plic() { plic::~plic() {}
}
void plic::clock_cb() { void plic::clock_cb() { this->clk = clk_i.read(); }
this->clk=clk_i.read();
}
void plic::reset_cb() { void plic::reset_cb() {
if(rst_i.read()) if (rst_i.read())
regs->reset_start(); regs->reset_start();
else else
regs->reset_stop(); regs->reset_stop();

20
riscv.sc/src/sysc/spi.cpp
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@ -21,28 +21,20 @@
namespace sysc { namespace sysc {
spi::spi(sc_core::sc_module_name nm) spi::spi(sc_core::sc_module_name nm)
: sc_core::sc_module(nm) : sc_core::sc_module(nm), tlm_target<>(clk), NAMED(clk_i), NAMED(rst_i), NAMEDD(spi_regs, regs) {
, tlm_target<>(clk)
, NAMED(clk_i)
, NAMED(rst_i)
, NAMEDD(spi_regs, regs)
{
regs->registerResources(*this); regs->registerResources(*this);
SC_METHOD(clock_cb); SC_METHOD(clock_cb);
sensitive<<clk_i; sensitive << clk_i;
SC_METHOD(reset_cb); SC_METHOD(reset_cb);
sensitive<<rst_i; sensitive << rst_i;
} }
spi::~spi() { spi::~spi() {}
}
void spi::clock_cb() { void spi::clock_cb() { this->clk = clk_i.read(); }
this->clk=clk_i.read();
}
void spi::reset_cb() { void spi::reset_cb() {
if(rst_i.read()) if (rst_i.read())
regs->reset_start(); regs->reset_start();
else else
regs->reset_stop(); regs->reset_stop();

20
riscv.sc/src/sysc/uart.cpp
View File

@ -21,28 +21,20 @@
namespace sysc { namespace sysc {
uart::uart(sc_core::sc_module_name nm) uart::uart(sc_core::sc_module_name nm)
: sc_core::sc_module(nm) : sc_core::sc_module(nm), tlm_target<>(clk), NAMED(clk_i), NAMED(rst_i), NAMEDD(uart_regs, regs) {
, tlm_target<>(clk)
, NAMED(clk_i)
, NAMED(rst_i)
, NAMEDD(uart_regs, regs)
{
regs->registerResources(*this); regs->registerResources(*this);
SC_METHOD(clock_cb); SC_METHOD(clock_cb);
sensitive<<clk_i; sensitive << clk_i;
SC_METHOD(reset_cb); SC_METHOD(reset_cb);
sensitive<<rst_i; sensitive << rst_i;
} }
uart::~uart() { uart::~uart() {}
}
void uart::clock_cb() { void uart::clock_cb() { this->clk = clk_i.read(); }
this->clk=clk_i.read();
}
void uart::reset_cb() { void uart::reset_cb() {
if(rst_i.read()) if (rst_i.read())
regs->reset_start(); regs->reset_start();
else else
regs->reset_stop(); regs->reset_stop();

44
riscv/incl/cli_options.h
View File

@ -35,44 +35,42 @@
#ifndef _CLI_OPTIONS_H_ #ifndef _CLI_OPTIONS_H_
#define _CLI_OPTIONS_H_ #define _CLI_OPTIONS_H_
#include <boost/program_options.hpp> #include <boost/program_options.hpp>
#include <util/logging.h>
#include <iostream>
#include <cstdio> #include <cstdio>
#include <iostream>
#include <util/logging.h>
const size_t ERROR_IN_COMMAND_LINE = 1; const size_t ERROR_IN_COMMAND_LINE = 1;
const size_t SUCCESS = 0; const size_t SUCCESS = 0;
const size_t ERROR_UNHANDLED_EXCEPTION = 2; const size_t ERROR_UNHANDLED_EXCEPTION = 2;
inline int parse_cli_options(boost::program_options::variables_map& vm, int argc, char *argv[]){ inline int parse_cli_options(boost::program_options::variables_map &vm, int argc, char *argv[]) {
namespace po = boost::program_options; namespace po = boost::program_options;
po::options_description desc("Options"); po::options_description desc("Options");
desc.add_options() desc.add_options()("help,h", "Print help message")("verbose,v", po::value<int>()->implicit_value(0),
("help,h", "Print help message") "Sets logging verbosity")("vmodule", po::value<std::string>(),
("verbose,v", po::value<int>()->implicit_value(0), "Sets logging verbosity") "Defines the module(s) to be logged")(
("vmodule", po::value<std::string>(),"Defines the module(s) to be logged") "logging-flags", po::value<int>(), "Sets logging flag(s).")("log-file", po::value<std::string>(),
("logging-flags", po::value<int>(),"Sets logging flag(s).") "Sets default log file.")(
("log-file", po::value<std::string>(),"Sets default log file.") "disass,d", po::value<std::string>()->implicit_value(""),
("disass,d", po::value<std::string>()->implicit_value(""),"Enables disassembly") "Enables disassembly")("elf,l", po::value<std::vector<std::string>>(), "ELF file(s) to load")(
("elf,l", po::value< std::vector<std::string> >(), "ELF file(s) to load") "gdb-port,g", po::value<unsigned>(), "enable gdb server and specify port to use")(
("gdb-port,g", po::value<unsigned>(), "enable gdb server and specify port to use") "input,i", po::value<std::string>(), "the elf file to load (instead of hex files)")(
("input,i", po::value<std::string>(), "the elf file to load (instead of hex files)") "dump-ir", "dump the intermediate representation")("cycles,c", po::value<int64_t>()->default_value(-1),
("dump-ir", "dump the intermediate representation") "number of cycles to run")(
("cycles,c", po::value<int64_t>()->default_value(-1), "number of cycles to run") "systemc,s", "Run as SystemC simulation")("time", po::value<int>(), "SystemC siimulation time in ms")(
("systemc,s", "Run as SystemC simulation") "reset,r", po::value<std::string>(), "reset address")(
("time", po::value<int>(), "SystemC siimulation time in ms") "trace", po::value<uint8_t>(), "enable tracing, or cmbintation of 1=signals and 2=TX text, 4=TX "
("reset,r", po::value<std::string>(), "reset address") "compressed text, 6=TX in SQLite")("mem,m", po::value<std::string>(),
("trace", po::value<uint8_t>(), "enable tracing, or cmbintation of 1=signals and 2=TX text, 4=TX compressed text, 6=TX in SQLite")\ "the memory input file")("rv64", "run RV64");
("mem,m", po::value<std::string>(), "the memory input file")
("rv64", "run RV64");
try { try {
po::store(po::parse_command_line(argc, argv, desc), vm); // can throw po::store(po::parse_command_line(argc, argv, desc), vm); // can throw
// --help option // --help option
if ( vm.count("help") ){ if (vm.count("help")) {
std::cout << "DBT-RISE-RiscV" << std::endl << desc << std::endl; std::cout << "DBT-RISE-RiscV" << std::endl << desc << std::endl;
return SUCCESS; return SUCCESS;
} }
po::notify(vm); // throws on error, so do after help in case po::notify(vm); // throws on error, so do after help in case
} catch(po::error& e){ } catch (po::error &e) {
// there are problems // there are problems
std::cerr << "ERROR: " << e.what() << std::endl << std::endl; std::cerr << "ERROR: " << e.what() << std::endl << std::endl;
std::cerr << desc << std::endl; std::cerr << desc << std::endl;

1312
riscv/incl/iss/arch/riscv_hart_msu_vp.h
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65
riscv/incl/iss/arch/rv32imac.h
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@ -36,19 +36,30 @@
#ifndef _RV32IMAC_H_ #ifndef _RV32IMAC_H_
#define _RV32IMAC_H_ #define _RV32IMAC_H_
#include <iss/arch/traits.h>
#include <iss/arch_if.h> #include <iss/arch_if.h>
#include <iss/vm_if.h> #include <iss/vm_if.h>
#include <iss/arch/traits.h>
namespace iss { namespace iss {
namespace arch { namespace arch {
struct rv32imac; struct rv32imac;
template<> template <> struct traits<rv32imac> {
struct traits<rv32imac> {
enum constants {XLEN=32,XLEN2=64,XLEN_BIT_MASK=31,PCLEN=32,fence=0,fencei=1,fencevmal=2,fencevmau=3,MISA_VAL=1075056897,PGSIZE=4096,PGMASK=4095}; enum constants {
XLEN = 32,
XLEN2 = 64,
XLEN_BIT_MASK = 31,
PCLEN = 32,
fence = 0,
fencei = 1,
fencevmal = 2,
fencevmau = 3,
MISA_VAL = 1075056897,
PGSIZE = 4096,
PGMASK = 4095
};
enum reg_e { enum reg_e {
X0, X0,
@ -85,7 +96,7 @@ struct traits<rv32imac> {
X31, X31,
PC, PC,
NUM_REGS, NUM_REGS,
NEXT_PC=NUM_REGS, NEXT_PC = NUM_REGS,
TRAP_STATE, TRAP_STATE,
PENDING_TRAP, PENDING_TRAP,
MACHINE_STATE, MACHINE_STATE,
@ -96,29 +107,32 @@ struct traits<rv32imac> {
typedef uint32_t addr_t; typedef uint32_t addr_t;
typedef uint32_t code_word_t; //TODO: check removal typedef uint32_t code_word_t; // TODO: check removal
typedef iss::typed_addr_t<iss::VIRTUAL> virt_addr_t; typedef iss::typed_addr_t<iss::VIRTUAL> virt_addr_t;
typedef iss::typed_addr_t<iss::PHYSICAL> phys_addr_t; typedef iss::typed_addr_t<iss::PHYSICAL> phys_addr_t;
constexpr static unsigned reg_bit_width(unsigned r) { constexpr static unsigned reg_bit_width(unsigned r) {
const uint32_t RV32IMAC_reg_size[] = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64}; const uint32_t RV32IMAC_reg_size[] = {32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 64};
return RV32IMAC_reg_size[r]; return RV32IMAC_reg_size[r];
} }
constexpr static unsigned reg_byte_offset(unsigned r) { constexpr static unsigned reg_byte_offset(unsigned r) {
const uint32_t RV32IMAC_reg_byte_offset[] = {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,152,160}; const uint32_t RV32IMAC_reg_byte_offset[] = {0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48,
52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 96, 100,
104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 152, 160};
return RV32IMAC_reg_byte_offset[r]; return RV32IMAC_reg_byte_offset[r];
} }
enum sreg_flag_e {FLAGS}; enum sreg_flag_e { FLAGS };
enum mem_type_e {MEM,CSR,FENCE,RES};
enum mem_type_e { MEM, CSR, FENCE, RES };
}; };
struct rv32imac: public arch_if { struct rv32imac : public arch_if {
using virt_addr_t = typename traits<rv32imac>::virt_addr_t; using virt_addr_t = typename traits<rv32imac>::virt_addr_t;
using phys_addr_t = typename traits<rv32imac>::phys_addr_t; using phys_addr_t = typename traits<rv32imac>::phys_addr_t;
@ -128,29 +142,29 @@ struct rv32imac: public arch_if {
rv32imac(); rv32imac();
~rv32imac(); ~rv32imac();
virtual void reset(uint64_t address=0) override; virtual void reset(uint64_t address = 0) override;
virtual uint8_t* get_regs_base_ptr() override; virtual uint8_t *get_regs_base_ptr() override;
/// deprecated /// deprecated
virtual void get_reg(short idx, std::vector<uint8_t>& value) override {} virtual void get_reg(short idx, std::vector<uint8_t> &value) override {}
virtual void set_reg(short idx, const std::vector<uint8_t>& value) override {} virtual void set_reg(short idx, const std::vector<uint8_t> &value) override {}
/// deprecated /// deprecated
virtual bool get_flag(int flag) override {return false;} virtual bool get_flag(int flag) override { return false; }
virtual void set_flag(int, bool value) override {}; virtual void set_flag(int, bool value) override{};
/// deprecated /// deprecated
virtual void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {}; virtual void update_flags(operations op, uint64_t opr1, uint64_t opr2) override{};
virtual void notify_phase(exec_phase phase){ virtual void notify_phase(exec_phase phase) {
if(phase==ISTART){ if (phase == ISTART) {
++reg.icount; ++reg.icount;
reg.PC=reg.NEXT_PC; reg.PC = reg.NEXT_PC;
reg.trap_state=reg.pending_trap; reg.trap_state = reg.pending_trap;
} }
} }
uint64_t get_icount() { return reg.icount;} uint64_t get_icount() { return reg.icount; }
virtual phys_addr_t v2p(const iss::addr_t& pc); virtual phys_addr_t v2p(const iss::addr_t &pc);
virtual iss::sync_type needed_sync() const { return iss::PRE_SYNC; } virtual iss::sync_type needed_sync() const { return iss::PRE_SYNC; }
@ -194,7 +208,6 @@ protected:
uint64_t icount; uint64_t icount;
} reg; } reg;
}; };
} }
} }
#endif /* _RV32IMAC_H_ */ #endif /* _RV32IMAC_H_ */

64
riscv/incl/iss/arch/rv64ia.h
View File

@ -36,19 +36,30 @@
#ifndef _RV64IA_H_ #ifndef _RV64IA_H_
#define _RV64IA_H_ #define _RV64IA_H_
#include <iss/arch/traits.h>
#include <iss/arch_if.h> #include <iss/arch_if.h>
#include <iss/vm_if.h> #include <iss/vm_if.h>
#include <iss/arch/traits.h>
namespace iss { namespace iss {
namespace arch { namespace arch {
struct rv64ia; struct rv64ia;
template<> template <> struct traits<rv64ia> {
struct traits<rv64ia> {
enum constants {XLEN=64,XLEN2=128,XLEN_BIT_MASK=63,PCLEN=64,fence=0,fencei=1,fencevmal=2,fencevmau=3,MISA_VAL=2147750144,PGSIZE=4096,PGMASK=4095}; enum constants {
XLEN = 64,
XLEN2 = 128,
XLEN_BIT_MASK = 63,
PCLEN = 64,
fence = 0,
fencei = 1,
fencevmal = 2,
fencevmau = 3,
MISA_VAL = 2147750144,
PGSIZE = 4096,
PGMASK = 4095
};
enum reg_e { enum reg_e {
X0, X0,
@ -85,7 +96,7 @@ struct traits<rv64ia> {
X31, X31,
PC, PC,
NUM_REGS, NUM_REGS,
NEXT_PC=NUM_REGS, NEXT_PC = NUM_REGS,
TRAP_STATE, TRAP_STATE,
PENDING_TRAP, PENDING_TRAP,
MACHINE_STATE, MACHINE_STATE,
@ -96,29 +107,31 @@ struct traits<rv64ia> {
typedef uint64_t addr_t; typedef uint64_t addr_t;
typedef uint64_t code_word_t; //TODO: check removal typedef uint64_t code_word_t; // TODO: check removal
typedef iss::typed_addr_t<iss::VIRTUAL> virt_addr_t; typedef iss::typed_addr_t<iss::VIRTUAL> virt_addr_t;
typedef iss::typed_addr_t<iss::PHYSICAL> phys_addr_t; typedef iss::typed_addr_t<iss::PHYSICAL> phys_addr_t;
constexpr static unsigned reg_bit_width(unsigned r) { constexpr static unsigned reg_bit_width(unsigned r) {
const uint32_t RV64IA_reg_size[] = {64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,32,32,32,64}; const uint32_t RV64IA_reg_size[] = {64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 32, 32, 32, 64};
return RV64IA_reg_size[r]; return RV64IA_reg_size[r];
} }
constexpr static unsigned reg_byte_offset(unsigned r) { constexpr static unsigned reg_byte_offset(unsigned r) {
const uint32_t RV64IA_reg_byte_offset[] = {0,8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,256,264,272,276,280,288,296}; const uint32_t RV64IA_reg_byte_offset[] = {0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96,
104, 112, 120, 128, 136, 144, 152, 160, 168, 176, 184, 192, 200,
208, 216, 224, 232, 240, 248, 256, 264, 272, 276, 280, 288, 296};
return RV64IA_reg_byte_offset[r]; return RV64IA_reg_byte_offset[r];
} }
enum sreg_flag_e {FLAGS}; enum sreg_flag_e { FLAGS };
enum mem_type_e {MEM,CSR,FENCE,RES};
enum mem_type_e { MEM, CSR, FENCE, RES };
}; };
struct rv64ia: public arch_if { struct rv64ia : public arch_if {
using virt_addr_t = typename traits<rv64ia>::virt_addr_t; using virt_addr_t = typename traits<rv64ia>::virt_addr_t;
using phys_addr_t = typename traits<rv64ia>::phys_addr_t; using phys_addr_t = typename traits<rv64ia>::phys_addr_t;
@ -128,29 +141,29 @@ struct rv64ia: public arch_if {
rv64ia(); rv64ia();
~rv64ia(); ~rv64ia();
virtual void reset(uint64_t address=0) override; virtual void reset(uint64_t address = 0) override;
virtual uint8_t* get_regs_base_ptr() override; virtual uint8_t *get_regs_base_ptr() override;
/// deprecated /// deprecated
virtual void get_reg(short idx, std::vector<uint8_t>& value) override {} virtual void get_reg(short idx, std::vector<uint8_t> &value) override {}
virtual void set_reg(short idx, const std::vector<uint8_t>& value) override {} virtual void set_reg(short idx, const std::vector<uint8_t> &value) override {}
/// deprecated /// deprecated
virtual bool get_flag(int flag) override {return false;} virtual bool get_flag(int flag) override { return false; }
virtual void set_flag(int, bool value) override {}; virtual void set_flag(int, bool value) override{};
/// deprecated /// deprecated
virtual void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {}; virtual void update_flags(operations op, uint64_t opr1, uint64_t opr2) override{};
virtual void notify_phase(exec_phase phase){ virtual void notify_phase(exec_phase phase) {
if(phase==ISTART){ if (phase == ISTART) {
++reg.icount; ++reg.icount;
reg.PC=reg.NEXT_PC; reg.PC = reg.NEXT_PC;
reg.trap_state=reg.pending_trap; reg.trap_state = reg.pending_trap;
} }
} }
uint64_t get_icount() { return reg.icount;} uint64_t get_icount() { return reg.icount; }
virtual phys_addr_t v2p(const iss::addr_t& pc); virtual phys_addr_t v2p(const iss::addr_t &pc);
virtual iss::sync_type needed_sync() const { return iss::PRE_SYNC; } virtual iss::sync_type needed_sync() const { return iss::PRE_SYNC; }
@ -194,7 +207,6 @@ protected:
uint64_t icount; uint64_t icount;
} reg; } reg;
}; };
} }
} }
#endif /* _RV64IA_H_ */ #endif /* _RV64IA_H_ */

599
riscv/src/internal/vm_riscv.in.cpp
View File

@ -34,18 +34,18 @@
// //
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
#include <iss/iss.h>
#include <iss/debugger/gdb_session.h>
#include <util/logging.h>
#include <memory>
#include <cstring> #include <cstring>
#include <iss/debugger/gdb_session.h>
#include <iss/iss.h>
#include <memory>
#include <util/logging.h>
#include "iss/vm_base.h"
#include "iss/arch/CORE_DEF_NAME.h" #include "iss/arch/CORE_DEF_NAME.h"
#include "iss/debugger/server.h" #include "iss/debugger/server.h"
#include "iss/vm_base.h"
#include <boost/format.hpp>
#include "iss/arch/riscv_hart_msu_vp.h" #include "iss/arch/riscv_hart_msu_vp.h"
#include <boost/format.hpp>
namespace iss { namespace iss {
namespace CORE_DEF_NAME { namespace CORE_DEF_NAME {
@ -53,28 +53,22 @@ using namespace iss::arch;
using namespace llvm; using namespace llvm;
using namespace iss::debugger; using namespace iss::debugger;
template<typename ARCH> template <typename ARCH> struct vm_impl;
struct vm_impl;
template<typename ARCH> template <typename ARCH> struct target_adapter : public target_adapter_base {
struct target_adapter: public target_adapter_base {
target_adapter(server_if* srv, vm_impl<ARCH>* vm) target_adapter(server_if *srv, vm_impl<ARCH> *vm) : target_adapter_base(srv), vm(vm) {}
: target_adapter_base(srv)
, vm(vm)
{
}
/*============== Thread Control ===============================*/ /*============== Thread Control ===============================*/
/* Set generic thread */ /* Set generic thread */
status set_gen_thread(rp_thread_ref& thread) override; status set_gen_thread(rp_thread_ref &thread) override;
/* Set control thread */ /* Set control thread */
status set_ctrl_thread(rp_thread_ref& thread) override; status set_ctrl_thread(rp_thread_ref &thread) override;
/* Get thread status */ /* Get thread status */
status is_thread_alive(rp_thread_ref& thread, bool& alive) override; status is_thread_alive(rp_thread_ref &thread, bool &alive) override;
/*============= Register Access ================================*/ /*============= Register Access ================================*/
@ -82,49 +76,51 @@ struct target_adapter: public target_adapter_base {
target byte order. If register is not available target byte order. If register is not available
corresponding bytes in avail_buf are 0, otherwise corresponding bytes in avail_buf are 0, otherwise
avail buf is 1 */ avail buf is 1 */
status read_registers(std::vector<uint8_t>& data, std::vector<uint8_t>& avail) override; status read_registers(std::vector<uint8_t> &data, std::vector<uint8_t> &avail) override;
/* Write all registers. buf is 4-byte aligned and it is in target /* Write all registers. buf is 4-byte aligned and it is in target
byte order */ byte order */
status write_registers(const std::vector<uint8_t>& data) override; status write_registers(const std::vector<uint8_t> &data) override;
/* Read one register. buf is 4-byte aligned and it is in /* Read one register. buf is 4-byte aligned and it is in
target byte order. If register is not available target byte order. If register is not available
corresponding bytes in avail_buf are 0, otherwise corresponding bytes in avail_buf are 0, otherwise
avail buf is 1 */ avail buf is 1 */
status read_single_register(unsigned int reg_no, std::vector<uint8_t>& buf, std::vector<uint8_t>& avail_buf) override; status read_single_register(unsigned int reg_no, std::vector<uint8_t> &buf,
std::vector<uint8_t> &avail_buf) override;
/* Write one register. buf is 4-byte aligned and it is in target byte /* Write one register. buf is 4-byte aligned and it is in target byte
order */ order */
status write_single_register(unsigned int reg_no, const std::vector<uint8_t>& buf) override; status write_single_register(unsigned int reg_no, const std::vector<uint8_t> &buf) override;
/*=================== Memory Access =====================*/ /*=================== Memory Access =====================*/
/* Read memory, buf is 4-bytes aligned and it is in target /* Read memory, buf is 4-bytes aligned and it is in target
byte order */ byte order */
status read_mem(uint64_t addr, std::vector<uint8_t>& buf) override; status read_mem(uint64_t addr, std::vector<uint8_t> &buf) override;
/* Write memory, buf is 4-bytes aligned and it is in target /* Write memory, buf is 4-bytes aligned and it is in target
byte order */ byte order */
status write_mem(uint64_t addr, const std::vector<uint8_t>& buf) override; status write_mem(uint64_t addr, const std::vector<uint8_t> &buf) override;
status process_query(unsigned int& mask, const rp_thread_ref& arg, rp_thread_info& info) override; status process_query(unsigned int &mask, const rp_thread_ref &arg, rp_thread_info &info) override;
status thread_list_query(int first, const rp_thread_ref& arg, std::vector<rp_thread_ref>& result, size_t max_num, size_t& num, bool& done) override; status thread_list_query(int first, const rp_thread_ref &arg, std::vector<rp_thread_ref> &result, size_t max_num,
size_t &num, bool &done) override;
status current_thread_query(rp_thread_ref& thread) override; status current_thread_query(rp_thread_ref &thread) override;
status offsets_query(uint64_t& text, uint64_t& data, uint64_t& bss) override; status offsets_query(uint64_t &text, uint64_t &data, uint64_t &bss) override;
status crc_query(uint64_t addr, size_t len, uint32_t& val) override; status crc_query(uint64_t addr, size_t len, uint32_t &val) override;
status raw_query(std::string in_buf, std::string& out_buf) override; status raw_query(std::string in_buf, std::string &out_buf) override;
status threadinfo_query(int first, std::string& out_buf) override; status threadinfo_query(int first, std::string &out_buf) override;
status threadextrainfo_query(const rp_thread_ref& thread, std::string& out_buf) override; status threadextrainfo_query(const rp_thread_ref &thread, std::string &out_buf) override;
status packetsize_query(std::string& out_buf) override; status packetsize_query(std::string &out_buf) override;
status add_break(int type, uint64_t addr, unsigned int length) override; status add_break(int type, uint64_t addr, unsigned int length) override;
@ -133,52 +129,46 @@ struct target_adapter: public target_adapter_base {
status resume_from_addr(bool step, int sig, uint64_t addr) override; status resume_from_addr(bool step, int sig, uint64_t addr) override;
protected: protected:
static inline constexpr addr_t map_addr(const addr_t& i){ static inline constexpr addr_t map_addr(const addr_t &i) { return i; }
return i;
}
vm_impl<ARCH>* vm; vm_impl<ARCH> *vm;
rp_thread_ref thread_idx; rp_thread_ref thread_idx;
}; };
template<typename ARCH> template <typename ARCH> struct vm_impl : public vm::vm_base<ARCH> {
struct vm_impl: public vm::vm_base<ARCH> {
using super = typename vm::vm_base<ARCH>; using super = typename vm::vm_base<ARCH>;
using virt_addr_t = typename super::virt_addr_t; using virt_addr_t = typename super::virt_addr_t;
using phys_addr_t = typename super::phys_addr_t; using phys_addr_t = typename super::phys_addr_t;
using code_word_t = typename super::code_word_t; using code_word_t = typename super::code_word_t;
using addr_t = typename super::addr_t ; using addr_t = typename super::addr_t;
vm_impl(); vm_impl();
vm_impl(ARCH& core, bool dump=false); vm_impl(ARCH &core, bool dump = false);
void enableDebug(bool enable) { void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
super::sync_exec=super::ALL_SYNC;
}
target_adapter_if* accquire_target_adapter(server_if* srv){ target_adapter_if *accquire_target_adapter(server_if *srv) {
debugger_if::dbg_enabled=true; debugger_if::dbg_enabled = true;
if(vm::vm_base<ARCH>::tgt_adapter==nullptr) if (vm::vm_base<ARCH>::tgt_adapter == nullptr)
vm::vm_base<ARCH>::tgt_adapter=new target_adapter<ARCH>(srv, this); vm::vm_base<ARCH>::tgt_adapter = new target_adapter<ARCH>(srv, this);
return vm::vm_base<ARCH>::tgt_adapter; return vm::vm_base<ARCH>::tgt_adapter;
} }
protected: protected:
template <typename T> inline llvm::ConstantInt *size(T type) {
template<typename T> inline
llvm::ConstantInt* size(T type){
return llvm::ConstantInt::get(getContext(), llvm::APInt(32, type->getType()->getScalarSizeInBits())); return llvm::ConstantInt::get(getContext(), llvm::APInt(32, type->getType()->getScalarSizeInBits()));
} }
inline llvm::Value * gen_choose(llvm::Value * cond, llvm::Value * trueVal, llvm::Value * falseVal, unsigned size) const { inline llvm::Value *gen_choose(llvm::Value *cond, llvm::Value *trueVal, llvm::Value *falseVal,
unsigned size) const {
return this->gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size)); return this->gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
} }
std::tuple<vm::continuation_e, llvm::BasicBlock*> gen_single_inst_behavior(virt_addr_t&, unsigned int&, llvm::BasicBlock*) override; std::tuple<vm::continuation_e, llvm::BasicBlock *> gen_single_inst_behavior(virt_addr_t &, unsigned int &,
llvm::BasicBlock *) override;
void gen_leave_behavior(llvm::BasicBlock* leave_blk) override; void gen_leave_behavior(llvm::BasicBlock *leave_blk) override;
void gen_raise_trap(uint16_t trap_id, uint16_t cause); void gen_raise_trap(uint16_t trap_id, uint16_t cause);
@ -186,113 +176,109 @@ protected:
void gen_wait(unsigned type); void gen_wait(unsigned type);
void gen_trap_behavior(llvm::BasicBlock*) override; void gen_trap_behavior(llvm::BasicBlock *) override;
void gen_trap_check(llvm::BasicBlock* bb); void gen_trap_check(llvm::BasicBlock *bb);
inline inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
void gen_set_pc(virt_addr_t pc, unsigned reg_num){ llvm::Value *next_pc_v = this->builder->CreateSExtOrTrunc(this->gen_const(traits<ARCH>::XLEN, pc.val),
llvm::Value* next_pc_v = this->builder->CreateSExtOrTrunc(this->gen_const(traits<ARCH>::XLEN, pc.val), this->get_type(traits<ARCH>::XLEN)); this->get_type(traits<ARCH>::XLEN));
this->builder->CreateStore(next_pc_v, get_reg_ptr(reg_num), true); this->builder->CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
} }
inline inline llvm::Value *get_reg_ptr(unsigned i) {
llvm::Value* get_reg_ptr(unsigned i){ void *ptr = this->core.get_regs_base_ptr() + traits<ARCH>::reg_byte_offset(i);
void* ptr = this->core.get_regs_base_ptr()+traits<ARCH>::reg_byte_offset(i); llvm::PointerType *ptrType = nullptr;
llvm::PointerType* ptrType=nullptr; switch (traits<ARCH>::reg_bit_width(i) >> 3) {
switch (traits<ARCH>::reg_bit_width(i)>>3) {
case 8: case 8:
ptrType=llvm::Type::getInt64PtrTy(this->mod->getContext()); ptrType = llvm::Type::getInt64PtrTy(this->mod->getContext());
break; break;
case 4: case 4:
ptrType=llvm::Type::getInt32PtrTy(this->mod->getContext()); ptrType = llvm::Type::getInt32PtrTy(this->mod->getContext());
break; break;
case 2: case 2:
ptrType=llvm::Type::getInt16PtrTy(this->mod->getContext()); ptrType = llvm::Type::getInt16PtrTy(this->mod->getContext());
break; break;
case 1: case 1:
ptrType=llvm::Type::getInt8PtrTy(this->mod->getContext()); ptrType = llvm::Type::getInt8PtrTy(this->mod->getContext());
break; break;
default: default:
throw std::runtime_error("unsupported access with"); throw std::runtime_error("unsupported access with");
break; break;
} }
return llvm::ConstantExpr::getIntToPtr( return llvm::ConstantExpr::getIntToPtr(
llvm::ConstantInt::get(this->mod->getContext(), llvm::APInt( llvm::ConstantInt::get(this->mod->getContext(),
8/*bits*/ * sizeof(uint8_t*), llvm::APInt(8 /*bits*/ * sizeof(uint8_t *), reinterpret_cast<uint64_t>(ptr))),
reinterpret_cast<uint64_t>(ptr)
)),
ptrType); ptrType);
} }
inline inline llvm::Value *gen_reg_load(unsigned i, unsigned level = 0) {
llvm::Value* gen_reg_load(unsigned i, unsigned level=0){ // if(level){
// if(level){
return this->builder->CreateLoad(get_reg_ptr(i), false); return this->builder->CreateLoad(get_reg_ptr(i), false);
// } else { // } else {
// if(!this->loaded_regs[i]) // if(!this->loaded_regs[i])
// this->loaded_regs[i]=this->builder->CreateLoad(get_reg_ptr(i), false); // this->loaded_regs[i]=this->builder->CreateLoad(get_reg_ptr(i),
// return this->loaded_regs[i]; // false);
// } // return this->loaded_regs[i];
// }
} }
inline inline void gen_set_pc(virt_addr_t pc) {
void gen_set_pc(virt_addr_t pc){ llvm::Value *pc_l = this->builder->CreateSExt(this->gen_const(traits<ARCH>::caddr_bit_width, (unsigned)pc),
llvm::Value* pc_l = this->builder->CreateSExt(this->gen_const(traits<ARCH>::caddr_bit_width, (unsigned)pc), this->get_type(traits<ARCH>::caddr_bit_width)); this->get_type(traits<ARCH>::caddr_bit_width));
super::gen_set_reg(traits<ARCH>::PC, pc_l); super::gen_set_reg(traits<ARCH>::PC, pc_l);
} }
// some compile time constants // some compile time constants
enum {MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111}; enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
enum {EXTR_MASK16 = MASK16>>2, EXTR_MASK32 = MASK32>>2}; enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
enum {LUT_SIZE = 1<< bit_count(EXTR_MASK32), LUT_SIZE_C = 1<<bit_count(EXTR_MASK16)}; enum { LUT_SIZE = 1 << bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << bit_count(EXTR_MASK16) };
using this_class = vm_impl<ARCH>; using this_class = vm_impl<ARCH>;
using compile_func = std::tuple<vm::continuation_e, llvm::BasicBlock*> (this_class::*)(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb); using compile_func = std::tuple<vm::continuation_e, llvm::BasicBlock *> (this_class::*)(virt_addr_t &pc,
code_word_t instr,
llvm::BasicBlock *bb);
compile_func lut[LUT_SIZE]; compile_func lut[LUT_SIZE];
std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10; std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
std::array<compile_func, LUT_SIZE> lut_11; std::array<compile_func, LUT_SIZE> lut_11;
compile_func* qlut[4];// = {lut_00, lut_01, lut_10, lut_11}; compile_func *qlut[4]; // = {lut_00, lut_01, lut_10, lut_11};
const uint32_t lutmasks[4]={EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}; const uint32_t lutmasks[4] = {EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32};
void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[], compile_func f){ void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
if(pos<0){ compile_func f) {
lut[idx]=f; if (pos < 0) {
lut[idx] = f;
} else { } else {
auto bitmask = 1UL<<pos; auto bitmask = 1UL << pos;
if((mask & bitmask)==0){ if ((mask & bitmask) == 0) {
expand_bit_mask(pos-1, mask, value, valid, idx, lut, f); expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
} else { } else {
if((valid & bitmask) == 0) { if ((valid & bitmask) == 0) {
expand_bit_mask(pos-1, mask, value, valid, (idx<<1), lut, f); expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
expand_bit_mask(pos-1, mask, value, valid, (idx<<1)+1, lut, f); expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
} else { } else {
auto new_val = idx<<1; auto new_val = idx << 1;
if((value&bitmask)!=0) if ((value & bitmask) != 0) new_val++;
new_val++; expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
expand_bit_mask(pos-1, mask, value, valid, new_val, lut, f);
} }
} }
} }
} }
inline uint32_t extract_fields(uint32_t val){ inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
return extract_fields(29, val>>2, lutmasks[val&0x3], 0);
}
uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val){ uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
if(pos>=0) { if (pos >= 0) {
auto bitmask = 1UL<<pos; auto bitmask = 1UL << pos;
if((mask & bitmask)==0){ if ((mask & bitmask) == 0) {
lut_val = extract_fields(pos-1, val, mask, lut_val); lut_val = extract_fields(pos - 1, val, mask, lut_val);
} else { } else {
auto new_val = lut_val<<1; auto new_val = lut_val << 1;
if((val&bitmask)!=0) if ((val & bitmask) != 0) new_val++;
new_val++; lut_val = extract_fields(pos - 1, val, mask, new_val);
lut_val = extract_fields(pos-1, val, mask, new_val);
} }
} }
return lut_val; return lut_val;
@ -315,381 +301,346 @@ private:
/**************************************************************************** /****************************************************************************
* end opcode definitions * end opcode definitions
****************************************************************************/ ****************************************************************************/
std::tuple<vm::continuation_e, llvm::BasicBlock*> illegal_intruction(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ std::tuple<vm::continuation_e, llvm::BasicBlock *> illegal_intruction(virt_addr_t &pc, code_word_t instr,
//this->gen_sync(iss::PRE_SYNC); llvm::BasicBlock *bb) {
this->builder->CreateStore( // this->gen_sync(iss::PRE_SYNC);
this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), true), this->builder->CreateStore(this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), true),
get_reg_ptr(traits<ARCH>::PC), true); get_reg_ptr(traits<ARCH>::PC), true);
this->builder->CreateStore( this->builder->CreateStore(
this->builder->CreateAdd( this->builder->CreateAdd(this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::ICOUNT), true),
this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::ICOUNT), true),
this->gen_const(64U, 1)), this->gen_const(64U, 1)),
get_reg_ptr(traits<ARCH>::ICOUNT), true); get_reg_ptr(traits<ARCH>::ICOUNT), true);
if(this->debugging_enabled()) this->gen_sync(iss::PRE_SYNC); if (this->debugging_enabled()) this->gen_sync(iss::PRE_SYNC);
pc=pc+((instr&3) == 3?4:2); pc = pc + ((instr & 3) == 3 ? 4 : 2);
this->gen_raise_trap(0, 2); // illegal instruction trap this->gen_raise_trap(0, 2); // illegal instruction trap
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
this->gen_trap_check(this->leave_blk); this->gen_trap_check(this->leave_blk);
return std::make_tuple(iss::vm::BRANCH, nullptr); return std::make_tuple(iss::vm::BRANCH, nullptr);
} }
}; };
template<typename CODE_WORD> template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
void debug_fn(CODE_WORD insn){ volatile CODE_WORD x = insn;
volatile CODE_WORD x=insn; insn = 2 * x;
insn=2*x;
} }
template<typename ARCH> template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
vm_impl<ARCH>::vm_impl(){
this(new ARCH());
}
template<typename ARCH> template <typename ARCH> vm_impl<ARCH>::vm_impl(ARCH &core, bool dump) : vm::vm_base<ARCH>(core, dump) {
vm_impl<ARCH>::vm_impl(ARCH& core, bool dump) : vm::vm_base<ARCH>(core, dump) {
qlut[0] = lut_00.data(); qlut[0] = lut_00.data();
qlut[1] = lut_01.data(); qlut[1] = lut_01.data();
qlut[2] = lut_10.data(); qlut[2] = lut_10.data();
qlut[3] = lut_11.data(); qlut[3] = lut_11.data();
for(auto instr: instr_descr){ for (auto instr : instr_descr) {
auto quantrant = instr.value&0x3; auto quantrant = instr.value & 0x3;
expand_bit_mask(29, lutmasks[quantrant], instr.value>>2, instr.mask>>2, 0, qlut[quantrant], instr.op); expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
} }
this->sync_exec=static_cast<sync_type>(this->sync_exec|core.needed_sync()); this->sync_exec = static_cast<sync_type>(this->sync_exec | core.needed_sync());
} }
template<typename ARCH> template <typename ARCH>
std::tuple<vm::continuation_e, llvm::BasicBlock*> vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t& pc, unsigned int& inst_cnt, llvm::BasicBlock* this_block){ std::tuple<vm::continuation_e, llvm::BasicBlock *>
vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, llvm::BasicBlock *this_block) {
// we fetch at max 4 byte, alignment is 2 // we fetch at max 4 byte, alignment is 2
code_word_t insn = 0; code_word_t insn = 0;
iss::addr_t paddr; iss::addr_t paddr;
const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK; const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
try { try {
uint8_t* const data = (uint8_t*)&insn; uint8_t *const data = (uint8_t *)&insn;
paddr=this->core.v2p(pc); paddr = this->core.v2p(pc);
if((pc.val&upper_bits) != ((pc.val+2)&upper_bits)){ // we may cross a page boundary if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
auto res = this->core.read(paddr, 2, data); auto res = this->core.read(paddr, 2, data);
if(res!=iss::Ok) if (res != iss::Ok) throw trap_access(1, pc.val);
throw trap_access(1, pc.val); if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
if((insn & 0x3) == 0x3){ // this is a 32bit instruction res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
res = this->core.read(this->core.v2p(pc+2), 2, data+2);
} }
} else { } else {
auto res = this->core.read(paddr, 4, data); auto res = this->core.read(paddr, 4, data);
if(res!=iss::Ok) if (res != iss::Ok) throw trap_access(1, pc.val);
throw trap_access(1, pc.val);
} }
} catch(trap_access& ta){ } catch (trap_access &ta) {
throw trap_access(ta.id, pc.val); throw trap_access(ta.id, pc.val);
} }
if(insn==0x0000006f) if (insn == 0x0000006f) throw simulation_stopped(0);
throw simulation_stopped(0);
// curr pc on stack // curr pc on stack
typename vm_impl<ARCH>::processing_pc_entry addr(*this, pc, paddr); typename vm_impl<ARCH>::processing_pc_entry addr(*this, pc, paddr);
++inst_cnt; ++inst_cnt;
auto lut_val = extract_fields(insn); auto lut_val = extract_fields(insn);
auto f = qlut[insn&0x3][lut_val]; auto f = qlut[insn & 0x3][lut_val];
if (f==nullptr){ if (f == nullptr) {
f=&this_class::illegal_intruction; f = &this_class::illegal_intruction;
} }
return (this->*f)(pc, insn, this_block); return (this->*f)(pc, insn, this_block);
} }
template<typename ARCH> template <typename ARCH> void vm_impl<ARCH>::gen_leave_behavior(llvm::BasicBlock *leave_blk) {
void vm_impl<ARCH>::gen_leave_behavior(llvm::BasicBlock* leave_blk){
this->builder->SetInsertPoint(leave_blk); this->builder->SetInsertPoint(leave_blk);
this->builder->CreateRet(this->builder->CreateLoad(get_reg_ptr(arch::traits<ARCH>::NEXT_PC), false)); this->builder->CreateRet(this->builder->CreateLoad(get_reg_ptr(arch::traits<ARCH>::NEXT_PC), false));
} }
template<typename ARCH> template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause){ auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
auto* TRAP_val = this->gen_const(32, 0x80<<24| (cause<<16) | trap_id );
this->builder->CreateStore(TRAP_val, get_reg_ptr(traits<ARCH>::TRAP_STATE), true); this->builder->CreateStore(TRAP_val, get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
} }
template<typename ARCH> template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
void vm_impl<ARCH>::gen_leave_trap(unsigned lvl){ std::vector<llvm::Value *> args{
std::vector<llvm::Value*> args { this->core_ptr, llvm::ConstantInt::get(getContext(), llvm::APInt(64, lvl)),
this->core_ptr,
llvm::ConstantInt::get(getContext(), llvm::APInt(64, lvl)),
}; };
this->builder->CreateCall(this->mod->getFunction("leave_trap"), args); this->builder->CreateCall(this->mod->getFunction("leave_trap"), args);
auto* PC_val = this->gen_read_mem(traits<ARCH>::CSR, (lvl<<8)+0x41, traits<ARCH>::XLEN/8); auto *PC_val = this->gen_read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN / 8);
this->builder->CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false); this->builder->CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
} }
template<typename ARCH> template <typename ARCH> void vm_impl<ARCH>::gen_wait(unsigned type) {
void vm_impl<ARCH>::gen_wait(unsigned type){ std::vector<llvm::Value *> args{
std::vector<llvm::Value*> args { this->core_ptr, llvm::ConstantInt::get(getContext(), llvm::APInt(64, type)),
this->core_ptr,
llvm::ConstantInt::get(getContext(), llvm::APInt(64, type)),
}; };
this->builder->CreateCall(this->mod->getFunction("wait"), args); this->builder->CreateCall(this->mod->getFunction("wait"), args);
} }
template<typename ARCH> template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(llvm::BasicBlock *trap_blk) {
void vm_impl<ARCH>::gen_trap_behavior(llvm::BasicBlock* trap_blk){
this->builder->SetInsertPoint(trap_blk); this->builder->SetInsertPoint(trap_blk);
auto* trap_state_val = this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::TRAP_STATE), true); auto *trap_state_val = this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
std::vector<llvm::Value*> args { std::vector<llvm::Value *> args{this->core_ptr, this->adj_to64(trap_state_val),
this->core_ptr, this->adj_to64(this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::PC), false))};
this->adj_to64(trap_state_val),
this->adj_to64(this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::PC), false))
};
this->builder->CreateCall(this->mod->getFunction("enter_trap"), args); this->builder->CreateCall(this->mod->getFunction("enter_trap"), args);
auto* trap_addr_val = this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), false); auto *trap_addr_val = this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), false);
this->builder->CreateRet(trap_addr_val); this->builder->CreateRet(trap_addr_val);
} }
template<typename ARCH> inline template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(llvm::BasicBlock *bb) {
void vm_impl<ARCH>::gen_trap_check(llvm::BasicBlock* bb){ auto *v = this->builder->CreateLoad(get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), true);
auto* v = this->builder->CreateLoad(get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), true); this->gen_cond_branch(this->builder->CreateICmp(
this->gen_cond_branch( ICmpInst::ICMP_EQ, v,
this->builder->CreateICmp(
ICmpInst::ICMP_EQ,
v,
llvm::ConstantInt::get(getContext(), llvm::APInt(v->getType()->getIntegerBitWidth(), 0))), llvm::ConstantInt::get(getContext(), llvm::APInt(v->getType()->getIntegerBitWidth(), 0))),
bb, bb, this->trap_blk, 1);
this->trap_blk, 1);
} }
} // namespace CORE_DEF_NAME } // namespace CORE_DEF_NAME
#define CREATE_FUNCS(ARCH) \ #define CREATE_FUNCS(ARCH) \
template<> std::unique_ptr<vm_if> create<ARCH>(ARCH* core, unsigned short port, bool dump) {\ template <> std::unique_ptr<vm_if> create<ARCH>(ARCH * core, unsigned short port, bool dump) { \
std::unique_ptr<CORE_DEF_NAME::vm_impl<ARCH> > ret = std::make_unique<CORE_DEF_NAME::vm_impl<ARCH> >(*core, dump);\ std::unique_ptr<CORE_DEF_NAME::vm_impl<ARCH>> ret = \
debugger::server<debugger::gdb_session>::run_server(ret.get(), port);\ std::make_unique<CORE_DEF_NAME::vm_impl<ARCH>>(*core, dump); \
return ret;\ debugger::server<debugger::gdb_session>::run_server(ret.get(), port); \
}\ return ret; \
template<> std::unique_ptr<vm_if> create<ARCH>(std::string inst_name, unsigned short port, bool dump) {\ } \
return create<ARCH>(new arch::riscv_hart_msu_vp<ARCH>(), port, dump); /* FIXME: memory leak!!!!!!! */\ template <> std::unique_ptr<vm_if> create<ARCH>(std::string inst_name, unsigned short port, bool dump) { \
}\ return create<ARCH>(new arch::riscv_hart_msu_vp<ARCH>(), port, dump); /* FIXME: memory leak!!!!!!! */ \
template<> std::unique_ptr<vm_if> create<ARCH>(ARCH* core, bool dump) {\ } \
return std::make_unique<CORE_DEF_NAME::vm_impl<ARCH> >(*core, dump); /* FIXME: memory leak!!!!!!! */ \ template <> std::unique_ptr<vm_if> create<ARCH>(ARCH * core, bool dump) { \
}\ return std::make_unique<CORE_DEF_NAME::vm_impl<ARCH>>(*core, dump); /* FIXME: memory leak!!!!!!! */ \
template<> std::unique_ptr<vm_if> create<ARCH>(std::string inst_name, bool dump) { \ } \
return create<ARCH>(new arch::riscv_hart_msu_vp<ARCH>(), dump);\ template <> std::unique_ptr<vm_if> create<ARCH>(std::string inst_name, bool dump) { \
} return create<ARCH>(new arch::riscv_hart_msu_vp<ARCH>(), dump); \
}
CREATE_FUNCS(arch::CORE_DEF_NAME) CREATE_FUNCS(arch::CORE_DEF_NAME)
namespace CORE_DEF_NAME { namespace CORE_DEF_NAME {
template<typename ARCH> template <typename ARCH> status target_adapter<ARCH>::set_gen_thread(rp_thread_ref &thread) {
status target_adapter<ARCH>::set_gen_thread(rp_thread_ref& thread) { thread_idx = thread;
thread_idx=thread;
return Ok; return Ok;
} }
template<typename ARCH> template <typename ARCH> status target_adapter<ARCH>::set_ctrl_thread(rp_thread_ref &thread) {
status target_adapter<ARCH>::set_ctrl_thread(rp_thread_ref& thread) { thread_idx = thread;
thread_idx=thread;
return Ok; return Ok;
} }
template<typename ARCH> template <typename ARCH> status target_adapter<ARCH>::is_thread_alive(rp_thread_ref &thread, bool &alive) {
status target_adapter<ARCH>::is_thread_alive(rp_thread_ref& thread, bool& alive) { alive = 1;
alive=1;
return Ok; return Ok;
} }
/* List threads. If first is non-zero then start from the first thread, /* List threads. If first is non-zero then start from the first thread,
* otherwise start from arg, result points to array of threads to be * otherwise start from arg, result points to array of threads to be
* filled out, result size is number of elements in the result, * filled out, result size is number of elements in the result,
* num points to the actual number of threads found, done is * num points to the actual number of threads found, done is
* set if all threads are processed. * set if all threads are processed.
*/ */
template<typename ARCH> template <typename ARCH>
status target_adapter<ARCH>::thread_list_query(int first, const rp_thread_ref& arg, std::vector<rp_thread_ref>& result, size_t max_num, status target_adapter<ARCH>::thread_list_query(int first, const rp_thread_ref &arg, std::vector<rp_thread_ref> &result,
size_t& num, bool& done) { size_t max_num, size_t &num, bool &done) {
if(first==0){ if (first == 0) {
result.clear(); result.clear();
result.push_back(thread_idx); result.push_back(thread_idx);
num=1; num = 1;
done=true; done = true;
return Ok; return Ok;
} else } else
return NotSupported; return NotSupported;
} }
template<typename ARCH> template <typename ARCH> status target_adapter<ARCH>::current_thread_query(rp_thread_ref &thread) {
status target_adapter<ARCH>::current_thread_query(rp_thread_ref& thread) { thread = thread_idx;
thread=thread_idx;
return Ok; return Ok;
} }
template<typename ARCH> template <typename ARCH>
status target_adapter<ARCH>::read_registers(std::vector<uint8_t>& data, std::vector<uint8_t>& avail) { status target_adapter<ARCH>::read_registers(std::vector<uint8_t> &data, std::vector<uint8_t> &avail) {
LOG(TRACE)<<"reading target registers"; LOG(TRACE) << "reading target registers";
//return idx<0?:; // return idx<0?:;
data.clear(); data.clear();
avail.clear(); avail.clear();
std::vector<uint8_t> reg_data; std::vector<uint8_t> reg_data;
for(size_t reg_no = 0; reg_no < arch::traits<ARCH>::NUM_REGS; ++reg_no){ for (size_t reg_no = 0; reg_no < arch::traits<ARCH>::NUM_REGS; ++reg_no) {
auto reg_bit_width = arch::traits<ARCH>::reg_bit_width(static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)); auto reg_bit_width = arch::traits<ARCH>::reg_bit_width(static_cast<typename arch::traits<ARCH>::reg_e>(reg_no));
auto reg_width=reg_bit_width/8; auto reg_width = reg_bit_width / 8;
reg_data.resize(reg_width); reg_data.resize(reg_width);
vm->get_arch()->get_reg(reg_no, reg_data); vm->get_arch()->get_reg(reg_no, reg_data);
for(size_t j=0; j<reg_data.size(); ++j){ for (size_t j = 0; j < reg_data.size(); ++j) {
data.push_back(reg_data[j]); data.push_back(reg_data[j]);
avail.push_back(0xff); avail.push_back(0xff);
} }
} }
// work around fill with F type registers // work around fill with F type registers
if(arch::traits<ARCH>::NUM_REGS < 65){ if (arch::traits<ARCH>::NUM_REGS < 65) {
auto reg_width=sizeof(typename arch::traits<ARCH>::reg_t); auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
for(size_t reg_no = 0; reg_no < 33; ++reg_no){ for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
for(size_t j=0; j<reg_width; ++j){ for (size_t j = 0; j < reg_width; ++j) {
data.push_back(0x0); data.push_back(0x0);
avail.push_back(0x00); avail.push_back(0x00);
} }
} }
} }
return Ok; return Ok;
} }
template<typename ARCH> template <typename ARCH> status target_adapter<ARCH>::write_registers(const std::vector<uint8_t> &data) {
status target_adapter<ARCH>::write_registers(const std::vector<uint8_t>& data) { size_t data_index = 0;
size_t data_index=0; auto reg_count = arch::traits<ARCH>::NUM_REGS;
auto reg_count=arch::traits<ARCH>::NUM_REGS;
std::vector<uint8_t> reg_data; std::vector<uint8_t> reg_data;
for(size_t reg_no = 0; reg_no < reg_count; ++reg_no){ for (size_t reg_no = 0; reg_no < reg_count; ++reg_no) {
auto reg_bit_width = arch::traits<ARCH>::reg_bit_width(static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)); auto reg_bit_width = arch::traits<ARCH>::reg_bit_width(static_cast<typename arch::traits<ARCH>::reg_e>(reg_no));
auto reg_width=reg_bit_width/8; auto reg_width = reg_bit_width / 8;
vm->get_arch()->set_reg(reg_no, std::vector<uint8_t>(data.begin()+data_index, data.begin()+data_index+reg_width)); vm->get_arch()->set_reg(reg_no,
data_index+=reg_width; std::vector<uint8_t>(data.begin() + data_index, data.begin() + data_index + reg_width));
data_index += reg_width;
} }
return Ok; return Ok;
} }
template<typename ARCH> template <typename ARCH>
status target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t>& data, std::vector<uint8_t>& avail) { status target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t> &data,
if(reg_no<65){ std::vector<uint8_t> &avail) {
//auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename arch::traits<ARCH>::reg_e>(reg_no))/8; if (reg_no < 65) {
// auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename
// arch::traits<ARCH>::reg_e>(reg_no))/8;
data.resize(0); data.resize(0);
vm->get_arch()->get_reg(reg_no, data); vm->get_arch()->get_reg(reg_no, data);
avail.resize(data.size()); avail.resize(data.size());
std::fill(avail.begin(), avail.end(), 0xff); std::fill(avail.begin(), avail.end(), 0xff);
} else { } else {
typed_addr_t<iss::PHYSICAL> a(iss::DEBUG_READ, traits<ARCH>::CSR, reg_no-65); typed_addr_t<iss::PHYSICAL> a(iss::DEBUG_READ, traits<ARCH>::CSR, reg_no - 65);
data.resize(sizeof(typename traits<ARCH>::reg_t)); data.resize(sizeof(typename traits<ARCH>::reg_t));
avail.resize(sizeof(typename traits<ARCH>::reg_t)); avail.resize(sizeof(typename traits<ARCH>::reg_t));
std::fill(avail.begin(), avail.end(), 0xff); std::fill(avail.begin(), avail.end(), 0xff);
vm->get_arch()->read(a, data.size(), data.data()); vm->get_arch()->read(a, data.size(), data.data());
} }
return data.size()>0?Ok:Err; return data.size() > 0 ? Ok : Err;
} }
template<typename ARCH> template <typename ARCH>
status target_adapter<ARCH>::write_single_register(unsigned int reg_no, const std::vector<uint8_t>& data) { status target_adapter<ARCH>::write_single_register(unsigned int reg_no, const std::vector<uint8_t> &data) {
if(reg_no<65) if (reg_no < 65)
vm->get_arch()->set_reg(reg_no, data); vm->get_arch()->set_reg(reg_no, data);
else { else {
typed_addr_t<iss::PHYSICAL> a(iss::DEBUG_WRITE, traits<ARCH>::CSR, reg_no-65); typed_addr_t<iss::PHYSICAL> a(iss::DEBUG_WRITE, traits<ARCH>::CSR, reg_no - 65);
vm->get_arch()->write(a, data.size(), data.data()); vm->get_arch()->write(a, data.size(), data.data());
} }
return Ok; return Ok;
} }
template<typename ARCH> template <typename ARCH> status target_adapter<ARCH>::read_mem(uint64_t addr, std::vector<uint8_t> &data) {
status target_adapter<ARCH>::read_mem(uint64_t addr, std::vector<uint8_t>& data) { auto a = map_addr({iss::DEBUG_READ, iss::VIRTUAL, 0, addr});
auto a=map_addr({iss::DEBUG_READ, iss::VIRTUAL, 0, addr}); auto f = [&]() -> status { return vm->get_arch()->read(a, data.size(), data.data()); };
auto f = [&]()->status {
return vm->get_arch()->read(a, data.size(), data.data());
};
return srv->execute_syncronized(f); return srv->execute_syncronized(f);
}
} template <typename ARCH> status target_adapter<ARCH>::write_mem(uint64_t addr, const std::vector<uint8_t> &data) {
auto a = map_addr({iss::DEBUG_READ, iss::VIRTUAL, 0, addr});
template<typename ARCH>
status target_adapter<ARCH>::write_mem(uint64_t addr, const std::vector<uint8_t>& data) {
auto a=map_addr({iss::DEBUG_READ, iss::VIRTUAL, 0, addr});
return srv->execute_syncronized(&arch_if::write, vm->get_arch(), a, data.size(), data.data()); return srv->execute_syncronized(&arch_if::write, vm->get_arch(), a, data.size(), data.data());
} }
template<typename ARCH> template <typename ARCH>
status target_adapter<ARCH>::process_query(unsigned int& mask, const rp_thread_ref& arg, rp_thread_info& info) { status target_adapter<ARCH>::process_query(unsigned int &mask, const rp_thread_ref &arg, rp_thread_info &info) {
return NotSupported; return NotSupported;
} }
template<typename ARCH> template <typename ARCH> status target_adapter<ARCH>::offsets_query(uint64_t &text, uint64_t &data, uint64_t &bss) {
status target_adapter<ARCH>::offsets_query(uint64_t& text, uint64_t& data, uint64_t& bss) { text = 0;
text=0; data = 0;
data=0; bss = 0;
bss=0;
return Ok; return Ok;
} }
template<typename ARCH> template <typename ARCH> status target_adapter<ARCH>::crc_query(uint64_t addr, size_t len, uint32_t &val) {
status target_adapter<ARCH>::crc_query(uint64_t addr, size_t len, uint32_t& val) {
return NotSupported; return NotSupported;
} }
template<typename ARCH> template <typename ARCH> status target_adapter<ARCH>::raw_query(std::string in_buf, std::string &out_buf) {
status target_adapter<ARCH>::raw_query(std::string in_buf, std::string& out_buf) {
return NotSupported; return NotSupported;
} }
template<typename ARCH> template <typename ARCH> status target_adapter<ARCH>::threadinfo_query(int first, std::string &out_buf) {
status target_adapter<ARCH>::threadinfo_query(int first, std::string& out_buf) { if (first) {
if(first){
std::stringstream ss; std::stringstream ss;
ss<<"m"<<std::hex<<thread_idx.val; ss << "m" << std::hex << thread_idx.val;
out_buf=ss.str(); out_buf = ss.str();
} else { } else {
out_buf="l"; out_buf = "l";
} }
return Ok; return Ok;
} }
template<typename ARCH> template <typename ARCH>
status target_adapter<ARCH>::threadextrainfo_query(const rp_thread_ref& thread, std::string& out_buf) { status target_adapter<ARCH>::threadextrainfo_query(const rp_thread_ref &thread, std::string &out_buf) {
char buf[20]; char buf[20];
memset(buf, 0, 20); memset(buf, 0, 20);
sprintf (buf, "%02x%02x%02x%02x%02x%02x%02x%02x%02x", 'R', 'u', 'n', 'n', 'a', 'b', 'l', 'e', 0); sprintf(buf, "%02x%02x%02x%02x%02x%02x%02x%02x%02x", 'R', 'u', 'n', 'n', 'a', 'b', 'l', 'e', 0);
out_buf=buf; out_buf = buf;
return Ok; return Ok;
} }
template<typename ARCH> template <typename ARCH> status target_adapter<ARCH>::packetsize_query(std::string &out_buf) {
status target_adapter<ARCH>::packetsize_query(std::string& out_buf) { out_buf = "PacketSize=1000";
out_buf="PacketSize=1000";
return Ok; return Ok;
} }
template<typename ARCH> template <typename ARCH> status target_adapter<ARCH>::add_break(int type, uint64_t addr, unsigned int length) {
status target_adapter<ARCH>::add_break(int type, uint64_t addr, unsigned int length) { auto saddr = map_addr({iss::CODE, iss::PHYSICAL, addr});
auto saddr=map_addr({iss::CODE, iss::PHYSICAL, addr}); auto eaddr = map_addr({iss::CODE, iss::PHYSICAL, addr + length});
auto eaddr=map_addr({iss::CODE, iss::PHYSICAL, addr+length}); target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val-saddr.val); LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex
LOG(TRACE)<<"Adding breakpoint with handle "<<target_adapter_base::bp_count<<" for addr 0x"<<std::hex<<saddr.val<<std::dec; << saddr.val << std::dec;
LOG(TRACE)<<"Now having "<<target_adapter_base::bp_lut.size()<<" breakpoints"; LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
return Ok; return Ok;
} }
template<typename ARCH> template <typename ARCH> status target_adapter<ARCH>::remove_break(int type, uint64_t addr, unsigned int length) {
status target_adapter<ARCH>::remove_break(int type, uint64_t addr, unsigned int length) { auto saddr = map_addr({iss::CODE, iss::PHYSICAL, addr});
auto saddr=map_addr({iss::CODE, iss::PHYSICAL, addr}); unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
unsigned handle=target_adapter_base::bp_lut.getEntry(saddr.val);
// TODO: check length of addr range // TODO: check length of addr range
if(handle){ if (handle) {
LOG(TRACE)<<"Removing breakpoint with handle "<<handle<<" for addr 0x"<<std::hex<<saddr.val<<std::dec; LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val
<< std::dec;
target_adapter_base::bp_lut.removeEntry(handle); target_adapter_base::bp_lut.removeEntry(handle);
LOG(TRACE)<<"Now having "<<target_adapter_base::bp_lut.size()<<" breakpoints"; LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
return Ok; return Ok;
} }
LOG(TRACE)<<"Now having "<<target_adapter_base::bp_lut.size()<<" breakpoints"; LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
return Err; return Err;
} }
template<typename ARCH> template <typename ARCH> status target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t addr) {
status target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t addr) {
unsigned reg_no = arch::traits<ARCH>::PC; unsigned reg_no = arch::traits<ARCH>::PC;
std::vector<uint8_t> data(8); std::vector<uint8_t> data(8);
*(reinterpret_cast<uint64_t*>(&data[0]))=addr; *(reinterpret_cast<uint64_t *>(&data[0])) = addr;
vm->get_arch()->set_reg(reg_no, data); vm->get_arch()->set_reg(reg_no, data);
return resume_from_current(step, sig); return resume_from_current(step, sig);
} }
} // namespace CORE_DEF_NAME } // namespace CORE_DEF_NAME
} // namespace iss } // namespace iss

3846
riscv/src/internal/vm_rv32imac.cpp
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File diff suppressed because it is too large Load Diff

3126
riscv/src/internal/vm_rv64ia.cpp
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File diff suppressed because it is too large Load Diff

28
riscv/src/iss/rv32imac.cpp
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@ -46,31 +46,27 @@ extern "C" {
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#include <fstream>
#include <cstdio> #include <cstdio>
#include <cstring> #include <cstring>
#include <fstream>
using namespace iss::arch; using namespace iss::arch;
rv32imac::rv32imac() { rv32imac::rv32imac() { reg.icount = 0; }
reg.icount=0;
}
rv32imac::~rv32imac(){ rv32imac::~rv32imac() {}
}
void rv32imac::reset(uint64_t address) { void rv32imac::reset(uint64_t address) {
for(size_t i=0; i<traits<rv32imac>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<rv32imac>::reg_t),0)); for (size_t i = 0; i < traits<rv32imac>::NUM_REGS; ++i)
reg.PC=address; set_reg(i, std::vector<uint8_t>(sizeof(traits<rv32imac>::reg_t), 0));
reg.NEXT_PC=reg.PC; reg.PC = address;
reg.trap_state=0; reg.NEXT_PC = reg.PC;
reg.machine_state=0x3; reg.trap_state = 0;
reg.machine_state = 0x3;
} }
uint8_t* rv32imac::get_regs_base_ptr(){ uint8_t *rv32imac::get_regs_base_ptr() { return reinterpret_cast<uint8_t *>(&reg); }
return reinterpret_cast<uint8_t*>(&reg);
}
rv32imac::phys_addr_t rv32imac::v2p(const iss::addr_t& pc) { rv32imac::phys_addr_t rv32imac::v2p(const iss::addr_t &pc) {
return phys_addr_t(pc); //change logical address to physical address return phys_addr_t(pc); // change logical address to physical address
} }

28
riscv/src/iss/rv64ia.cpp
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@ -46,31 +46,27 @@ extern "C" {
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#include <fstream>
#include <cstdio> #include <cstdio>
#include <cstring> #include <cstring>
#include <fstream>
using namespace iss::arch; using namespace iss::arch;
rv64ia::rv64ia() { rv64ia::rv64ia() { reg.icount = 0; }
reg.icount=0;
}
rv64ia::~rv64ia(){ rv64ia::~rv64ia() {}
}
void rv64ia::reset(uint64_t address) { void rv64ia::reset(uint64_t address) {
for(size_t i=0; i<traits<rv64ia>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<rv64ia>::reg_t),0)); for (size_t i = 0; i < traits<rv64ia>::NUM_REGS; ++i)
reg.PC=address; set_reg(i, std::vector<uint8_t>(sizeof(traits<rv64ia>::reg_t), 0));
reg.NEXT_PC=reg.PC; reg.PC = address;
reg.trap_state=0; reg.NEXT_PC = reg.PC;
reg.machine_state=0x0; reg.trap_state = 0;
reg.machine_state = 0x0;
} }
uint8_t* rv64ia::get_regs_base_ptr(){ uint8_t *rv64ia::get_regs_base_ptr() { return reinterpret_cast<uint8_t *>(&reg); }
return reinterpret_cast<uint8_t*>(&reg);
}
rv64ia::phys_addr_t rv64ia::v2p(const iss::addr_t& pc) { rv64ia::phys_addr_t rv64ia::v2p(const iss::addr_t &pc) {
return phys_addr_t(pc); //change logical address to physical address return phys_addr_t(pc); // change logical address to physical address
} }

52
riscv/src/main.cpp
View File

@ -32,32 +32,31 @@
// eyck@minres.com - initial API and implementation // eyck@minres.com - initial API and implementation
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
#include <cli_options.h> #include <cli_options.h>
#include <iss/iss.h>
#include <iostream> #include <iostream>
#include <iss/iss.h>
#include <iss/log_categories.h> #include <boost/lexical_cast.hpp>
#include <iss/arch/rv32imac.h> #include <iss/arch/rv32imac.h>
#include <iss/arch/rv64ia.h> #include <iss/arch/rv64ia.h>
#include <iss/jit/MCJIThelper.h> #include <iss/jit/MCJIThelper.h>
#include <boost/lexical_cast.hpp> #include <iss/log_categories.h>
namespace po= boost::program_options; namespace po = boost::program_options;
int main(int argc, char *argv[]) { int main(int argc, char *argv[]) {
try{ try {
/* /*
* Define and parse the program options * Define and parse the program options
*/ */
po::variables_map vm; po::variables_map vm;
if(parse_cli_options(vm, argc, argv)) return ERROR_IN_COMMAND_LINE; if (parse_cli_options(vm, argc, argv)) return ERROR_IN_COMMAND_LINE;
if(vm.count("verbose")){ if (vm.count("verbose")) {
auto l = logging::as_log_level(vm["verbose"].as<int>()); auto l = logging::as_log_level(vm["verbose"].as<int>());
LOGGER(DEFAULT)::reporting_level() = l; LOGGER(DEFAULT)::reporting_level() = l;
LOGGER(connection)::reporting_level()=l; LOGGER(connection)::reporting_level() = l;
} }
if(vm.count("log-file")){ if (vm.count("log-file")) {
// configure the connection logger // configure the connection logger
auto f = fopen(vm["log-file"].as<std::string>().c_str(), "w"); auto f = fopen(vm["log-file"].as<std::string>().c_str(), "w");
LOG_OUTPUT(DEFAULT)::stream() = f; LOG_OUTPUT(DEFAULT)::stream() = f;
@ -66,48 +65,47 @@ int main(int argc, char *argv[]) {
// application code comes here // // application code comes here //
iss::init_jit(argc, argv); iss::init_jit(argc, argv);
bool dump=vm.count("dump-ir"); bool dump = vm.count("dump-ir");
// instantiate the simulator // instantiate the simulator
std::unique_ptr<iss::vm_if> cpu = nullptr; std::unique_ptr<iss::vm_if> cpu = nullptr;
if(vm.count("rv64")==1){ if (vm.count("rv64") == 1) {
if(vm.count("gdb-port")==1) if (vm.count("gdb-port") == 1)
cpu = iss::create<iss::arch::rv64ia>("rv64ia", vm["gdb-port"].as<unsigned>(), dump); cpu = iss::create<iss::arch::rv64ia>("rv64ia", vm["gdb-port"].as<unsigned>(), dump);
else else
cpu = iss::create<iss::arch::rv64ia>("rv64ia", dump); cpu = iss::create<iss::arch::rv64ia>("rv64ia", dump);
} else { } else {
if(vm.count("gdb-port")==1) if (vm.count("gdb-port") == 1)
cpu = iss::create<iss::arch::rv32imac>("rv32ima", vm["gdb-port"].as<unsigned>(), dump); cpu = iss::create<iss::arch::rv32imac>("rv32ima", vm["gdb-port"].as<unsigned>(), dump);
else else
cpu = iss::create<iss::arch::rv32imac>("rv32ima", dump); cpu = iss::create<iss::arch::rv32imac>("rv32ima", dump);
} }
if(vm.count("elf")){ if (vm.count("elf")) {
for(std::string input: vm["elf"].as<std::vector<std::string> >()) for (std::string input : vm["elf"].as<std::vector<std::string>>()) cpu->get_arch()->load_file(input);
cpu->get_arch()->load_file(input); } else if (vm.count("mem")) {
} else if(vm.count("mem")){ cpu->get_arch()->load_file(vm["mem"].as<std::string>(), iss::arch::traits<iss::arch::rv32imac>::MEM);
cpu->get_arch()->load_file(vm["mem"].as<std::string>() , iss::arch::traits<iss::arch::rv32imac>::MEM);
} }
if(vm.count("disass")){ if (vm.count("disass")) {
cpu->setDisassEnabled(true); cpu->setDisassEnabled(true);
LOGGER(disass)::reporting_level()=logging::INFO; LOGGER(disass)::reporting_level() = logging::INFO;
auto file_name=vm["disass"].as<std::string>(); auto file_name = vm["disass"].as<std::string>();
if (file_name.length() > 0) { if (file_name.length() > 0) {
LOG_OUTPUT(disass)::stream() = fopen(file_name.c_str(), "w"); LOG_OUTPUT(disass)::stream() = fopen(file_name.c_str(), "w");
LOGGER(disass)::print_time() = false; LOGGER(disass)::print_time() = false;
LOGGER(disass)::print_severity() = false; LOGGER(disass)::print_severity() = false;
} }
} }
if(vm.count("reset")){ if (vm.count("reset")) {
auto str = vm["reset"].as<std::string>(); auto str = vm["reset"].as<std::string>();
auto start_address = str.find("0x")==0? std::stoull(str, 0, 16):std::stoull(str, 0, 10); auto start_address = str.find("0x") == 0 ? std::stoull(str, 0, 16) : std::stoull(str, 0, 10);
cpu->reset(start_address); cpu->reset(start_address);
} else { } else {
cpu->reset(); cpu->reset();
} }
return cpu->start(vm["cycles"].as<int64_t>()); return cpu->start(vm["cycles"].as<int64_t>());
} catch(std::exception& e){ } catch (std::exception &e) {
LOG(ERROR) << "Unhandled Exception reached the top of main: " LOG(ERROR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit"
<< e.what() << ", application will now exit" << std::endl; << std::endl;
return ERROR_UNHANDLED_EXCEPTION; return ERROR_UNHANDLED_EXCEPTION;
} }
} }

2
sc-components

@ -1 +1 @@
Subproject commit 46d79504a8a5a6a9541b19a6774fb8161350a0a4 Subproject commit a5c9101b71da3824af4a54322232de270c5547de