DBT-RISE/DBT-RISE-TGC
12
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

Applied clang-format

Browse Source
This commit is contained in:
Eyck Jentzsch
2017-09-22 11:23:23 +02:00
parent 39150b68c0
commit b38319f9c2
34 changed files with 5579 additions and 6723 deletions
Download Patch File Download Diff File Expand all files Collapse all files

791
riscv/src/internal/vm_riscv.in.cpp
View File

File diff suppressed because it is too large Load Diff

4872
riscv/src/internal/vm_rv32imac.cpp
View File

File diff suppressed because it is too large Load Diff

3952
riscv/src/internal/vm_rv64ia.cpp
View File

File diff suppressed because it is too large Load Diff

40
riscv/src/iss/rv32imac.cpp
View File

@@ -1,21 +1,21 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -27,7 +27,7 @@
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
//
// Created on: Tue Aug 29 16:45:20 CEST 2017
// * rv32imac.cpp Author: <CoreDSL Generator>
//
@@ -46,31 +46,27 @@ extern "C" {
#ifdef __cplusplus
}
#endif
#include <fstream>
#include <cstdio>
#include <cstring>
#include <fstream>
using namespace iss::arch;
rv32imac::rv32imac() {
reg.icount=0;
}
rv32imac::rv32imac() { reg.icount = 0; }
rv32imac::~rv32imac(){
}
rv32imac::~rv32imac() {}
void rv32imac::reset(uint64_t address) {
for(size_t i=0; i<traits<rv32imac>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<rv32imac>::reg_t),0));
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.trap_state=0;
reg.machine_state=0x3;
for (size_t i = 0; i < traits<rv32imac>::NUM_REGS; ++i)
set_reg(i, std::vector<uint8_t>(sizeof(traits<rv32imac>::reg_t), 0));
reg.PC = address;
reg.NEXT_PC = reg.PC;
reg.trap_state = 0;
reg.machine_state = 0x3;
}
uint8_t* rv32imac::get_regs_base_ptr(){
return reinterpret_cast<uint8_t*>(&reg);
}
uint8_t *rv32imac::get_regs_base_ptr() { return reinterpret_cast<uint8_t *>(&reg); }
rv32imac::phys_addr_t rv32imac::v2p(const iss::addr_t& pc) {
return phys_addr_t(pc); //change logical address to physical address
rv32imac::phys_addr_t rv32imac::v2p(const iss::addr_t &pc) {
return phys_addr_t(pc); // change logical address to physical address
}

40
riscv/src/iss/rv64ia.cpp
View File

@@ -1,21 +1,21 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -27,7 +27,7 @@
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
//
// Created on: Tue Sep 05 18:57:24 CEST 2017
// * rv64ia.cpp Author: <CoreDSL Generator>
//
@@ -46,31 +46,27 @@ extern "C" {
#ifdef __cplusplus
}
#endif
#include <fstream>
#include <cstdio>
#include <cstring>
#include <fstream>
using namespace iss::arch;
rv64ia::rv64ia() {
reg.icount=0;
}
rv64ia::rv64ia() { reg.icount = 0; }
rv64ia::~rv64ia(){
}
rv64ia::~rv64ia() {}
void rv64ia::reset(uint64_t address) {
for(size_t i=0; i<traits<rv64ia>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<rv64ia>::reg_t),0));
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.trap_state=0;
reg.machine_state=0x0;
for (size_t i = 0; i < traits<rv64ia>::NUM_REGS; ++i)
set_reg(i, std::vector<uint8_t>(sizeof(traits<rv64ia>::reg_t), 0));
reg.PC = address;
reg.NEXT_PC = reg.PC;
reg.trap_state = 0;
reg.machine_state = 0x0;
}
uint8_t* rv64ia::get_regs_base_ptr(){
return reinterpret_cast<uint8_t*>(&reg);
}
uint8_t *rv64ia::get_regs_base_ptr() { return reinterpret_cast<uint8_t *>(&reg); }
rv64ia::phys_addr_t rv64ia::v2p(const iss::addr_t& pc) {
return phys_addr_t(pc); //change logical address to physical address
rv64ia::phys_addr_t rv64ia::v2p(const iss::addr_t &pc) {
return phys_addr_t(pc); // change logical address to physical address
}

64
riscv/src/main.cpp
View File

@@ -1,21 +1,21 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -27,37 +27,36 @@
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
//
// Contributors:
// eyck@minres.com - initial API and implementation
////////////////////////////////////////////////////////////////////////////////
#include <cli_options.h>
#include <iss/iss.h>
#include <iostream>
#include <iss/iss.h>
#include <iss/log_categories.h>
#include <boost/lexical_cast.hpp>
#include <iss/arch/rv32imac.h>
#include <iss/arch/rv64ia.h>
#include <iss/jit/MCJIThelper.h>
#include <boost/lexical_cast.hpp>
#include <iss/log_categories.h>
namespace po= boost::program_options;
namespace po = boost::program_options;
int main(int argc, char *argv[]) {
try{
try {
/*
* Define and parse the program options
*/
po::variables_map vm;
if(parse_cli_options(vm, argc, argv)) return ERROR_IN_COMMAND_LINE;
if(vm.count("verbose")){
if (parse_cli_options(vm, argc, argv)) return ERROR_IN_COMMAND_LINE;
if (vm.count("verbose")) {
auto l = logging::as_log_level(vm["verbose"].as<int>());
LOGGER(DEFAULT)::reporting_level() = l;
LOGGER(connection)::reporting_level()=l;
LOGGER(connection)::reporting_level() = l;
}
if(vm.count("log-file")){
if (vm.count("log-file")) {
// configure the connection logger
auto f = fopen(vm["log-file"].as<std::string>().c_str(), "w");
LOG_OUTPUT(DEFAULT)::stream() = f;
@@ -66,48 +65,47 @@ int main(int argc, char *argv[]) {
// application code comes here //
iss::init_jit(argc, argv);
bool dump=vm.count("dump-ir");
bool dump = vm.count("dump-ir");
// instantiate the simulator
std::unique_ptr<iss::vm_if> cpu = nullptr;
if(vm.count("rv64")==1){
if(vm.count("gdb-port")==1)
if (vm.count("rv64") == 1) {
if (vm.count("gdb-port") == 1)
cpu = iss::create<iss::arch::rv64ia>("rv64ia", vm["gdb-port"].as<unsigned>(), dump);
else
cpu = iss::create<iss::arch::rv64ia>("rv64ia", dump);
} else {
if(vm.count("gdb-port")==1)
if (vm.count("gdb-port") == 1)
cpu = iss::create<iss::arch::rv32imac>("rv32ima", vm["gdb-port"].as<unsigned>(), dump);
else
cpu = iss::create<iss::arch::rv32imac>("rv32ima", dump);
}
if(vm.count("elf")){
for(std::string input: vm["elf"].as<std::vector<std::string> >())
cpu->get_arch()->load_file(input);
} else if(vm.count("mem")){
cpu->get_arch()->load_file(vm["mem"].as<std::string>() , iss::arch::traits<iss::arch::rv32imac>::MEM);
if (vm.count("elf")) {
for (std::string input : vm["elf"].as<std::vector<std::string>>()) cpu->get_arch()->load_file(input);
} else if (vm.count("mem")) {
cpu->get_arch()->load_file(vm["mem"].as<std::string>(), iss::arch::traits<iss::arch::rv32imac>::MEM);
}
if(vm.count("disass")){
if (vm.count("disass")) {
cpu->setDisassEnabled(true);
LOGGER(disass)::reporting_level()=logging::INFO;
auto file_name=vm["disass"].as<std::string>();
LOGGER(disass)::reporting_level() = logging::INFO;
auto file_name = vm["disass"].as<std::string>();
if (file_name.length() > 0) {
LOG_OUTPUT(disass)::stream() = fopen(file_name.c_str(), "w");
LOGGER(disass)::print_time() = false;
LOGGER(disass)::print_severity() = false;
}
}
if(vm.count("reset")){
if (vm.count("reset")) {
auto str = vm["reset"].as<std::string>();
auto start_address = str.find("0x")==0? std::stoull(str, 0, 16):std::stoull(str, 0, 10);
auto start_address = str.find("0x") == 0 ? std::stoull(str, 0, 16) : std::stoull(str, 0, 10);
cpu->reset(start_address);
} else {
cpu->reset();
}
return cpu->start(vm["cycles"].as<int64_t>());
} catch(std::exception& e){
LOG(ERROR) << "Unhandled Exception reached the top of main: "
<< e.what() << ", application will now exit" << std::endl;
} catch (std::exception &e) {
LOG(ERROR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit"
<< std::endl;
return ERROR_UNHANDLED_EXCEPTION;
}
}