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Applied clang-format

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This commit is contained in:
Eyck Jentzsch
2017-09-22 11:23:23 +02:00
parent 39150b68c0
commit b38319f9c2
34 changed files with 5579 additions and 6723 deletions
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62
riscv/incl/cli_options.h
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@ -1,21 +1,21 @@
/*******************************************************************************
* Copyright (C) 2017, MINRES Technologies GmbH
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@ -27,7 +27,7 @@
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*
* Contributors:
* eyck@minres.com - initial API and implementation
******************************************************************************/
@ -35,49 +35,47 @@
#ifndef _CLI_OPTIONS_H_
#define _CLI_OPTIONS_H_
#include <boost/program_options.hpp>
#include <util/logging.h>
#include <iostream>
#include <cstdio>
#include <iostream>
#include <util/logging.h>
const size_t ERROR_IN_COMMAND_LINE = 1;
const size_t SUCCESS = 0;
const size_t ERROR_UNHANDLED_EXCEPTION = 2;
inline int parse_cli_options(boost::program_options::variables_map& vm, int argc, char *argv[]){
inline int parse_cli_options(boost::program_options::variables_map &vm, int argc, char *argv[]) {
namespace po = boost::program_options;
po::options_description desc("Options");
desc.add_options()
("help,h", "Print help message")
("verbose,v", po::value<int>()->implicit_value(0), "Sets logging verbosity")
("vmodule", po::value<std::string>(),"Defines the module(s) to be logged")
("logging-flags", po::value<int>(),"Sets logging flag(s).")
("log-file", po::value<std::string>(),"Sets default log file.")
("disass,d", po::value<std::string>()->implicit_value(""),"Enables disassembly")
("elf,l", po::value< std::vector<std::string> >(), "ELF file(s) to load")
("gdb-port,g", po::value<unsigned>(), "enable gdb server and specify port to use")
("input,i", po::value<std::string>(), "the elf file to load (instead of hex files)")
("dump-ir", "dump the intermediate representation")
("cycles,c", po::value<int64_t>()->default_value(-1), "number of cycles to run")
("systemc,s", "Run as SystemC simulation")
("time", po::value<int>(), "SystemC siimulation time in ms")
("reset,r", po::value<std::string>(), "reset address")
("trace", po::value<uint8_t>(), "enable tracing, or cmbintation of 1=signals and 2=TX text, 4=TX compressed text, 6=TX in SQLite")\
("mem,m", po::value<std::string>(), "the memory input file")
("rv64", "run RV64");
desc.add_options()("help,h", "Print help message")("verbose,v", po::value<int>()->implicit_value(0),
"Sets logging verbosity")("vmodule", po::value<std::string>(),
"Defines the module(s) to be logged")(
"logging-flags", po::value<int>(), "Sets logging flag(s).")("log-file", po::value<std::string>(),
"Sets default log file.")(
"disass,d", po::value<std::string>()->implicit_value(""),
"Enables disassembly")("elf,l", po::value<std::vector<std::string>>(), "ELF file(s) to load")(
"gdb-port,g", po::value<unsigned>(), "enable gdb server and specify port to use")(
"input,i", po::value<std::string>(), "the elf file to load (instead of hex files)")(
"dump-ir", "dump the intermediate representation")("cycles,c", po::value<int64_t>()->default_value(-1),
"number of cycles to run")(
"systemc,s", "Run as SystemC simulation")("time", po::value<int>(), "SystemC siimulation time in ms")(
"reset,r", po::value<std::string>(), "reset address")(
"trace", po::value<uint8_t>(), "enable tracing, or cmbintation of 1=signals and 2=TX text, 4=TX "
"compressed text, 6=TX in SQLite")("mem,m", po::value<std::string>(),
"the memory input file")("rv64", "run RV64");
try {
po::store(po::parse_command_line(argc, argv, desc), vm); // can throw
// --help option
if ( vm.count("help") ){
if (vm.count("help")) {
std::cout << "DBT-RISE-RiscV" << std::endl << desc << std::endl;
return SUCCESS;
}
po::notify(vm); // throws on error, so do after help in case
} catch(po::error& e){
// there are problems
std::cerr << "ERROR: " << e.what() << std::endl << std::endl;
} catch (po::error &e) {
// there are problems
std::cerr << "ERROR: " << e.what() << std::endl << std::endl;
std::cerr << desc << std::endl;
return ERROR_IN_COMMAND_LINE;
}
return SUCCESS;
return SUCCESS;
}
#endif /* _CLI_OPTIONS_H_ */

1382
riscv/incl/iss/arch/riscv_hart_msu_vp.h
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83
riscv/incl/iss/arch/rv32imac.h
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@ -1,21 +1,21 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@ -27,7 +27,7 @@
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
//
// Created on: Thu Sep 21 17:01:54 CEST 2017
// * rv32imac.h Author: <CoreDSL Generator>
//
@ -36,19 +36,30 @@
#ifndef _RV32IMAC_H_
#define _RV32IMAC_H_
#include <iss/arch/traits.h>
#include <iss/arch_if.h>
#include <iss/vm_if.h>
#include <iss/arch/traits.h>
namespace iss {
namespace arch {
struct rv32imac;
template<>
struct traits<rv32imac> {
template <> struct traits<rv32imac> {
enum constants {XLEN=32,XLEN2=64,XLEN_BIT_MASK=31,PCLEN=32,fence=0,fencei=1,fencevmal=2,fencevmau=3,MISA_VAL=1075056897,PGSIZE=4096,PGMASK=4095};
enum constants {
XLEN = 32,
XLEN2 = 64,
XLEN_BIT_MASK = 31,
PCLEN = 32,
fence = 0,
fencei = 1,
fencevmal = 2,
fencevmau = 3,
MISA_VAL = 1075056897,
PGSIZE = 4096,
PGMASK = 4095
};
enum reg_e {
X0,
@ -85,7 +96,7 @@ struct traits<rv32imac> {
X31,
PC,
NUM_REGS,
NEXT_PC=NUM_REGS,
NEXT_PC = NUM_REGS,
TRAP_STATE,
PENDING_TRAP,
MACHINE_STATE,
@ -96,61 +107,64 @@ struct traits<rv32imac> {
typedef uint32_t addr_t;
typedef uint32_t code_word_t; //TODO: check removal
typedef uint32_t code_word_t; // TODO: check removal
typedef iss::typed_addr_t<iss::VIRTUAL> virt_addr_t;
typedef iss::typed_addr_t<iss::VIRTUAL> virt_addr_t;
typedef iss::typed_addr_t<iss::PHYSICAL> phys_addr_t;
constexpr static unsigned reg_bit_width(unsigned r) {
const uint32_t RV32IMAC_reg_size[] = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64};
const uint32_t RV32IMAC_reg_size[] = {32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 64};
return RV32IMAC_reg_size[r];
}
constexpr static unsigned reg_byte_offset(unsigned r) {
const uint32_t RV32IMAC_reg_byte_offset[] = {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,152,160};
const uint32_t RV32IMAC_reg_byte_offset[] = {0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48,
52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 96, 100,
104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 152, 160};
return RV32IMAC_reg_byte_offset[r];
}
enum sreg_flag_e {FLAGS};
enum mem_type_e {MEM,CSR,FENCE,RES};
enum sreg_flag_e { FLAGS };
enum mem_type_e { MEM, CSR, FENCE, RES };
};
struct rv32imac: public arch_if {
struct rv32imac : public arch_if {
using virt_addr_t = typename traits<rv32imac>::virt_addr_t;
using phys_addr_t = typename traits<rv32imac>::phys_addr_t;
using reg_t = typename traits<rv32imac>::reg_t;
using reg_t = typename traits<rv32imac>::reg_t;
using addr_t = typename traits<rv32imac>::addr_t;
rv32imac();
~rv32imac();
virtual void reset(uint64_t address=0) override;
virtual void reset(uint64_t address = 0) override;
virtual uint8_t* get_regs_base_ptr() override;
virtual uint8_t *get_regs_base_ptr() override;
/// deprecated
virtual void get_reg(short idx, std::vector<uint8_t>& value) override {}
virtual void set_reg(short idx, const std::vector<uint8_t>& value) override {}
virtual void get_reg(short idx, std::vector<uint8_t> &value) override {}
virtual void set_reg(short idx, const std::vector<uint8_t> &value) override {}
/// deprecated
virtual bool get_flag(int flag) override {return false;}
virtual void set_flag(int, bool value) override {};
virtual bool get_flag(int flag) override { return false; }
virtual void set_flag(int, bool value) override{};
/// deprecated
virtual void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
virtual void update_flags(operations op, uint64_t opr1, uint64_t opr2) override{};
virtual void notify_phase(exec_phase phase){
if(phase==ISTART){
virtual void notify_phase(exec_phase phase) {
if (phase == ISTART) {
++reg.icount;
reg.PC=reg.NEXT_PC;
reg.trap_state=reg.pending_trap;
reg.PC = reg.NEXT_PC;
reg.trap_state = reg.pending_trap;
}
}
uint64_t get_icount() { return reg.icount;}
uint64_t get_icount() { return reg.icount; }
virtual phys_addr_t v2p(const iss::addr_t& pc);
virtual phys_addr_t v2p(const iss::addr_t &pc);
virtual iss::sync_type needed_sync() const { return iss::PRE_SYNC; }
@ -194,7 +208,6 @@ protected:
uint64_t icount;
} reg;
};
}
}
}
#endif /* _RV32IMAC_H_ */

82
riscv/incl/iss/arch/rv64ia.h
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@ -1,21 +1,21 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@ -27,7 +27,7 @@
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
//
// Created on: Thu Sep 21 17:01:54 CEST 2017
// * rv64ia.h Author: <CoreDSL Generator>
//
@ -36,19 +36,30 @@
#ifndef _RV64IA_H_
#define _RV64IA_H_
#include <iss/arch/traits.h>
#include <iss/arch_if.h>
#include <iss/vm_if.h>
#include <iss/arch/traits.h>
namespace iss {
namespace arch {
struct rv64ia;
template<>
struct traits<rv64ia> {
template <> struct traits<rv64ia> {
enum constants {XLEN=64,XLEN2=128,XLEN_BIT_MASK=63,PCLEN=64,fence=0,fencei=1,fencevmal=2,fencevmau=3,MISA_VAL=2147750144,PGSIZE=4096,PGMASK=4095};
enum constants {
XLEN = 64,
XLEN2 = 128,
XLEN_BIT_MASK = 63,
PCLEN = 64,
fence = 0,
fencei = 1,
fencevmal = 2,
fencevmau = 3,
MISA_VAL = 2147750144,
PGSIZE = 4096,
PGMASK = 4095
};
enum reg_e {
X0,
@ -85,7 +96,7 @@ struct traits<rv64ia> {
X31,
PC,
NUM_REGS,
NEXT_PC=NUM_REGS,
NEXT_PC = NUM_REGS,
TRAP_STATE,
PENDING_TRAP,
MACHINE_STATE,
@ -96,61 +107,63 @@ struct traits<rv64ia> {
typedef uint64_t addr_t;
typedef uint64_t code_word_t; //TODO: check removal
typedef uint64_t code_word_t; // TODO: check removal
typedef iss::typed_addr_t<iss::VIRTUAL> virt_addr_t;
typedef iss::typed_addr_t<iss::VIRTUAL> virt_addr_t;
typedef iss::typed_addr_t<iss::PHYSICAL> phys_addr_t;
constexpr static unsigned reg_bit_width(unsigned r) {
const uint32_t RV64IA_reg_size[] = {64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,32,32,32,64};
const uint32_t RV64IA_reg_size[] = {64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 32, 32, 32, 64};
return RV64IA_reg_size[r];
}
constexpr static unsigned reg_byte_offset(unsigned r) {
const uint32_t RV64IA_reg_byte_offset[] = {0,8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,256,264,272,276,280,288,296};
const uint32_t RV64IA_reg_byte_offset[] = {0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96,
104, 112, 120, 128, 136, 144, 152, 160, 168, 176, 184, 192, 200,
208, 216, 224, 232, 240, 248, 256, 264, 272, 276, 280, 288, 296};
return RV64IA_reg_byte_offset[r];
}
enum sreg_flag_e {FLAGS};
enum mem_type_e {MEM,CSR,FENCE,RES};
enum sreg_flag_e { FLAGS };
enum mem_type_e { MEM, CSR, FENCE, RES };
};
struct rv64ia: public arch_if {
struct rv64ia : public arch_if {
using virt_addr_t = typename traits<rv64ia>::virt_addr_t;
using phys_addr_t = typename traits<rv64ia>::phys_addr_t;
using reg_t = typename traits<rv64ia>::reg_t;
using reg_t = typename traits<rv64ia>::reg_t;
using addr_t = typename traits<rv64ia>::addr_t;
rv64ia();
~rv64ia();
virtual void reset(uint64_t address=0) override;
virtual void reset(uint64_t address = 0) override;
virtual uint8_t* get_regs_base_ptr() override;
virtual uint8_t *get_regs_base_ptr() override;
/// deprecated
virtual void get_reg(short idx, std::vector<uint8_t>& value) override {}
virtual void set_reg(short idx, const std::vector<uint8_t>& value) override {}
virtual void get_reg(short idx, std::vector<uint8_t> &value) override {}
virtual void set_reg(short idx, const std::vector<uint8_t> &value) override {}
/// deprecated
virtual bool get_flag(int flag) override {return false;}
virtual void set_flag(int, bool value) override {};
virtual bool get_flag(int flag) override { return false; }
virtual void set_flag(int, bool value) override{};
/// deprecated
virtual void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
virtual void update_flags(operations op, uint64_t opr1, uint64_t opr2) override{};
virtual void notify_phase(exec_phase phase){
if(phase==ISTART){
virtual void notify_phase(exec_phase phase) {
if (phase == ISTART) {
++reg.icount;
reg.PC=reg.NEXT_PC;
reg.trap_state=reg.pending_trap;
reg.PC = reg.NEXT_PC;
reg.trap_state = reg.pending_trap;
}
}
uint64_t get_icount() { return reg.icount;}
uint64_t get_icount() { return reg.icount; }
virtual phys_addr_t v2p(const iss::addr_t& pc);
virtual phys_addr_t v2p(const iss::addr_t &pc);
virtual iss::sync_type needed_sync() const { return iss::PRE_SYNC; }
@ -194,7 +207,6 @@ protected:
uint64_t icount;
} reg;
};
}
}
}
#endif /* _RV64IA_H_ */

791
riscv/src/internal/vm_riscv.in.cpp
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4872
riscv/src/internal/vm_rv32imac.cpp
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3952
riscv/src/internal/vm_rv64ia.cpp
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40
riscv/src/iss/rv32imac.cpp
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@ -1,21 +1,21 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@ -27,7 +27,7 @@
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
//
// Created on: Tue Aug 29 16:45:20 CEST 2017
// * rv32imac.cpp Author: <CoreDSL Generator>
//
@ -46,31 +46,27 @@ extern "C" {
#ifdef __cplusplus
}
#endif
#include <fstream>
#include <cstdio>
#include <cstring>
#include <fstream>
using namespace iss::arch;
rv32imac::rv32imac() {
reg.icount=0;
}
rv32imac::rv32imac() { reg.icount = 0; }
rv32imac::~rv32imac(){
}
rv32imac::~rv32imac() {}
void rv32imac::reset(uint64_t address) {
for(size_t i=0; i<traits<rv32imac>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<rv32imac>::reg_t),0));
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.trap_state=0;
reg.machine_state=0x3;
for (size_t i = 0; i < traits<rv32imac>::NUM_REGS; ++i)
set_reg(i, std::vector<uint8_t>(sizeof(traits<rv32imac>::reg_t), 0));
reg.PC = address;
reg.NEXT_PC = reg.PC;
reg.trap_state = 0;
reg.machine_state = 0x3;
}
uint8_t* rv32imac::get_regs_base_ptr(){
return reinterpret_cast<uint8_t*>(&reg);
}
uint8_t *rv32imac::get_regs_base_ptr() { return reinterpret_cast<uint8_t *>(&reg); }
rv32imac::phys_addr_t rv32imac::v2p(const iss::addr_t& pc) {
return phys_addr_t(pc); //change logical address to physical address
rv32imac::phys_addr_t rv32imac::v2p(const iss::addr_t &pc) {
return phys_addr_t(pc); // change logical address to physical address
}

40
riscv/src/iss/rv64ia.cpp
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@ -1,21 +1,21 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@ -27,7 +27,7 @@
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
//
// Created on: Tue Sep 05 18:57:24 CEST 2017
// * rv64ia.cpp Author: <CoreDSL Generator>
//
@ -46,31 +46,27 @@ extern "C" {
#ifdef __cplusplus
}
#endif
#include <fstream>
#include <cstdio>
#include <cstring>
#include <fstream>
using namespace iss::arch;
rv64ia::rv64ia() {
reg.icount=0;
}
rv64ia::rv64ia() { reg.icount = 0; }
rv64ia::~rv64ia(){
}
rv64ia::~rv64ia() {}
void rv64ia::reset(uint64_t address) {
for(size_t i=0; i<traits<rv64ia>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<rv64ia>::reg_t),0));
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.trap_state=0;
reg.machine_state=0x0;
for (size_t i = 0; i < traits<rv64ia>::NUM_REGS; ++i)
set_reg(i, std::vector<uint8_t>(sizeof(traits<rv64ia>::reg_t), 0));
reg.PC = address;
reg.NEXT_PC = reg.PC;
reg.trap_state = 0;
reg.machine_state = 0x0;
}
uint8_t* rv64ia::get_regs_base_ptr(){
return reinterpret_cast<uint8_t*>(&reg);
}
uint8_t *rv64ia::get_regs_base_ptr() { return reinterpret_cast<uint8_t *>(&reg); }
rv64ia::phys_addr_t rv64ia::v2p(const iss::addr_t& pc) {
return phys_addr_t(pc); //change logical address to physical address
rv64ia::phys_addr_t rv64ia::v2p(const iss::addr_t &pc) {
return phys_addr_t(pc); // change logical address to physical address
}

64
riscv/src/main.cpp
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@ -1,21 +1,21 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@ -27,37 +27,36 @@
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
//
// Contributors:
// eyck@minres.com - initial API and implementation
////////////////////////////////////////////////////////////////////////////////
#include <cli_options.h>
#include <iss/iss.h>
#include <iostream>
#include <iss/iss.h>
#include <iss/log_categories.h>
#include <boost/lexical_cast.hpp>
#include <iss/arch/rv32imac.h>
#include <iss/arch/rv64ia.h>
#include <iss/jit/MCJIThelper.h>
#include <boost/lexical_cast.hpp>
#include <iss/log_categories.h>
namespace po= boost::program_options;
namespace po = boost::program_options;
int main(int argc, char *argv[]) {
try{
try {
/*
* Define and parse the program options
*/
po::variables_map vm;
if(parse_cli_options(vm, argc, argv)) return ERROR_IN_COMMAND_LINE;
if(vm.count("verbose")){
if (parse_cli_options(vm, argc, argv)) return ERROR_IN_COMMAND_LINE;
if (vm.count("verbose")) {
auto l = logging::as_log_level(vm["verbose"].as<int>());
LOGGER(DEFAULT)::reporting_level() = l;
LOGGER(connection)::reporting_level()=l;
LOGGER(connection)::reporting_level() = l;
}
if(vm.count("log-file")){
if (vm.count("log-file")) {
// configure the connection logger
auto f = fopen(vm["log-file"].as<std::string>().c_str(), "w");
LOG_OUTPUT(DEFAULT)::stream() = f;
@ -66,48 +65,47 @@ int main(int argc, char *argv[]) {
// application code comes here //
iss::init_jit(argc, argv);
bool dump=vm.count("dump-ir");
bool dump = vm.count("dump-ir");
// instantiate the simulator
std::unique_ptr<iss::vm_if> cpu = nullptr;
if(vm.count("rv64")==1){
if(vm.count("gdb-port")==1)
if (vm.count("rv64") == 1) {
if (vm.count("gdb-port") == 1)
cpu = iss::create<iss::arch::rv64ia>("rv64ia", vm["gdb-port"].as<unsigned>(), dump);
else
cpu = iss::create<iss::arch::rv64ia>("rv64ia", dump);
} else {
if(vm.count("gdb-port")==1)
if (vm.count("gdb-port") == 1)
cpu = iss::create<iss::arch::rv32imac>("rv32ima", vm["gdb-port"].as<unsigned>(), dump);
else
cpu = iss::create<iss::arch::rv32imac>("rv32ima", dump);
}
if(vm.count("elf")){
for(std::string input: vm["elf"].as<std::vector<std::string> >())
cpu->get_arch()->load_file(input);
} else if(vm.count("mem")){
cpu->get_arch()->load_file(vm["mem"].as<std::string>() , iss::arch::traits<iss::arch::rv32imac>::MEM);
if (vm.count("elf")) {
for (std::string input : vm["elf"].as<std::vector<std::string>>()) cpu->get_arch()->load_file(input);
} else if (vm.count("mem")) {
cpu->get_arch()->load_file(vm["mem"].as<std::string>(), iss::arch::traits<iss::arch::rv32imac>::MEM);
}
if(vm.count("disass")){
if (vm.count("disass")) {
cpu->setDisassEnabled(true);
LOGGER(disass)::reporting_level()=logging::INFO;
auto file_name=vm["disass"].as<std::string>();
LOGGER(disass)::reporting_level() = logging::INFO;
auto file_name = vm["disass"].as<std::string>();
if (file_name.length() > 0) {
LOG_OUTPUT(disass)::stream() = fopen(file_name.c_str(), "w");
LOGGER(disass)::print_time() = false;
LOGGER(disass)::print_severity() = false;
}
}
if(vm.count("reset")){
if (vm.count("reset")) {
auto str = vm["reset"].as<std::string>();
auto start_address = str.find("0x")==0? std::stoull(str, 0, 16):std::stoull(str, 0, 10);
auto start_address = str.find("0x") == 0 ? std::stoull(str, 0, 16) : std::stoull(str, 0, 10);
cpu->reset(start_address);
} else {
cpu->reset();
}
return cpu->start(vm["cycles"].as<int64_t>());
} catch(std::exception& e){
LOG(ERROR) << "Unhandled Exception reached the top of main: "
<< e.what() << ", application will now exit" << std::endl;
} catch (std::exception &e) {
LOG(ERROR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit"
<< std::endl;
return ERROR_UNHANDLED_EXCEPTION;
}
}