DBT-RISE/DBT-RISE-TGC
12
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

fix formatting

Browse Source
This commit is contained in:
Stanislaw Kaushanski
2024-03-19 11:47:12 +01:00
parent 6c986d38d8
commit b25b7848c6
5 changed files with 20 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
src/iss/arch/riscv_hart_mu_p.h
View File

@ -916,19 +916,19 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
switch(length) {
case 8:
CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x"
<< std::hex << addr;
<< std::hex << addr;
break;
case 4:
CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x"
<< std::hex << addr;
<< std::hex << addr;
break;
case 2:
CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x"
<< std::hex << addr;
<< std::hex << addr;
break;
case 1:
CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x"
<< std::hex << addr;
<< std::hex << addr;
break;
default:
CPPLOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
@ -1349,10 +1349,10 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned l
case 0:
if(hostvar != 0x1) {
CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
<< "), stopping simulation";
<< "), stopping simulation";
} else {
CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
<< "), stopping simulation";
<< "), stopping simulation";
}
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
this->interrupt_sim = hostvar;