diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h
index db7e715..90a7d5f 100644
--- a/src/iss/arch/riscv_hart_m_p.h
+++ b/src/iss/arch/riscv_hart_m_p.h
@@ -730,19 +730,19 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
     switch(length) {
     case 8:
         CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x"
-                   << std::hex << addr;
+                      << std::hex << addr;
         break;
     case 4:
         CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x"
-                   << std::hex << addr;
+                      << std::hex << addr;
         break;
     case 2:
         CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x"
-                   << std::hex << addr;
+                      << std::hex << addr;
         break;
     case 1:
         CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x"
-                   << std::hex << addr;
+                      << std::hex << addr;
         break;
     default:
         CPPLOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
@@ -1118,10 +1118,10 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned le
                     case 0:
                         if(hostvar != 0x1) {
                             CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
-                                       << "), stopping simulation";
+                                          << "), stopping simulation";
                         } else {
                             CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
-                                      << "), stopping simulation";
+                                         << "), stopping simulation";
                         }
                         this->reg.trap_state = std::numeric_limits<uint32_t>::max();
                         this->interrupt_sim = hostvar;
diff --git a/src/iss/arch/riscv_hart_msu_vp.h b/src/iss/arch/riscv_hart_msu_vp.h
index d3339e3..1a350b8 100644
--- a/src/iss/arch/riscv_hart_msu_vp.h
+++ b/src/iss/arch/riscv_hart_msu_vp.h
@@ -729,19 +729,19 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
     switch(length) {
     case 8:
         CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x"
-                   << std::hex << addr;
+                      << std::hex << addr;
         break;
     case 4:
         CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x"
-                   << std::hex << addr;
+                      << std::hex << addr;
         break;
     case 2:
         CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x"
-                   << std::hex << addr;
+                      << std::hex << addr;
         break;
     case 1:
         CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x"
-                   << std::hex << addr;
+                      << std::hex << addr;
         break;
     default:
         CPPLOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
@@ -1106,10 +1106,10 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_add
                     case 0:
                         if(hostvar != 0x1) {
                             CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
-                                       << "), stopping simulation";
+                                          << "), stopping simulation";
                         } else {
                             CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
-                                      << "), stopping simulation";
+                                         << "), stopping simulation";
                         }
                         this->reg.trap_state = std::numeric_limits<uint32_t>::max();
                         this->interrupt_sim = hostvar;
diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h
index 4597ce7..8f2a07f 100644
--- a/src/iss/arch/riscv_hart_mu_p.h
+++ b/src/iss/arch/riscv_hart_mu_p.h
@@ -916,19 +916,19 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
     switch(length) {
     case 8:
         CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x"
-                   << std::hex << addr;
+                      << std::hex << addr;
         break;
     case 4:
         CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x"
-                   << std::hex << addr;
+                      << std::hex << addr;
         break;
     case 2:
         CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x"
-                   << std::hex << addr;
+                      << std::hex << addr;
         break;
     case 1:
         CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x"
-                   << std::hex << addr;
+                      << std::hex << addr;
         break;
     default:
         CPPLOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
@@ -1349,10 +1349,10 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned l
                     case 0:
                         if(hostvar != 0x1) {
                             CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
-                                       << "), stopping simulation";
+                                          << "), stopping simulation";
                         } else {
                             CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
-                                      << "), stopping simulation";
+                                         << "), stopping simulation";
                         }
                         this->reg.trap_state = std::numeric_limits<uint32_t>::max();
                         this->interrupt_sim = hostvar;
diff --git a/src/iss/debugger/riscv_target_adapter.h b/src/iss/debugger/riscv_target_adapter.h
index ac85a67..7e18339 100644
--- a/src/iss/debugger/riscv_target_adapter.h
+++ b/src/iss/debugger/riscv_target_adapter.h
@@ -329,7 +329,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(break_type
         auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
         target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
         CPPLOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex << saddr.val
-                   << std::dec;
+                      << std::dec;
         CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
         return Ok;
     }
diff --git a/src/vm/asmjit/vm_tgc5c.cpp b/src/vm/asmjit/vm_tgc5c.cpp
index 84b4a7e..6a6033c 100644
--- a/src/vm/asmjit/vm_tgc5c.cpp
+++ b/src/vm/asmjit/vm_tgc5c.cpp
@@ -4607,9 +4607,9 @@ std::unique_ptr<vm_if> create<arch::tgc5c>(arch::tgc5c *core, unsigned short por
 } // namespace asmjit
 } // namespace iss
 
-#include <iss/factory.h>
 #include <iss/arch/riscv_hart_m_p.h>
 #include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/factory.h>
 namespace iss {
 namespace {
 volatile std::array<bool, 2> dummy = {