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DBT-RISE-TGC
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corrects gen_sync update order, improves illegal instruction

This commit is contained in:
Eyck-Alexander Jentzsch 2024-07-17 20:52:01 +02:00
parent 244bf6d2f2
commit b24965d321
2 changed files with 199 additions and 181 deletions
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15
gen_input/templates/llvm/CORENAME.cpp.gtl
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@ -170,13 +170,13 @@ private:
auto cur_pc_val = this->gen_const(32,pc.val); auto cur_pc_val = this->gen_const(32,pc.val);
pc=pc+ ${instr.length/8}; pc=pc+ ${instr.length/8};
this->gen_set_pc(pc, traits::NEXT_PC); this->gen_set_pc(pc, traits::NEXT_PC);
this->set_tval(PC); this->set_tval(instr);
/*generate behavior*/ /*generate behavior*/
<%instr.behavior.eachLine{%>${it} <%instr.behavior.eachLine{%>${it}
<%}%> <%}%>
this->gen_sync(POST_SYNC, ${idx});
this->gen_instr_epilogue(bb); this->gen_instr_epilogue(bb);
this->gen_sync(POST_SYNC, ${idx});
this->builder.CreateBr(bb); this->builder.CreateBr(bb);
return returnValue; return returnValue;
} }
@ -185,6 +185,15 @@ private:
* end opcode definitions * end opcode definitions
****************************************************************************/ ****************************************************************************/
std::tuple<continuation_e, BasicBlock *> illegal_instruction(virt_addr_t &pc, code_word_t instr, BasicBlock *bb) { std::tuple<continuation_e, BasicBlock *> illegal_instruction(virt_addr_t &pc, code_word_t instr, BasicBlock *bb) {
if(this->disass_enabled){
auto mnemonic = std::string("illegal_instruction");
std::vector<Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(mnemonic),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
this->gen_sync(iss::PRE_SYNC, instr_descr.size()); this->gen_sync(iss::PRE_SYNC, instr_descr.size());
this->builder.CreateStore(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), true), this->builder.CreateStore(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), true),
get_reg_ptr(traits::PC), true); get_reg_ptr(traits::PC), true);
@ -193,6 +202,7 @@ private:
this->gen_const(64U, 1)), this->gen_const(64U, 1)),
get_reg_ptr(traits::ICOUNT), true); get_reg_ptr(traits::ICOUNT), true);
pc = pc + ((instr & 3) == 3 ? 4 : 2); pc = pc + ((instr & 3) == 3 ? 4 : 2);
this->set_tval(instr);
this->gen_raise_trap(0, 2); // illegal instruction trap this->gen_raise_trap(0, 2); // illegal instruction trap
this->gen_sync(iss::POST_SYNC, instr_descr.size()); this->gen_sync(iss::POST_SYNC, instr_descr.size());
this->gen_instr_epilogue(this->leave_blk); this->gen_instr_epilogue(this->leave_blk);
@ -341,7 +351,6 @@ inline void vm_impl<ARCH>::set_tval(Value* new_tval) {
template <typename ARCH> template <typename ARCH>
void vm_impl<ARCH>::gen_trap_behavior(BasicBlock *trap_blk) { void vm_impl<ARCH>::gen_trap_behavior(BasicBlock *trap_blk) {
this->builder.SetInsertPoint(trap_blk); this->builder.SetInsertPoint(trap_blk);
this->gen_sync(POST_SYNC, -1); //TODO get right InstrId
auto *trap_state_val = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true); auto *trap_state_val = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true);
this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
get_reg_ptr(traits::LAST_BRANCH), false); get_reg_ptr(traits::LAST_BRANCH), false);

365
src/vm/llvm/vm_tgc5c.cpp
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