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DBT-RISE-TGC
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add tgc_c_xrb_nn to tgc-sim

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Eyck Jentzsch 2022-02-02 21:33:42 +01:00
parent 68b5697c8f
commit ac86f14a54
1 changed files with 11 additions and 0 deletions
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11
src/main.cpp
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@ -44,6 +44,11 @@ using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
#include "iss/arch/tgc_b.h" #include "iss/arch/tgc_b.h"
using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>; using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
#endif #endif
#ifdef CORE_TGC_C_XRB_NN
#include "iss/arch/riscv_hart_m_p.h"
#include "iss/arch/tgc_c_xrb_nn.h"
using tgc_c_xrb_nn_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c_xrb_nn>;
#endif
#ifdef CORE_TGC_D #ifdef CORE_TGC_D
#include "iss/arch/riscv_hart_mu_p.h" #include "iss/arch/riscv_hart_mu_p.h"
#include "iss/arch/tgc_d.h" #include "iss/arch/tgc_d.h"
@ -152,6 +157,12 @@ int main(int argc, char *argv[]) {
iss::create_cpu<tgc_b_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>()); iss::create_cpu<tgc_b_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
} else } else
#endif #endif
#ifdef CORE_TGC_C_XRB_NN
if (isa_opt == "tgc_c_xrb_nn") {
std::tie(cpu, vm) =
iss::create_cpu<tgc_c_xrb_nn_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
} else
#endif
#ifdef CORE_TGC_D #ifdef CORE_TGC_D
if (isa_opt == "tgc_d") { if (isa_opt == "tgc_d") {
std::tie(cpu, vm) = std::tie(cpu, vm) =